Kinda working

src/regs/verilog6502_io_regs.sv

@@ -87,6 +87,7 @@ module verilog6502_io_regs (
     //--------------------------------------------------------------------------
     typedef struct {
         logic core_ctrl;
+        logic nmi;
         logic reset_brq;
     } decoded_reg_strb_t;
     decoded_reg_strb_t decoded_reg_strb;
@@ -103,6 +104,7 @@ module verilog6502_io_regs (
         is_valid_addr = '1; // No valid address check
         is_valid_rw = '1; // No valid RW check
         decoded_reg_strb.core_ctrl = cpuif_req_masked & (cpuif_addr == 12'h0);
+        decoded_reg_strb.nmi = cpuif_req_masked & (cpuif_addr == 12'hff8);
         decoded_reg_strb.reset_brq = cpuif_req_masked & (cpuif_addr == 12'hffc);
         decoded_err = '0;
     end
@@ -124,6 +126,12 @@ module verilog6502_io_regs (
                 logic load_next;
             } reset;
         } core_ctrl;
+        struct {
+            struct {
+                logic [15:0] next;
+                logic load_next;
+            } nmi;
+        } nmi;
         struct {
             struct {
                 logic [15:0] next;
@@ -143,6 +151,11 @@ module verilog6502_io_regs (
                 logic value;
             } reset;
         } core_ctrl;
+        struct {
+            struct {
+                logic [15:0] value;
+            } nmi;
+        } nmi;
         struct {
             struct {
                 logic [15:0] value;
@@ -177,6 +190,29 @@ module verilog6502_io_regs (
         end
     end
     assign hwif_out.core_ctrl.reset.value = field_storage.core_ctrl.reset.value;
+    // Field: verilog6502_io_regs.nmi.nmi
+    always_comb begin
+        automatic logic [15:0] next_c;
+        automatic logic load_next_c;
+        next_c = field_storage.nmi.nmi.value;
+        load_next_c = '0;
+        if(decoded_reg_strb.nmi && decoded_req_is_wr) begin // SW write
+            next_c = (field_storage.nmi.nmi.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]);
+            load_next_c = '1;
+        end
+        field_combo.nmi.nmi.next = next_c;
+        field_combo.nmi.nmi.load_next = load_next_c;
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.nmi.nmi.value <= 16'h200;
+        end else begin
+            if(field_combo.nmi.nmi.load_next) begin
+                field_storage.nmi.nmi.value <= field_combo.nmi.nmi.next;
+            end
+        end
+    end
+    assign hwif_out.nmi.nmi.value = field_storage.nmi.nmi.value;
     // Field: verilog6502_io_regs.reset_brq.reset
     always_comb begin
         automatic logic [15:0] next_c;
@@ -247,6 +283,9 @@ module verilog6502_io_regs (
         if(rd_mux_addr == 12'h0) begin
             readback_data_var[0] = field_storage.core_ctrl.reset.value;
         end
+        if(rd_mux_addr == 12'hff8) begin
+            readback_data_var[31:16] = field_storage.nmi.nmi.value;
+        end
         if(rd_mux_addr == 12'hffc) begin
             readback_data_var[15:0] = field_storage.reset_brq.reset.value;
             readback_data_var[31:16] = field_storage.reset_brq.brk.value;