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Kinda working

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This commit is contained in:
Byron Lathi
2026-04-18 16:18:57 -07:00
parent 50f8791588
commit 756b96d9e2
9 changed files with 143 additions and 17 deletions
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12
src/verilog6502_addr_decoder.sv
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@@ -6,9 +6,8 @@ module verilog6502_addr_decoder(
input logic [7:0] i_cpu_data,
output logic [7:0] o_cpu_data,
input logic i_cpu_we,
/* verilator lint_off UNOPTFLAT */
input logic i_cpu_rdy,
output logic o_cpu_rdy,
/* verilator lint_on UNOPTFLAT */
output logic [15:0] o_mem_addr,
@@ -95,28 +94,23 @@ always_comb begin
o_mem_we = i_cpu_we & o_cpu_rdy;
o_mem_rd = ~i_cpu_we & o_cpu_rdy;
prev_addr_next = MEM;
// o_cpu_rdy = i_mem_rdy;
// o_cpu_data = i_mem_data;
end else if (i_cpu_addr < 16'hF000) begin
o_external_addr = {4'b0, i_cpu_addr[11:0]};
o_external_data = i_cpu_data;
o_external_we = i_cpu_we & o_cpu_rdy;
o_external_rd = ~i_cpu_we & o_cpu_rdy;
prev_addr_next = EXT;
// o_cpu_rdy = i_external_rdy;
// o_cpu_data = i_external_data;
end else begin
o_io_addr = {4'b0, i_cpu_addr[11:0]};
o_io_data = i_cpu_data;
o_io_we = i_cpu_we & o_cpu_rdy;
o_io_rd = ~i_cpu_we & o_cpu_rdy;
prev_addr_next = IO;
// o_cpu_rdy = i_io_rdy;
// o_cpu_data = i_io_data;
end
end
if (i_rst) begin
if (i_rst | ~i_cpu_rdy) begin
prev_addr_next = NONE;
o_mem_rd = 0;
o_mem_we = 0;
o_external_rd = 0;