564 lines
25 KiB
Verilog
564 lines
25 KiB
Verilog
/////////////////////////////////////////////////////////////////////////////
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// _____
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// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
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// / / \
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// / / .. /
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// / / .' /
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// __/ /.' /
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// __ \ /
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// /_/ /\ \_____/ /
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// ____/ \_______/
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//
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// *******************************
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// Revisions:
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// 1.0 Initial rev
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//
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// *******************************
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`timescale 1 ns / 1 ns
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//`include "header.v" // use JTAG hard block
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module temac_ex
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(
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//Globle Signals
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//----pll_0
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input clk,
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input clk_125m,
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input pll_0_locked,
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input sw6,
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output wire pll_rstn,
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//TEMAC PHY RGMII Interface
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output wire [3:0] rgmii_txd_HI,
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output wire [3:0] rgmii_txd_LO,
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output wire rgmii_txc_HI,
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output wire rgmii_txc_LO,
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input [3:0] rgmii_rxd_HI,
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input [3:0] rgmii_rxd_LO,
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`ifdef TITANIUM
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output wire rgmii_tx_ctl_HI,
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output wire rgmii_tx_ctl_LO,
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input rgmii_rx_ctl_HI,
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input rgmii_rx_ctl_LO,
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input mux_clk,
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output [1:0] mux_clk_sw,
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`else
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input rgmii_rxc,
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output wire rgmii_tx_ctl,
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input rgmii_rx_ctl,
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`endif
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//TEMAC PHY Ctr Interface
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output wire phy_rstn,
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//hardware Jtag Interface
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`ifndef SIM_MODE
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`ifndef SOFT_TAP
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input jtag_inst1_TCK,
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input jtag_inst1_TDI,
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output wire jtag_inst1_TDO,
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input jtag_inst1_SEL,
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input jtag_inst1_CAPTURE,
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input jtag_inst1_SHIFT,
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input jtag_inst1_UPDATE,
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input jtag_inst1_RESET,
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`else
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//software Jtag Interface
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input io_jtag_tms,
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input io_jtag_tdi,
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output wire io_jtag_tdo,
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input io_jtag_tck,
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`endif
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//Debug Signals
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//output wire [1:0] debug_led
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output wire system_uart_0_io_txd,
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input system_uart_0_io_rxd,
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`endif
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output system_spi_0_io_sclk_write,
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output system_spi_0_io_data_0_writeEnable,
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input system_spi_0_io_data_0_read,
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output system_spi_0_io_data_0_write,
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output system_spi_0_io_data_1_writeEnable,
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input system_spi_0_io_data_1_read,
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output system_spi_0_io_data_1_write,
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output system_spi_0_io_ss,
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//TEMAC PHY MDIO Interface
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input phy_mdi,
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output wire phy_mdo,
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output wire phy_mdo_en,
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output wire phy_mdc
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);
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// Parameter Define
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`include "gTSE_define.svh"
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// Register Define
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// Wire Define
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wire clk_50m;
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wire clk_50m_rstn;
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wire mac_reset;
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wire proto_reset;
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wire mac_rstn;
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//AXI4-Stream Interface
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wire rx_axis_clk;
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wire [7:0] rx_axis_mac_tdata;
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wire rx_axis_mac_tvalid;
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wire rx_axis_mac_tlast;
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wire rx_axis_mac_tuser;
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wire rx_axis_mac_tready;
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wire tx_axis_clk;
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wire [7:0] tx_axis_mac_tdata;
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wire tx_axis_mac_tvalid;
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wire tx_axis_mac_tlast;
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wire tx_axis_mac_tuser;
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wire tx_axis_mac_tready;
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wire [7:0] udp_tx_axis_mac_tdata;
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wire udp_tx_axis_mac_tvalid;
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wire udp_tx_axis_mac_tlast;
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wire udp_tx_axis_mac_tready;
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wire [7:0] mac_tx_axis_mac_tdata;
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wire mac_tx_axis_mac_tvalid;
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wire mac_tx_axis_mac_tlast;
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wire mac_tx_axis_mac_tready;
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wire [7:0] pat_tx_axis_mac_tdata;
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wire pat_tx_axis_mac_tvalid;
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wire pat_tx_axis_mac_tlast;
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wire pat_tx_axis_mac_tuser;
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wire pat_tx_axis_mac_tready;
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wire [7:0] loop_tx_axis_mac_tdata;
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wire loop_tx_axis_mac_tvalid;
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wire loop_tx_axis_mac_tlast;
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wire loop_tx_axis_mac_tuser;
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wire loop_tx_axis_mac_tready;
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//RiscV APB3 Interface
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wire [15:0] apb3_paddr;
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wire apb3_psel;
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wire apb3_penable;
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wire apb3_pready;
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wire apb3_pwrite;
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wire [31:0] apb3_pwdata;
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wire [31:0] apb3_prdata;
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wire apb3_pslverror;
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//Mac APB3 Interface
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wire [9:0] mac_apb3_paddr;
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wire mac_apb3_psel;
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wire mac_apb3_penable;
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wire mac_apb3_pready;
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wire mac_apb3_pwrite;
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wire [31:0] mac_apb3_pwdata;
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wire [31:0] mac_apb3_prdata;
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wire mac_apb3_pslverror;
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//Ex APB3 Interface
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wire [9:0] ex_apb3_paddr;
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wire ex_apb3_psel;
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wire ex_apb3_penable;
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wire ex_apb3_pready;
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wire ex_apb3_pwrite;
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wire [31:0] ex_apb3_pwdata;
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wire [31:0] ex_apb3_prdata;
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wire ex_apb3_pslverror;
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//AXI4-Lite Interface
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wire [9:0] axi_awaddr;
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wire axi_awvalid;
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wire axi_awready;
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wire [31:0] axi_wdata;
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wire axi_wvalid;
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wire axi_wready;
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wire [1:0] axi_bresp;
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wire axi_bvalid;
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wire axi_bready;
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wire [9:0] axi_araddr;
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wire axi_arvalid;
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wire axi_arready;
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wire [1:0] axi_rresp;
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wire [31:0] axi_rdata;
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wire axi_rvalid;
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wire axi_rready;
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//Cfg Space Registers
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wire mac_sw_rst;
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wire axi4_st_mux_select;
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wire pat_mux_select;
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wire udp_pat_gen_en;
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wire mac_pat_gen_en;
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wire [15:0] pat_gen_num;
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wire [15:0] pat_gen_ipg;
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wire [47:0] pat_dst_mac;
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wire [47:0] pat_src_mac;
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wire [15:0] pat_mac_dlen;
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wire [31:0] pat_src_ip;
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wire [31:0] pat_dst_ip;
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wire [15:0] pat_src_port;
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wire [15:0] pat_dst_port;
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wire [15:0] pat_udp_dlen;
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//TSE DDIO
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`ifdef TITANIUM
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wire rgmii_rxc;
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assign rgmii_rxc = mux_clk;
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`else
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wire rgmii_rx_ctl_LO;
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wire rgmii_rx_ctl_HI;
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wire rgmii_tx_ctl_LO;
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wire rgmii_tx_ctl_HI;
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assign rgmii_tx_ctl = rgmii_tx_ctl_HI | rgmii_tx_ctl_LO ;
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assign rgmii_rx_ctl_HI = rgmii_rx_ctl ;
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assign rgmii_rx_ctl_LO = rgmii_rx_ctl ;
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`endif
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/*----------------------------------------------------------------------------------*\
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The main code
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\*----------------------------------------------------------------------------------*/
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assign pll_rstn = 1;
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/*----------------------- Clock Region -----------------------*/
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//In full throughput usecase, rx_axis_clk and tx_axis_clk should be set to 125Mhz or above.
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//In this example design, these clocks are set to 50Mhz because the UDP/MAC pattern generator has
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//high combi logic and couldn't meet timing at 125Mhz.
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assign rx_axis_clk = clk;//clk_125m;
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assign tx_axis_clk = clk;//clk_125m;
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/*----------------------- Reset Region -----------------------*/
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//assign pll_0_reset = 1'b0;
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assign clk_50m = clk;
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assign phy_rstn = sw6;
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assign clk_50m_rstn = pll_0_locked;
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assign mac_reset = ~pll_0_locked;
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assign proto_reset = mac_sw_rst;
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assign mac_rstn = ~(mac_reset || proto_reset);
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/*----------------------- MCU Module ----------------------------*/
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`ifndef SIM_MODE
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sapphire u_mcu
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(
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//user custom ports
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//SOC
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.io_systemClk (clk_50m ),
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.io_asyncReset (1'b0 ),
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.system_uart_0_io_txd (system_uart_0_io_txd ),
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.system_uart_0_io_rxd (system_uart_0_io_rxd ),
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.system_spi_0_io_sclk_write (system_spi_0_io_sclk_write ),
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.system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable ),
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.system_spi_0_io_data_0_read (system_spi_0_io_data_0_read ),
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.system_spi_0_io_data_0_write (system_spi_0_io_data_0_write ),
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.system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable ),
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.system_spi_0_io_data_1_read (system_spi_0_io_data_1_read ),
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.system_spi_0_io_data_1_write (system_spi_0_io_data_1_write ),
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.system_spi_0_io_ss (system_spi_0_io_ss ),
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.jtagCtrl_tck (jtag_inst1_TCK ),
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.jtagCtrl_tdi (jtag_inst1_TDI ),
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.jtagCtrl_tdo (jtag_inst1_TDO ),
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.jtagCtrl_enable (jtag_inst1_SEL ),
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.jtagCtrl_capture (jtag_inst1_CAPTURE ),
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.jtagCtrl_shift (jtag_inst1_SHIFT ),
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.jtagCtrl_update (jtag_inst1_UPDATE ),
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.jtagCtrl_reset (jtag_inst1_RESET ),
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//APB3 Master Interface
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.io_apbSlave_0_PADDR (apb3_paddr ),
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.io_apbSlave_0_PSEL (apb3_psel ),
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.io_apbSlave_0_PENABLE (apb3_penable ),
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.io_apbSlave_0_PREADY (apb3_pready ),
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.io_apbSlave_0_PWRITE (apb3_pwrite ),
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.io_apbSlave_0_PWDATA (apb3_pwdata ),
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.io_apbSlave_0_PRDATA (apb3_prdata ),
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.io_apbSlave_0_PSLVERROR (apb3_pslverror )
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);
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`endif
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assign apb3_pready = (apb3_paddr[9] == 1'b0) ? mac_apb3_pready : ex_apb3_pready;
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assign apb3_prdata = (apb3_paddr[9] == 1'b0) ? mac_apb3_prdata : ex_apb3_prdata;
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assign apb3_pslverror = (apb3_paddr[9] == 1'b0) ? mac_apb3_pslverror : ex_apb3_pslverror;
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assign mac_apb3_paddr = apb3_paddr[9:0];
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assign mac_apb3_psel = (apb3_paddr[9] == 1'b0) ? apb3_psel : 1'b0;
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assign mac_apb3_penable = apb3_penable;
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assign mac_apb3_pwrite = apb3_pwrite;
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assign mac_apb3_pwdata = apb3_pwdata;
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assign ex_apb3_paddr = apb3_paddr[9:0];
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assign ex_apb3_psel = (apb3_paddr[9] == 1'b1) ? apb3_psel : 1'b0;
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assign ex_apb3_penable = apb3_penable;
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assign ex_apb3_pwrite = apb3_pwrite;
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assign ex_apb3_pwdata = apb3_pwdata;
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apb3_2_axi4_lite#(
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.ADDR_WTH (10 )
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)
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u_apb3_2_axi4_lite
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(
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//Globle Signals
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.clk (clk_50m ),
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.rstn (clk_50m_rstn ),
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//APB3 Slave Interface
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.s_apb3_paddr (mac_apb3_paddr ),
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.s_apb3_psel (mac_apb3_psel ),
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.s_apb3_penable (mac_apb3_penable ),
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.s_apb3_pready (mac_apb3_pready ),
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.s_apb3_pwrite (mac_apb3_pwrite ),
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.s_apb3_pwdata (mac_apb3_pwdata ),
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.s_apb3_prdata (mac_apb3_prdata ),
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.s_apb3_pslverror (mac_apb3_pslverror ),
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//AXI4-Lite Master Interface
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.m_axi_awaddr (axi_awaddr ),
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.m_axi_awvalid (axi_awvalid ),
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.m_axi_awready (axi_awready ),
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.m_axi_wdata (axi_wdata ),
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.m_axi_wvalid (axi_wvalid ),
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.m_axi_wready (axi_wready ),
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.m_axi_bresp (axi_bresp ),
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.m_axi_bvalid (axi_bvalid ),
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.m_axi_bready (axi_bready ),
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.m_axi_araddr (axi_araddr ),
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.m_axi_arvalid (axi_arvalid ),
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.m_axi_arready (axi_arready ),
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.m_axi_rresp (axi_rresp ),
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.m_axi_rdata (axi_rdata ),
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.m_axi_rvalid (axi_rvalid ),
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.m_axi_rready (axi_rready )
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);
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reg_apb3#(
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.ADDR_WTH (10 )
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)
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u_reg_apb3
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(
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//Globle Signals
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//
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//APB3 Slave Interface
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.s_apb3_clk (clk_50m ),
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.s_apb3_rstn (clk_50m_rstn ),
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.s_apb3_paddr (ex_apb3_paddr ),
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.s_apb3_psel (ex_apb3_psel ),
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.s_apb3_penable (ex_apb3_penable ),
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.s_apb3_pready (ex_apb3_pready ),
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.s_apb3_pwrite (ex_apb3_pwrite ),
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.s_apb3_pwdata (ex_apb3_pwdata ),
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.s_apb3_prdata (ex_apb3_prdata ),
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.s_apb3_pslverror (ex_apb3_pslverror ),
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//Cfg Space Registers
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//--Example Registers Field
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.mac_sw_rst (mac_sw_rst ),
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.axi4_st_mux_select (axi4_st_mux_select ),
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.pat_mux_select (pat_mux_select ),
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.udp_pat_gen_en (udp_pat_gen_en ),
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.mac_pat_gen_en (mac_pat_gen_en ),
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.pat_gen_num (pat_gen_num ),
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.pat_gen_ipg (pat_gen_ipg ),
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.pat_dst_mac (pat_dst_mac ),
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.pat_src_mac (pat_src_mac ),
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.pat_mac_dlen (pat_mac_dlen ),
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.pat_src_ip (pat_src_ip ),
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.pat_dst_ip (pat_dst_ip ),
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.pat_src_port (pat_src_port ),
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.pat_dst_port (pat_dst_port ),
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.pat_udp_dlen (pat_udp_dlen ),
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.clkmux_sel (mux_clk_sw )
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);
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//generate if (PATTERN_TYPE == 0) begin //UDP
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//
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//assign mac_tx_axis_mac_tdata = 8'h0;
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//assign mac_tx_axis_mac_tvalid = 1'b0;
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//assign mac_tx_axis_mac_tlast = 1'b0;
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/*----------------------- The Ethernet Pattern Module -----------------------*/
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udp_pat_gen u_udp_pat_gen
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(
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//Globle Signals
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.clk (tx_axis_clk ),
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.rstn (mac_rstn ),
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//Control Interface
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.pat_gen_en (udp_pat_gen_en ),
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.pat_gen_num (pat_gen_num ),
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.pat_gen_ipg (pat_gen_ipg ),
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//MAC Protocol Signals
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.dst_mac (pat_dst_mac ),
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.src_mac (pat_src_mac ),
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//IP Protocol Signals
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.src_ip (pat_src_ip ),
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.dst_ip (pat_dst_ip ),
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//UDP Protocol Signals
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.src_port (pat_src_port ),
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.dst_port (pat_dst_port ),
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.udp_dlen (pat_udp_dlen ),
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//AXI4-Stream Interface
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.rclk (rx_axis_clk ),
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.rrstn (mac_rstn ),
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.rdata (rx_axis_mac_tdata ),
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.rvalid (rx_axis_mac_tvalid ),
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.rlast (rx_axis_mac_tlast ),
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.tdata (udp_tx_axis_mac_tdata ),
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.tvalid (udp_tx_axis_mac_tvalid ),
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.tlast (udp_tx_axis_mac_tlast ),
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.tready (udp_tx_axis_mac_tready )
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);
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//end
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//else begin //MAC
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//
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//assign udp_tx_axis_mac_tdata = 8'h0;
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//assign udp_tx_axis_mac_tvalid = 1'b0;
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//assign udp_tx_axis_mac_tlast = 1'b0;
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mac_pat_gen u_mac_pat_gen
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(
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//Globle Signals
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.clk (tx_axis_clk ),
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.rstn (mac_rstn ),
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//Control Interface
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.pat_gen_en (mac_pat_gen_en ),
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.pat_gen_num (pat_gen_num ),
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.pat_gen_ipg (pat_gen_ipg ),
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//MAC Protocol Signals
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.dst_mac (pat_dst_mac ),
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.src_mac (pat_src_mac ),
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.mac_dlen (pat_mac_dlen ),
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//AXI4-Stream Interface
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.rclk (rx_axis_clk ),
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.rrstn (mac_rstn ),
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.rdata (rx_axis_mac_tdata ),
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.rvalid (rx_axis_mac_tvalid ),
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.rlast (rx_axis_mac_tlast ),
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.tdata (mac_tx_axis_mac_tdata ),
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.tvalid (mac_tx_axis_mac_tvalid ),
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.tlast (mac_tx_axis_mac_tlast ),
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.tready (mac_tx_axis_mac_tready )
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);
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//end
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//endgenerate
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axi4_st_mux u_pat_mux
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(
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//Globle Signals
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.mux_select (pat_mux_select ),//0:udp pat; 1:mac pat;
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|
//Mux In 0 Interface
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.tdata0 (udp_tx_axis_mac_tdata ),
|
|
.tvalid0 (udp_tx_axis_mac_tvalid ),
|
|
.tlast0 (udp_tx_axis_mac_tlast ),
|
|
.tuser0 (1'b0 ),
|
|
.tready0 (udp_tx_axis_mac_tready ),
|
|
//Mux In 1 Interface
|
|
.tdata1 (mac_tx_axis_mac_tdata ),
|
|
.tvalid1 (mac_tx_axis_mac_tvalid ),
|
|
.tlast1 (mac_tx_axis_mac_tlast ),
|
|
.tuser1 (1'b0 ),
|
|
.tready1 (mac_tx_axis_mac_tready ),
|
|
//Mux Out Interface
|
|
.tdata (pat_tx_axis_mac_tdata ),
|
|
.tvalid (pat_tx_axis_mac_tvalid ),
|
|
.tlast (pat_tx_axis_mac_tlast ),
|
|
.tuser (pat_tx_axis_mac_tuser ),
|
|
.tready (pat_tx_axis_mac_tready )
|
|
);
|
|
|
|
/*----------------------- The Tx AXI4 St Mux Module -----------------------*/
|
|
axi4_st_mux u_tx_axi4st_mux
|
|
(
|
|
//Globle Signals
|
|
.mux_select (axi4_st_mux_select ),//0:pat; 1:rx2tx loopback;
|
|
//Mux In 0 Interface
|
|
.tdata0 (pat_tx_axis_mac_tdata ),
|
|
.tvalid0 (pat_tx_axis_mac_tvalid ),
|
|
.tlast0 (pat_tx_axis_mac_tlast ),
|
|
.tuser0 (pat_tx_axis_mac_tuser ),
|
|
.tready0 (pat_tx_axis_mac_tready ),
|
|
//Mux In 1 Interface
|
|
.tdata1 (loop_tx_axis_mac_tdata ),
|
|
.tvalid1 (loop_tx_axis_mac_tvalid ),
|
|
.tlast1 (loop_tx_axis_mac_tlast ),
|
|
.tuser1 (loop_tx_axis_mac_tuser ),
|
|
.tready1 (loop_tx_axis_mac_tready ),
|
|
//Mux Out Interface
|
|
.tdata (tx_axis_mac_tdata ),
|
|
.tvalid (tx_axis_mac_tvalid ),
|
|
.tlast (tx_axis_mac_tlast ),
|
|
.tuser (tx_axis_mac_tuser ),
|
|
.tready (tx_axis_mac_tready )
|
|
);
|
|
|
|
/*----------------------- The Tri-mode Ethernet MAC core -----------------------*/
|
|
gTSE u_tsemac
|
|
(
|
|
//Globle Signals
|
|
.mac_reset (mac_reset ),
|
|
.proto_reset (proto_reset ),
|
|
.tx_mac_aclk (clk_125m ),
|
|
.rx_mac_aclk ( ),
|
|
.eth_speed ( ),
|
|
//Receive AXI4-Stream Interface
|
|
.rx_axis_clk (rx_axis_clk ),
|
|
.rx_axis_mac_tdata (rx_axis_mac_tdata ),
|
|
.rx_axis_mac_tvalid (rx_axis_mac_tvalid ),
|
|
.rx_axis_mac_tlast (rx_axis_mac_tlast ),
|
|
.rx_axis_mac_tstrb (),
|
|
.rx_axis_mac_tuser (rx_axis_mac_tuser ),
|
|
.rx_axis_mac_tready (rx_axis_mac_tready ),
|
|
//Transmit AXI4-Stream Interface
|
|
.tx_axis_clk (tx_axis_clk ),
|
|
.tx_axis_mac_tdata (tx_axis_mac_tdata ),
|
|
.tx_axis_mac_tvalid (tx_axis_mac_tvalid ),
|
|
.tx_axis_mac_tlast (tx_axis_mac_tlast ),
|
|
.tx_axis_mac_tstrb (1'b1 ),
|
|
.tx_axis_mac_tuser (tx_axis_mac_tuser ),
|
|
.tx_axis_mac_tready (tx_axis_mac_tready ),
|
|
//--RGMII Interface
|
|
.rgmii_txd_HI (rgmii_txd_HI ),
|
|
.rgmii_txd_LO (rgmii_txd_LO ),
|
|
.rgmii_tx_ctl_HI (rgmii_tx_ctl_HI ),
|
|
.rgmii_tx_ctl_LO (rgmii_tx_ctl_LO ),
|
|
.rgmii_txc_HI (rgmii_txc_HI ),
|
|
.rgmii_txc_LO (rgmii_txc_LO ),
|
|
.rgmii_rxd_HI (rgmii_rxd_HI ),
|
|
.rgmii_rxd_LO (rgmii_rxd_LO ),
|
|
.rgmii_rx_ctl_HI (rgmii_rx_ctl_HI ),
|
|
.rgmii_rx_ctl_LO (rgmii_rx_ctl_LO ),
|
|
.rgmii_rxc (rgmii_rxc ),
|
|
//AXI4-Lite Interface
|
|
.s_axi_aclk (clk_50m ),
|
|
.s_axi_awaddr (axi_awaddr ),
|
|
.s_axi_awvalid (axi_awvalid ),
|
|
.s_axi_awready (axi_awready ),
|
|
.s_axi_wdata (axi_wdata ),
|
|
.s_axi_wvalid (axi_wvalid ),
|
|
.s_axi_wready (axi_wready ),
|
|
.s_axi_bresp (axi_bresp ),
|
|
.s_axi_bvalid (axi_bvalid ),
|
|
.s_axi_bready (axi_bready ),
|
|
.s_axi_araddr (axi_araddr ),
|
|
.s_axi_arvalid (axi_arvalid ),
|
|
.s_axi_arready (axi_arready ),
|
|
.s_axi_rresp (axi_rresp ),
|
|
.s_axi_rdata (axi_rdata ),
|
|
.s_axi_rvalid (axi_rvalid ),
|
|
.s_axi_rready (axi_rready ),
|
|
//MDIO Interface
|
|
.Mdo (phy_mdo ),
|
|
.MdoEn (phy_mdo_en ),
|
|
.Mdi (phy_mdi ),
|
|
.Mdc (phy_mdc )
|
|
);
|
|
|
|
/*----------------------- User Interface Loopback Module ----------------------------*/
|
|
mac_rx2tx u_mac_rx2tx
|
|
(
|
|
//Globle Signals
|
|
//
|
|
//Receive AXI4-Stream Interface
|
|
.rx_axis_clk (rx_axis_clk ),
|
|
.rx_axis_rstn (mac_rstn ),
|
|
.rx_axis_mac_tdata (rx_axis_mac_tdata ),
|
|
.rx_axis_mac_tvalid (rx_axis_mac_tvalid ),
|
|
.rx_axis_mac_tlast (rx_axis_mac_tlast ),
|
|
.rx_axis_mac_tuser (rx_axis_mac_tuser ),
|
|
.rx_axis_mac_tready (rx_axis_mac_tready ),
|
|
//Transmit AXI4-Stream Interface
|
|
.tx_axis_clk (tx_axis_clk ),
|
|
.tx_axis_rstn (mac_rstn ),
|
|
.tx_axis_mac_tdata (loop_tx_axis_mac_tdata ),
|
|
.tx_axis_mac_tvalid (loop_tx_axis_mac_tvalid ),
|
|
.tx_axis_mac_tlast (loop_tx_axis_mac_tlast ),
|
|
.tx_axis_mac_tuser (loop_tx_axis_mac_tuser ),
|
|
.tx_axis_mac_tready (loop_tx_axis_mac_tready )
|
|
);
|
|
|
|
endmodule
|
|
|