160 lines
4.0 KiB
Verilog
160 lines
4.0 KiB
Verilog
`timescale 1 ps / 1 ps
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`celldefine
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module ODDR (Q, C, CE, D1, D2, R, S);
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output Q;
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input C;
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input CE;
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input D1;
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input D2;
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input R;
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input S;
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parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
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parameter INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D1_INVERTED = 1'b0;
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parameter [0:0] IS_D2_INVERTED = 1'b0;
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parameter SRTYPE = "SYNC";
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parameter ROC_WIDTH = 100000;
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localparam MODULE_NAME = "ODDR";
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pulldown P1 (R);
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pulldown P2 (S);
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reg GSR;
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reg q_out = INIT, qd2_posedge_int;
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wire c_in,delay_c;
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wire ce_in,delay_ce;
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wire d1_in,delay_d1;
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wire d2_in,delay_d2;
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wire gsr_in;
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wire r_in,delay_r;
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wire s_in,delay_s;
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assign gsr_in = GSR;
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assign Q = q_out;
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initial begin
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GSR = 1'b1;
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#(ROC_WIDTH)
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GSR = 1'b0;
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end
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initial begin
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if ((INIT != 0) && (INIT != 1)) begin
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$display("Attribute Syntax Error : The attribute INIT on %s instance %m is set to %d. Legal values for this attribute are 0 or 1.", MODULE_NAME, INIT);
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#1 $finish;
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end
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if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin
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$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on %s instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", MODULE_NAME, DDR_CLK_EDGE);
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#1 $finish;
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end
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if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
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$display("Attribute Syntax Error : The attribute SRTYPE on %s instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", MODULE_NAME, SRTYPE);
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#1 $finish;
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end
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end // initial begin
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always @(gsr_in or r_in or s_in) begin
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if (gsr_in == 1'b1) begin
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assign q_out = INIT;
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assign qd2_posedge_int = INIT;
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end
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else if (gsr_in == 1'b0) begin
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if (r_in == 1'b1 && SRTYPE == "ASYNC") begin
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assign q_out = 1'b0;
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assign qd2_posedge_int = 1'b0;
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end
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else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
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assign q_out = 1'b1;
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assign qd2_posedge_int = 1'b1;
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end
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else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
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deassign q_out;
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deassign qd2_posedge_int;
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end
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else if (r_in == 1'b0 && s_in == 1'b0) begin
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deassign q_out;
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deassign qd2_posedge_int;
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end
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end // if (gsr_in == 1'b0)
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end // always @ (gsr_in or r_in or s_in)
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always @(posedge c_in) begin
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if (r_in == 1'b1) begin
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q_out <= 1'b0;
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qd2_posedge_int <= 1'b0;
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end
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else if (r_in == 1'b0 && s_in == 1'b1) begin
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q_out <= 1'b1;
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qd2_posedge_int <= 1'b1;
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end
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else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
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q_out <= d1_in;
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qd2_posedge_int <= d2_in;
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end
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// CR 527698
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else if (ce_in == 1'b0 && r_in == 1'b0 && s_in == 1'b0) begin
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qd2_posedge_int <= q_out;
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end
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end // always @ (posedge c_in)
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always @(negedge c_in) begin
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if (r_in == 1'b1)
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q_out <= 1'b0;
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else if (r_in == 1'b0 && s_in == 1'b1)
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q_out <= 1'b1;
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else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
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if (DDR_CLK_EDGE == "SAME_EDGE")
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q_out <= qd2_posedge_int;
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else if (DDR_CLK_EDGE == "OPPOSITE_EDGE")
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q_out <= d2_in;
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end
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end // always @ (negedge c_in)
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assign delay_c = C;
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assign delay_ce = CE;
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assign delay_d1 = D1;
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assign delay_d2 = D2;
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assign delay_r = R;
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assign delay_s = S;
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assign c_in = IS_C_INVERTED ^ delay_c;
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assign ce_in = delay_ce;
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assign d1_in = IS_D1_INVERTED ^ delay_d1;
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assign d2_in = IS_D2_INVERTED ^ delay_d2;
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assign r_in = delay_r;
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assign s_in = delay_s;
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//*** Timing Checks Start here
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specify
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(C => Q) = (100:100:100, 100:100:100);
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(posedge R => (Q +: 0)) = (0:0:0, 0:0:0);
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(posedge S => (Q +: 0)) = (0:0:0, 0:0:0);
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specparam PATHPULSE$ = 0;
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endspecify
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endmodule // ODDR
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`endcelldefine
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