140 lines
4.9 KiB
Verilog
140 lines
4.9 KiB
Verilog
/////////////////////////////////////////////////////////////////////////////
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// _____
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// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
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// / / \
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// / / .. /
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// / / .' /
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// __/ /.' /
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// __ \ /
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// /_/ /\ \_____/ /
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// ____/ \_______/
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//
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// *******************************
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// Revisions:
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// 1.0 Initial rev
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//
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// *******************************
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`timescale 1 ns / 1 ns
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module mac_rx2tx
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(
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//Globle Signals
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//
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//Receive AXI4-Stream Interface
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input rx_axis_clk,
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input rx_axis_rstn,
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input [7:0] rx_axis_mac_tdata,
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input rx_axis_mac_tvalid,
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input rx_axis_mac_tlast,
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input rx_axis_mac_tuser,
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output reg rx_axis_mac_tready,
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//Transmit AXI4-Stream Interface
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input tx_axis_clk,
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input tx_axis_rstn,
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output reg [7:0] tx_axis_mac_tdata,
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output reg tx_axis_mac_tvalid,
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output reg tx_axis_mac_tlast,
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output reg tx_axis_mac_tuser,
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input tx_axis_mac_tready
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);
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// Parameter Define
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// Register Define
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// Wire Define
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wire [9:0] u1_data;
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wire u1_wrreq;
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wire u1_rdreq;
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wire [9:0] u1_q;
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wire u1_empty;
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wire u1_almfull;
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wire [10:0] u1_wrcnt;
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/*----------------------------------------------------------------------------------*\
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The main code
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\*----------------------------------------------------------------------------------*/
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/*----------------------- Rx Clock Region ----------------------------*/
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assign u1_almfull = (u1_wrcnt >= 2045);
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always @(posedge rx_axis_clk or negedge rx_axis_rstn)
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begin
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if(rx_axis_rstn == 1'b0)
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rx_axis_mac_tready <= 1'b0;
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else if(u1_almfull == 1'b1)
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rx_axis_mac_tready <= 1'b0;
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else
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rx_axis_mac_tready <= 1'b1;
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end
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/*----------------------- Fifo 1 Region ----------------------------*/
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DC_FIFO #(
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.FIFO_MODE ("ShowAhead" ),
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.DATA_WIDTH (10 ),
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.FIFO_DEPTH (2048 )
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)
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u1
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(
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//System Signal
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.Reset (!rx_axis_rstn ),
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//Write Signal
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.WrClk (rx_axis_clk ),
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.WrEn (u1_wrreq ),
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.WrDNum (u1_wrcnt ),
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.WrFull ( ),
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.WrData (u1_data ),
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//Read Signal
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.RdClk (tx_axis_clk ),
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.RdEn (u1_rdreq ),
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.RdDNum ( ),
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.RdEmpty (u1_empty ),
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.RdData (u1_q )
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);
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assign u1_data = {rx_axis_mac_tuser,rx_axis_mac_tlast,rx_axis_mac_tdata};
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assign u1_wrreq = (rx_axis_mac_tvalid == 1'b1) && (rx_axis_mac_tready == 1'b1);
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assign u1_rdreq = (u1_empty == 1'b0) && ((tx_axis_mac_tvalid == 1'b0) || (tx_axis_mac_tready == 1'b1));
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/*----------------------- Tx Clock Region ----------------------------*/
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always @(posedge tx_axis_clk or negedge tx_axis_rstn)
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begin
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if(tx_axis_rstn == 1'b0)
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tx_axis_mac_tvalid <= 1'b0;
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else if(u1_rdreq == 1'b1)
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tx_axis_mac_tvalid <= 1'b1;
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else if(tx_axis_mac_tready == 1'b1)
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tx_axis_mac_tvalid <= 1'b0;
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end
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always @(posedge tx_axis_clk or negedge tx_axis_rstn)
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begin
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if(tx_axis_rstn == 1'b0)
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tx_axis_mac_tdata <= 8'h0;
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else if(u1_rdreq == 1'b1)
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tx_axis_mac_tdata <= u1_q[7:0];
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else if(tx_axis_mac_tready == 1'b1)
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tx_axis_mac_tdata <= 8'h0;
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end
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always @(posedge tx_axis_clk or negedge tx_axis_rstn)
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begin
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if(tx_axis_rstn == 1'b0)
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tx_axis_mac_tlast <= 1'b0;
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else if(u1_rdreq == 1'b1)
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tx_axis_mac_tlast <= u1_q[8];
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else if(tx_axis_mac_tready == 1'b1)
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tx_axis_mac_tlast <= 1'b0;
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end
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always @(posedge tx_axis_clk or negedge tx_axis_rstn)
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begin
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if(tx_axis_rstn == 1'b0)
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tx_axis_mac_tuser <= 1'b0;
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else if((u1_rdreq == 1'b1) && (u1_q[8] == 1'b1))
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tx_axis_mac_tuser <= u1_q[9];
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else if(tx_axis_mac_tready == 1'b1)
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tx_axis_mac_tuser <= 1'b0;
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end
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endmodule
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