36 lines
1.1 KiB
Systemverilog
36 lines
1.1 KiB
Systemverilog
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
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// https://github.com/SystemRDL/PeakRDL-regblock
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package verilog6502_io_regs_pkg;
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localparam VERILOG6502_IO_REGS_DATA_WIDTH = 32;
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localparam VERILOG6502_IO_REGS_MIN_ADDR_WIDTH = 12;
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localparam VERILOG6502_IO_REGS_SIZE = 'h1000;
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typedef struct {
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logic value;
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} verilog6502_io_regs__core_ctrl__reset__out_t;
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typedef struct {
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verilog6502_io_regs__core_ctrl__reset__out_t reset;
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} verilog6502_io_regs__core_ctrl__out_t;
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typedef struct {
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logic [15:0] value;
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} verilog6502_io_regs__reset_brq__reset__out_t;
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typedef struct {
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logic [15:0] value;
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} verilog6502_io_regs__reset_brq__brk__out_t;
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typedef struct {
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verilog6502_io_regs__reset_brq__reset__out_t reset;
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verilog6502_io_regs__reset_brq__brk__out_t brk;
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} verilog6502_io_regs__reset_brq__out_t;
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typedef struct {
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verilog6502_io_regs__core_ctrl__out_t core_ctrl;
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verilog6502_io_regs__reset_brq__out_t reset_brq;
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} verilog6502_io_regs__out_t;
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endpackage
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