832 lines
30 KiB
Verilog
832 lines
30 KiB
Verilog
/////////////////////////////////////////////////////////////////////////////
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// _____
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// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
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// / / \
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// / / .. /
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// / / .' /
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// __/ /.' /
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// __ \ /
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// /_/ /\ \_____/ /
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// ____/ \_______/
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//
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// *******************************
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// Revisions:
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// 1.0 Initial rev
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//
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// *******************************
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`timescale 1 ns/100ps
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`define SIM_MODE
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`define RXFIFO_EN 1
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`define RXFIFO_DTH 2048
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`define TXFIFO_EN 1
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`define TXFIFO_DTH 2048
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module tb_top(
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);
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`include "gTSE_define.svh"
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// Parameter Define
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parameter TSET_CASE = 1;//Values range from "1" to "9"
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parameter MAC_SPEED = 2;//4:1000M; 2:100M; 1:10M;
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parameter PAT_TYPE = 1;//0:UDP Pattern; 1:MAC Pattern;
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parameter DST_MAC_H = 16'habcd;
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parameter DST_MAC_L = 32'hef22_1100;
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parameter SRC_MAC_H = 16'heae8;
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parameter SRC_MAC_L = 32'h5e00_60c8;
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parameter MAC_DLEN = 16'd64;
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parameter SRC_IP = 32'hc0a80164;
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parameter DST_IP = 32'hc0a80165;
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parameter SRC_PORT = 16'h0521;
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parameter DST_PORT = 16'h2715;
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parameter UDP_DLEN = 16'h64;
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// Register Define
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reg Reset;
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reg clk_50m=0;
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reg clk_125m=0;
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reg clk_25m=0;
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reg clk_2m5=0;
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reg err_ins=0;
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//--mac_reg command_config
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reg tx_ena=0;
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reg rx_ena=0;
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reg xon_gen=0;
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reg promis_en=0;
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reg pad_en=0;
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reg crc_fwd=0;
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reg pause_ignore=0;
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reg tx_addr_ins=0;
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reg sw_reset=0;
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reg loop_ena=0;
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reg [2:0] eth_speed=0;
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reg xoff_gen=0;
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reg cnt_reset=0;
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//--APB3 Interface
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reg [9:0] m_apb3_paddr=0;
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reg m_apb3_psel=0;
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reg m_apb3_penable=0;
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reg m_apb3_pwrite=0;
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reg [31:0] m_apb3_pwdata=0;
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// Wire Define
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wire [31:0] mac_command_config;
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//--Transmit AXI4-Stream Interface
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wire tx_axis_clk;
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wire [7:0] tx_axis_mac_tdata;
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wire tx_axis_mac_tvalid;
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wire tx_axis_mac_tlast;
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wire tx_axis_mac_tuser;
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wire tx_axis_mac_tready;
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//--APB3 Interface
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wire m_apb3_pready;
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wire [31:0] m_apb3_prdata;
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wire m_apb3_pslverror;
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//--AXI4-Lite Interface
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wire [9:0] axi_awaddr;
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wire axi_awvalid;
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wire axi_awready;
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wire [31:0] axi_wdata;
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wire axi_wvalid;
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wire axi_wready;
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wire [1:0] axi_bresp;
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wire axi_bvalid;
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wire axi_bready;
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wire [9:0] axi_araddr;
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wire axi_arvalid;
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wire axi_arready;
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wire [1:0] axi_rresp;
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wire [31:0] axi_rdata;
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wire axi_rvalid;
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wire axi_rready;
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//--RGMII Interface
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wire [3:0] rgmii_txd_HI;
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wire [3:0] rgmii_txd_LO;
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wire rgmii_tx_ctl;
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wire rgmii_txc_HI;
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wire rgmii_txc_LO;
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wire rgmii_txc;
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wire [3:0] rgmii_rxd_HI;
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wire [3:0] rgmii_rxd_LO;
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wire rgmii_rx_ctl;
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wire rgmii_rxc;
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wire rx_data_rlast;
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wire udp_rx_data_rlast;
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wire rx_data_ruser;
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integer i;
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//-----------------------------------------------------------------------------------//
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// THE Sim Behavior
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//-----------------------------------------------------------------------------------//
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initial
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begin
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//$shm_open("test.shm");
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//$shm_probe(tb_top,"ACMTF");
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Reset <=1;
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#20
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Reset <=0;
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init_task();
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if(TSET_CASE == 1)
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test_case_1_task();
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else if(TSET_CASE == 2)
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test_case_2_task();
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else if(TSET_CASE == 3)
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test_case_3_task();
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else if(TSET_CASE == 4)
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test_case_4_task();
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else if(TSET_CASE == 5)
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test_case_5_task();
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else if(TSET_CASE == 6)
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test_case_6_task();
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else if(TSET_CASE == 7)
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test_case_7_task();
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else if(TSET_CASE == 8)
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test_case_8_task();
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else if(TSET_CASE == 9)
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test_case_9_task();
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#5000
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$display("TEST PASSED");
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$finish(1);
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end
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//-----------------------------------------------------------------------------------//
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// THE Clock Generate
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//-----------------------------------------------------------------------------------//
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always clk_50m = #(10) ~clk_50m;
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always clk_2m5 = #(200) ~clk_2m5;
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always clk_25m = #(20) ~clk_25m;
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always clk_125m = #(4) ~clk_125m;
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//-----------------------------------------------------------------------------------//
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// THE Sim Condition
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//-----------------------------------------------------------------------------------//
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assign u_temac_ex.apb3_paddr = m_apb3_paddr;
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assign u_temac_ex.apb3_psel = m_apb3_psel;
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assign u_temac_ex.apb3_penable = m_apb3_penable;
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assign m_apb3_pready = u_temac_ex.apb3_pready;
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assign u_temac_ex.apb3_pwrite = m_apb3_pwrite;
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assign u_temac_ex.apb3_pwdata = m_apb3_pwdata;
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assign m_apb3_prdata = u_temac_ex.apb3_prdata;
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assign m_apb3_pslverror = u_temac_ex.apb3_pslverror;
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assign rx_data_rlast = u_temac_ex.u_mac_pat_gen.rlast;
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assign rx_data_ruser = u_temac_ex.rx_axis_mac_tlast;
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assign udp_rx_data_rlast = u_temac_ex.u_udp_pat_gen.rlast;
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assign mac_command_config = {cnt_reset,7'h0,
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1'h0,xoff_gen,3'h0,eth_speed[2:0],
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loop_ena,1'h0,sw_reset,3'h0,tx_addr_ins,pause_ignore,
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1'h0,crc_fwd,pad_en,promis_en,1'h0,xon_gen,rx_ena,tx_ena};
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assign rgmii_rxd_HI = (err_ins) ? 4'h0 : rgmii_txd_LO;
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assign rgmii_rxd_LO = (err_ins) ? 4'h0 : rgmii_txd_HI;
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assign rgmii_rx_ctl = rgmii_tx_ctl;
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assign rgmii_rxc = rgmii_txc;
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reg [7:0] rx_data_cnt;
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reg rdata_mismatch;
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always @(posedge clk_125m or negedge Reset)
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begin
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if(Reset == 1'b0)
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rx_data_cnt <= 8'h0;
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else if(u_temac_ex.rx_axis_mac_tlast)
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rx_data_cnt <= 8'h0;
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else if(u_temac_ex.rx_axis_mac_tvalid)
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rx_data_cnt <= rx_data_cnt + 1'b1;
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end
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always @(posedge clk_125m or negedge Reset)
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begin
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if(Reset == 1'b0)
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rdata_mismatch <= 1'b0;
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else if (u_temac_ex.rx_axis_mac_tlast)
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rdata_mismatch <= 1'b0;
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else if(u_temac_ex.rx_axis_mac_tvalid && rx_data_cnt >= 8'd42) begin
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if ((rx_data_cnt - u_temac_ex.rx_axis_mac_tdata) != 8'd42)
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rdata_mismatch <= 1'b1;
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end
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end
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//-----------------------------------------------------------------------------------//
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// THE DUT RX
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//-----------------------------------------------------------------------------------//
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temac_ex u_temac_ex
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(
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//Globle Signals
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//----pll_0
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//output wire pll_0_reset,
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.clk (clk_50m ),
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.clk_125m (clk_125m ),
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.pll_0_locked (!Reset ),
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.sw6 (),
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//TEMAC PHY RGMII Interface
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.rgmii_txd_HI (rgmii_txd_HI ),
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.rgmii_txd_LO (rgmii_txd_LO ),
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.rgmii_tx_ctl (rgmii_tx_ctl ),
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.rgmii_txc_HI (rgmii_txc_HI ),
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.rgmii_txc_LO (rgmii_txc_LO ),
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.rgmii_rxd_HI (rgmii_rxd_HI ),
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.rgmii_rxd_LO (rgmii_rxd_LO ),
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.rgmii_rx_ctl (rgmii_rx_ctl ),
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.rgmii_rxc (rgmii_rxc ),
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//TEMAC PHY MDIO Interface
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.phy_mdi (1'b0 ),
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.phy_mdo ( ),
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.phy_mdo_en ( ),
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.phy_mdc ( )
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);
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/*----------------------- ODDR Region ----------------------------*/
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//rgmii_txc
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ODDR #(
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.DDR_CLK_EDGE ("SAME_EDGE" )// "OPPOSITE_EDGE" or "SAME_EDGE"
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) rgmii_txc_ddr (
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.Q (rgmii_txc ),// 1-bit DDR output
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.C (clk_125m ),// 1-bit clock input
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.CE (1'b1 ),// 1-bit clock enable input
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.D1 (rgmii_txc_HI ),// 1-bit data input (positive edge)
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.D2 (rgmii_txc_LO ),// 1-bit data input (negative edge)
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.R (1'b0 ),// 1-bit reset
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.S (1'b0 )// 1-bit set
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);
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//-----------------------------------------------------------------------------------//
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// THE Base Task
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//-----------------------------------------------------------------------------------//
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//apb3 bus wr task
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task apb3_wr;
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input [9:0] awaddr;
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input [31:0] wdata;
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begin
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@(posedge clk_50m);
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m_apb3_paddr <= awaddr;
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m_apb3_pwrite <= 1'b1;
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m_apb3_psel <= 1'b1;
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m_apb3_pwdata <= wdata;
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@(posedge clk_50m);
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m_apb3_penable <= 1;
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wait(m_apb3_pready);
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@(posedge clk_50m);
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m_apb3_paddr <= 0;
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m_apb3_pwrite <= 0;
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m_apb3_psel <= 0;
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m_apb3_pwdata <= 1'b0;
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m_apb3_penable <= 0;
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@(posedge clk_50m);
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end
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endtask
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//apb3 bus rd task
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task apb3_rd;
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input [9:0] araddr;
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begin
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@(posedge clk_50m);
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m_apb3_paddr <= araddr;
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m_apb3_pwrite <= 1'b0;
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m_apb3_psel <= 1'b1;
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@(posedge clk_50m);
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m_apb3_penable <= 1;
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wait(m_apb3_pready);
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@(posedge clk_50m);
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m_apb3_paddr <= 0;
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m_apb3_pwrite <= 0;
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m_apb3_psel <= 0;
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m_apb3_penable <= 0;
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@(posedge clk_50m);
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end
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endtask
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//initial task
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task init_task;
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begin
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//initial mac_reg
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tx_ena <= 1'h1;
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rx_ena <= 1'h1;
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xon_gen <= 1'h0;
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promis_en <= 1'h0;
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pad_en <= 1'h0;
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crc_fwd <= 1'h0;
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pause_ignore <= 1'h0;
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tx_addr_ins <= 1'h0;
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sw_reset <= 1'h0;
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loop_ena <= 1'h0;
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eth_speed[2:0] <= MAC_SPEED;
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xoff_gen <= 1'h0;
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cnt_reset <= 1'h0;
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@(posedge clk_50m);
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$display("---- Configure TSE MAC IP register setting ----");
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apb3_wr('h2*4,mac_command_config);//mac_reg command_config
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//initial ex_reg
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apb3_wr('h84*4,DST_MAC_L);//ex_reg pat_dst_mac[31:0]
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apb3_wr('h85*4,DST_MAC_H);//ex_reg pat_dst_mac[47:32]
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apb3_wr('h86*4,SRC_MAC_L);//ex_reg pat_src_mac[31:0]
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apb3_wr('h87*4,SRC_MAC_H);//ex_reg pat_src_mac[47:32]
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apb3_wr('h89*4,SRC_IP);//ex_reg pat_src_ip
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apb3_wr('h8a*4,DST_IP);//ex_reg pat_dst_ip
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apb3_wr('h8b*4,{DST_PORT,SRC_PORT});//ex_reg pat_dst_port & pat_src_port
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if(PAT_TYPE == 1'b0)
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begin
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apb3_wr('h81*4,32'h0);//ex_reg pat_mux_select & axi4_st_mux_select
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end
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else
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begin
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apb3_wr('h81*4,32'h2);//ex_reg pat_mux_select & axi4_st_mux_select
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end
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end
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endtask
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//pause frame generator task
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task pause_gen_task;
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input [15:0] pause_quant;
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begin
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apb3_wr('h6*4,pause_quant);//mac_reg pause_quant
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xoff_gen <= 1'h1;
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@(posedge clk_50m);
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apb3_wr('h2*4,mac_command_config);//mac_reg command_config
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wait(u_temac_ex.u_tsemac.u_efx_mac1gbe.inst_tsemac.u_tsemac.u_tx_engine.u_tx_ctr.cur_state == 4'd4);
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xoff_gen <= 1'h0;
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@(posedge clk_50m);
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apb3_wr('h2*4,mac_command_config);//mac_reg command_config
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end
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endtask
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task check_rdata_task;
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input integer i;
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input [1:0] check_error_bit;
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begin
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while (rx_data_rlast == 0) @(posedge clk_125m);
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if (check_error_bit == 2'b01) begin
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apb3_rd('h22*4); // read ifInErrors
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if (|m_apb3_prdata == 0) begin
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$display("%t - Error: Expecting MAC packet ifInErrors to go high, ifInErrors = %h", $time, m_apb3_prdata);
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$fatal("FAIL: simulation fail");
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end
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else begin
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$display("%t - Correct MAC packet %d, received", $time, i);
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end
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end
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else if (check_error_bit == 2'b10) begin
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if (rx_data_ruser == 0) begin
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$display("%t - Error: Expecting MAC packet rx_data_ruser to go high, rx_data_ruser = %h", $time, rx_data_ruser);
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$fatal("FAIL: simulation fail");
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end
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else begin
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$display("%t - MAC packet %d is filtered", $time, i);
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end
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end
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else begin
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apb3_rd('h22*4); // read ifInErrors
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if (rdata_mismatch != 0) begin
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$display("%t - Error: Received data mismatch", $time);
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$fatal("FAIL: simulation fail");
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end
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if (|m_apb3_prdata != 0) begin
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$display("%t - Error: There is an Error in the MAC received packet, ifInErrors = %h", $time, m_apb3_prdata);
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$fatal("FAIL: simulation fail");
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end
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else begin
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$display("%t - Correct MAC packet %d, received", $time, i);
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end
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end
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end
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endtask
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task check_udp_rdata_task;
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input integer i;
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input [1:0] check_error_bit;
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begin
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while (rx_data_rlast == 0) @(posedge clk_125m);
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if (check_error_bit == 2'b01) begin
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apb3_rd('h22*4); // read ifInErrors
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if (|m_apb3_prdata == 0) begin
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$display("%t - Error: Expecting UDP packet ifInErrors to go high, ifInErrors = %h", $time, m_apb3_prdata);
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$fatal("FAIL: simulation fail");
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end
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else begin
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$display("%t - Correct UDP packet %d, received", $time, i);
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end
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end
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else if (check_error_bit == 2'b10) begin
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if (rx_data_ruser == 0) begin
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$display("%t - Error: Expecting UDP packet rx_data_ruser to go high, rx_data_ruser = %h", $time, rx_data_ruser);
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$fatal("FAIL: simulation fail");
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end
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else begin
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$display("%t - UDP packet %d is filtered", $time, i);
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end
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end
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else begin
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apb3_rd('h22*4); // read ifInErrors
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if (rdata_mismatch != 0) begin
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$display("%t - Error: Received data mismatch", $time);
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$fatal("FAIL: simulation fail");
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end
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if (|m_apb3_prdata != 0) begin
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$display("%t - Error: There is an Error in the UDP received packet, ifInErrors = %h", $time, m_apb3_prdata);
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$fatal("FAIL: simulation fail");
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end
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else begin
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$display("%t - Correct UDP packet %d, received", $time, i);
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end
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end
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end
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endtask
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//-----------------------------------------------------------------------------------//
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// THE Test Case Task
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//-----------------------------------------------------------------------------------//
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task test_case_1_task;
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begin
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apb3_wr('h81*4,32'h2);//ex_reg pat_mux_select & axi4_st_mux_select
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apb3_wr('h88*4,MAC_DLEN);//ex_reg pat_mac_dlen
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apb3_wr('h83*4,{16'h10,16'h3E8});//ex_reg pat_gen_ipg & pat_gen_num
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apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
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apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
for (i=0; i<16'h3E8; i = i + 1) begin
|
|
check_rdata_task(i, 2'b00);
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task test_case_2_task;
|
|
begin
|
|
apb3_wr('h81*4,32'h0);//ex_reg pat_mux_select & axi4_st_mux_select
|
|
apb3_wr('h8c*4,UDP_DLEN);//ex_reg pat_udp_dlen
|
|
apb3_wr('h83*4,{16'hff,16'h3E8});//ex_reg pat_gen_ipg & pat_gen_num
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
for (i=0; i<16'h3E8; i = i + 1) begin
|
|
check_udp_rdata_task(i, 2'b00);
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task test_case_3_task;
|
|
begin
|
|
begin // to transmit tx packet after rx pause frame finished processed
|
|
apb3_wr('h88*4,16'd100);//ex_reg pat_mac_dlen
|
|
apb3_wr('h8c*4,16'd100);//ex_reg pat_udp_dlen
|
|
apb3_wr('h83*4,{16'hf,16'h2});//ex_reg pat_gen_ipg & pat_gen_num
|
|
|
|
//Send 2 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_udp_rdata_task(0, 2'b00);
|
|
check_udp_rdata_task(1, 2'b00);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_rdata_task(0, 2'b00);
|
|
check_rdata_task(1, 2'b00);
|
|
end
|
|
|
|
//send 1 pause frames
|
|
pause_gen_task(16'd8);
|
|
|
|
while (rx_data_rlast == 0) @(posedge clk_125m);
|
|
|
|
#1000 // to have some buffer to make sure the core process rx pause frame entirely
|
|
|
|
//Send 2 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_udp_rdata_task(2, 2'b00);
|
|
check_udp_rdata_task(3, 2'b00);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_rdata_task(2, 2'b00);
|
|
check_rdata_task(3, 2'b00);
|
|
end
|
|
end
|
|
|
|
begin
|
|
//Send 2 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_udp_rdata_task(4, 2'b00);
|
|
check_udp_rdata_task(5, 2'b00);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_rdata_task(4, 2'b00);
|
|
check_rdata_task(5, 2'b00);
|
|
end
|
|
|
|
//send 1 pause frames
|
|
pause_gen_task(16'd8);
|
|
|
|
//Send 2 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
// check to make sure entire pause frame is received
|
|
while (rx_data_rlast == 0) @(posedge clk_125m);
|
|
repeat(1) @(posedge clk_125m);
|
|
|
|
check_udp_rdata_task(6, 2'b00);
|
|
check_udp_rdata_task(7, 2'b00);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
// check to make sure entire pause frame is received
|
|
while (rx_data_rlast == 0) @(posedge clk_125m);
|
|
repeat(1) @(posedge clk_125m);
|
|
|
|
check_rdata_task(8, 2'b00);
|
|
check_rdata_task(9, 2'b00);
|
|
end
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task test_case_4_task;
|
|
begin
|
|
apb3_wr('h83*4,{16'hf,16'h1});//ex_reg pat_gen_ipg & pat_gen_num
|
|
//Send 1 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h5*4,16'd9000+46);//mac_reg frm_length
|
|
apb3_wr('h8c*4,16'd9000);//ex_reg pat_udp_dlen
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_udp_rdata_task(0, 2'b00);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h5*4,16'd9000+18);//mac_reg frm_length
|
|
apb3_wr('h88*4,16'd9000);//ex_reg pat_mac_dlen
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_rdata_task(0, 2'b00);
|
|
end
|
|
//Send 1 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h8c*4,16'd9001);//ex_reg pat_udp_dlen
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_udp_rdata_task(1, 2'b01);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h88*4,16'd9001);//ex_reg pat_mac_dlen
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_rdata_task(1, 2'b01);
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task test_case_5_task;
|
|
begin
|
|
apb3_wr('h83*4,{16'hf,16'd20});//ex_reg pat_gen_ipg & pat_gen_num
|
|
|
|
for (i=0; i<20; i = i + 1) begin
|
|
apb3_wr('h88*4,i);//ex_reg pat_mac_dlen
|
|
apb3_wr('h8c*4,i);//ex_reg pat_udp_dlen
|
|
|
|
//Send 1 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_udp_rdata_task(i, 2'b00);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_rdata_task(i, 2'b00);
|
|
end
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task test_case_6_task;
|
|
begin
|
|
apb3_wr('h88*4,16'd64);//ex_reg pat_mac_dlen
|
|
apb3_wr('h8c*4,16'd64);//ex_reg pat_udp_dlen
|
|
apb3_wr('h83*4,{16'hf,16'h1});//ex_reg pat_gen_ipg & pat_gen_num
|
|
//Send 1 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_udp_rdata_task(0, 2'b00);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_rdata_task(0, 2'b00);
|
|
end
|
|
//Send 1 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_udp_rdata_task(1, 2'b00);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_rdata_task(1, 2'b00);
|
|
end
|
|
|
|
//Send 1 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h8c*4,16'd200);//ex_reg pat_udp_dlen
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
$display("%t Wait for rgmii_rx_ctl to go high", $time);
|
|
wait(u_temac_ex.u_tsemac.u_efx_mac1gbe.inst_tsemac.rgmii_rx_ctl_HI == 1);
|
|
repeat(20) @(posedge rgmii_rxc);
|
|
|
|
err_ins <= 1'b1;
|
|
$display("%t - insert error", $time);
|
|
repeat(4) @(posedge rgmii_rxc);
|
|
err_ins <= 1'b0;
|
|
$display("%t - deassert error", $time);
|
|
|
|
check_udp_rdata_task(2, 2'b01);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h88*4,16'd200);//ex_reg pat_mac_dlen
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
$display("%t Wait for rgmii_rx_ctl to go high", $time);
|
|
wait(u_temac_ex.u_tsemac.u_efx_mac1gbe.inst_tsemac.rgmii_rx_ctl_HI == 1);
|
|
repeat(20) @(posedge rgmii_rxc);
|
|
|
|
err_ins <= 1'b1;
|
|
$display("%t - insert error", $time);
|
|
repeat(4) @(posedge rgmii_rxc);
|
|
err_ins <= 1'b0;
|
|
$display("%t - deassert error", $time);
|
|
|
|
check_rdata_task(2, 2'b01);
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task test_case_7_task;
|
|
begin
|
|
apb3_wr('h88*4,16'd64);//ex_reg pat_mac_dlen
|
|
apb3_wr('h8c*4,16'd64);//ex_reg pat_udp_dlen
|
|
apb3_wr('h83*4,{16'hf,16'h1});//ex_reg pat_gen_ipg & pat_gen_num
|
|
//Send 1 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_udp_rdata_task(0, 2'b00);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_rdata_task(0, 2'b00);
|
|
end
|
|
apb3_wr('h51*4,32'hffffffff);//mac_reg mac_addr_mask[31:0]
|
|
apb3_wr('h52*4,16'hffff);//mac_reg mac_addr_mask[47:32]
|
|
//Send 1 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_udp_rdata_task(1, 2'b10);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_rdata_task(1, 2'b10);
|
|
end
|
|
apb3_wr('h84*4,32'hffffffff);//ex_reg pat_dst_mac[31:0]
|
|
apb3_wr('h85*4,16'hffff);//ex_reg pat_dst_mac[47:32]
|
|
//Send 1 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_udp_rdata_task(2, 2'b01);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_rdata_task(2, 2'b01);
|
|
end
|
|
apb3_wr('h50*4,32'h1);//mac_reg broadcast_filter_en
|
|
//Send 1 mac frames
|
|
if(PAT_TYPE == 1'b0)
|
|
begin
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_udp_rdata_task(3, 2'b10);
|
|
end
|
|
else
|
|
begin
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
check_rdata_task(3, 2'b10);
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task test_case_8_task; // small packet length & small inter-gap
|
|
begin
|
|
apb3_wr('h81*4,32'h2);//ex_reg pat_mux_select & axi4_st_mux_select
|
|
apb3_wr('h88*4,MAC_DLEN);//ex_reg pat_mac_dlen
|
|
apb3_wr('h83*4,{16'd12,16'd100});//ex_reg pat_gen_ipg & pat_gen_num
|
|
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
for (i=0; i<16'd100; i = i + 1) begin
|
|
check_rdata_task(i, 2'b00);
|
|
end
|
|
end
|
|
endtask
|
|
|
|
task test_case_9_task; // small packet length & small inter-gap
|
|
begin
|
|
apb3_wr('h81*4,32'h0);//ex_reg pat_mux_select & axi4_st_mux_select
|
|
apb3_wr('h8c*4,UDP_DLEN);//ex_reg pat_udp_dlen
|
|
apb3_wr('h83*4,{16'd12,16'd100});//ex_reg pat_gen_ipg & pat_gen_num
|
|
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
|
|
|
|
for (i=0; i<16'd100; i = i + 1) begin
|
|
check_udp_rdata_task(i, 2'b00);
|
|
end
|
|
end
|
|
endtask
|
|
|
|
endmodule
|