498 lines
15 KiB
Verilog
498 lines
15 KiB
Verilog
/////////////////////////////////////////////////////////////////////////////
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// _____
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// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
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// / / \
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// / / .. /
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// / / .' /
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// __/ /.' /
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// __ \ /
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// /_/ /\ \_____/ /
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// ____/ \_______/
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//
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// *******************************
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// Revisions:
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// 1.0 Initial rev
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//
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// *******************************
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`timescale 1 ns / 1 ns
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module udp_pat_gen
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(
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//Globle Signals
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input clk,
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input rstn,
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//Control Interface
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input pat_gen_en,
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input [15:0] pat_gen_num,//When value is 0, it's infinite mode
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input [15:0] pat_gen_ipg,
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//MAC Protocol Signals
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input [47:0] dst_mac,
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input [47:0] src_mac,
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//IP Protocol Signals
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input [31:0] src_ip,
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input [31:0] dst_ip,
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//UDP Protocol Signals
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input [15:0] udp_dlen,
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input [15:0] src_port,
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input [15:0] dst_port,
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//AXI4-Stream Interface
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input rclk,
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input rrstn,
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input [7:0] rdata,
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input rvalid,
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input rlast,
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output reg [7:0] tdata,
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output reg tvalid,
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output reg tlast,
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input tready
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);
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// Parameter Define
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localparam VER = 4'h4;//IPv4
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localparam IHL = 4'h5;//Internet Header Length
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localparam TOS = 8'h0;//Type Of Service
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localparam FLG = 3'h0;//Flags
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localparam TTL = 8'h40;//Time To Live
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localparam PTC = 8'h11;//UDP Protocol
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localparam IDLE = 3'h0;
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localparam UDP_CHKSUM = 3'h1;
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localparam IP_CHKSUM = 3'h2;
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localparam PAT_IPG = 3'h3;
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localparam PAT_GEN = 3'h4;
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// Register Define
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reg [2:0] cur_state;
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reg [2:0] next_state;
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reg pat_gen_en_dl1;
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reg pat_gen_en_dl2;
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reg [31:0] src_ip_r;
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reg [31:0] dst_ip_r;
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reg [15:0] src_port_r;
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reg [15:0] dst_port_r;
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reg pat_en;
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reg infinite_en;
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reg [15:0] num_cnt;
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reg [15:0] udp_chksum_cnt;
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reg [3:0] ip_chksum_cnt;
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reg [15:0] ipg_cnt;
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reg [15:0] pat_cnt;
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reg [15:0] udp_len;
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reg [15:0] udp_chksum_num;
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reg [7:0] udp_data_h;
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reg [7:0] udp_data_l;
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reg [16:0] udp_chksum_r;
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reg [15:0] udp_chksum;
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reg [15:0] ip_len;
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reg [15:0] ip_id;
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reg [12:0] ip_ofs;
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reg [16:0] ip_chksum_r;
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reg [15:0] ip_chksum;
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reg [15:0] pat_gen_num_r;
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reg [15:0] pat_gen_ipg_r;
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reg [47:0] dst_mac_r;
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reg [47:0] src_mac_r;
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reg [15:0] udp_dlen_r;
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// Wire Define
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/*----------------------------------------------------------------------------------*\
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The main code
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\*----------------------------------------------------------------------------------*/
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0) begin
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pat_gen_num_r <= 16'h0;
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pat_gen_ipg_r <= 16'h0;
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dst_mac_r <= 48'h0;
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src_mac_r <= 48'h0;
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udp_dlen_r <= 16'h0;
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end
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else begin
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pat_gen_num_r <= pat_gen_num;
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pat_gen_ipg_r <= pat_gen_ipg;
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dst_mac_r <= dst_mac;
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src_mac_r <= src_mac;
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udp_dlen_r <= udp_dlen;
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end
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end
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/*----------------------- FSM Region ----------------------------*/
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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cur_state <= IDLE;
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else
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cur_state <= next_state;
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end
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always @(*)
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begin
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case(cur_state)
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IDLE :
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if(pat_en == 1'b1)
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next_state = UDP_CHKSUM;
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else
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next_state = IDLE;
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UDP_CHKSUM :
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if(udp_chksum_cnt == udp_chksum_num)
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next_state = IP_CHKSUM;
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else
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next_state = UDP_CHKSUM;
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IP_CHKSUM :
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if(ip_chksum_cnt == 4'd9)
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next_state = PAT_GEN;
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else
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next_state = IP_CHKSUM;
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PAT_IPG :
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if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0)))
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next_state = IDLE;
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else if(ipg_cnt == pat_gen_ipg_r)
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next_state = IP_CHKSUM;
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else
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next_state = PAT_IPG;
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PAT_GEN :
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if((tlast == 1'b1) && (tready == 1'b1))
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next_state = PAT_IPG;
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else
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next_state = PAT_GEN;
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default :
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next_state = IDLE;
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endcase
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end
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/*----------------------- Generator Control Region ----------------------------*/
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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begin
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pat_gen_en_dl1 <= 1'h0;
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pat_gen_en_dl2 <= 1'h0;
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end
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else
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begin
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pat_gen_en_dl1 <= pat_gen_en;
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pat_gen_en_dl2 <= pat_gen_en_dl1;
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end
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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begin
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src_ip_r <= 32'h0;
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dst_ip_r <= 32'h0;
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src_port_r <= 16'h0;
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dst_port_r <= 16'h0;
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end
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else
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begin
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src_ip_r <= src_ip;
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dst_ip_r <= dst_ip;
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src_port_r <= src_port;
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dst_port_r <= dst_port;
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end
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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pat_en <= 1'h0;
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else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
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pat_en <= 1'h1;
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else if((cur_state == IDLE) && (pat_en == 1'b1))
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pat_en <= 1'h0;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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infinite_en <= 1'h0;
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else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0))
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infinite_en <= 1'h1;
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else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
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infinite_en <= 1'h0;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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num_cnt <= 16'h0;
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else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
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num_cnt <= pat_gen_num_r;
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else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0))
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num_cnt <= num_cnt - 1'b1;
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end
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/*----------------------- UDP Protocol Region ----------------------------*/
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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udp_len <= 16'h0;
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else
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udp_len <= udp_dlen_r + 16'd8;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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udp_chksum_num <= 16'h0;
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else if(udp_dlen_r[0] == 1'b1)
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udp_chksum_num <= udp_dlen_r[15:1] + 16'd10;
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else
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udp_chksum_num <= udp_dlen_r[15:1] + 16'd9;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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begin
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udp_data_h <= 8'h0;
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udp_data_l <= 8'h0;
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end
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else if(cur_state == IDLE)
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begin
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udp_data_h <= 8'h0;
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udp_data_l <= 8'h1;
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end
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else if((cur_state == UDP_CHKSUM) && (udp_chksum_cnt >= 16'h9))
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begin
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udp_data_h <= udp_data_h + 8'h2;
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udp_data_l <= udp_data_l + 8'h2;
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end
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end
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//udp checksum calculate
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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udp_chksum_r <= 17'h0;
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else if(cur_state == IDLE)
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udp_chksum_r <= 17'h0;
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else if(cur_state == UDP_CHKSUM) begin
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if (udp_chksum_cnt <= 16'd8) begin
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case(udp_chksum_cnt[3:0])
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4'd0 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[31:16] + udp_chksum_r[16];
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4'd1 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[15:0] + udp_chksum_r[16];
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4'd2 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[31:16] + udp_chksum_r[16];
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4'd3 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[15:0] + udp_chksum_r[16];
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4'd4 : udp_chksum_r <= udp_chksum_r[15:0] + 16'h11 + udp_chksum_r[16];
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4'd5 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16];
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4'd6 : udp_chksum_r <= udp_chksum_r[15:0] + src_port_r + udp_chksum_r[16];
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4'd7 : udp_chksum_r <= udp_chksum_r[15:0] + dst_port_r + udp_chksum_r[16];
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4'd8 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16];
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default : udp_chksum_r <= 17'h0;
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endcase
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end
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else begin
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if(udp_chksum_cnt == udp_chksum_num)
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udp_chksum_r <= udp_chksum_r[15:0] + udp_chksum_r[16];
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else if((udp_chksum_cnt == udp_chksum_num-1) && (udp_dlen_r[0] == 1'b1))
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udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,8'h0} + udp_chksum_r[16];
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else
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udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,udp_data_l} + udp_chksum_r[16];
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end
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end
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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udp_chksum <= 16'h0;
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else
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udp_chksum <= ~udp_chksum_r[15:0];
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end
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/*----------------------- IP Protocol Region ----------------------------*/
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//IP Frame Total Length
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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ip_len <= 16'h0;
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else
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ip_len <= udp_len + 16'd20;
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end
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//IP Frame Identification
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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ip_id <= 16'h0;
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else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1))
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ip_id <= ip_id + 1'b1;
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end
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//IP Frame Fragment Offset
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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ip_chksum <= 16'h0;
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else
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ip_chksum <= ~ip_chksum_r[15:0];
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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ip_ofs <= 13'h0;
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end
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//ip checksum calculate
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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ip_chksum_r <= 16'h0;
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else if(cur_state == IDLE)
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ip_chksum_r <= 16'h0;
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else if(cur_state == IP_CHKSUM) begin
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case(ip_chksum_cnt)
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4'd0 : ip_chksum_r <= ip_chksum_r[15:0] + {VER,IHL,TOS} + ip_chksum_r[16];
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4'd1 : ip_chksum_r <= ip_chksum_r[15:0] + ip_len + ip_chksum_r[16];
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4'd2 : ip_chksum_r <= ip_chksum_r[15:0] + ip_id + ip_chksum_r[16];
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4'd3 : ip_chksum_r <= ip_chksum_r[15:0] + {FLG,ip_ofs} + ip_chksum_r[16];
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4'd4 : ip_chksum_r <= ip_chksum_r[15:0] + {TTL,PTC} + ip_chksum_r[16];
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4'd5 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[31:16] + ip_chksum_r[16];
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4'd6 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[15:0] + ip_chksum_r[16];
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4'd7 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[31:16] + ip_chksum_r[16];
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4'd8 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[15:0] + ip_chksum_r[16];
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4'd9 : ip_chksum_r <= ip_chksum_r[15:0] + ip_chksum_r[16];
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endcase
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end
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else if(cur_state == PAT_IPG)
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ip_chksum_r <= 16'h0;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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ip_chksum <= 16'h0;
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else
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ip_chksum <= ~ip_chksum_r[15:0];
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end
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/*----------------------- Pattern Counter Region ----------------------------*/
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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udp_chksum_cnt <= 16'h0;
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else if(cur_state == UDP_CHKSUM)
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udp_chksum_cnt <= udp_chksum_cnt + 1'b1;
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else
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udp_chksum_cnt <= 16'h0;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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ip_chksum_cnt <= 4'h0;
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else if(cur_state == IP_CHKSUM)
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ip_chksum_cnt <= ip_chksum_cnt + 1'b1;
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else
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ip_chksum_cnt <= 4'h0;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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ipg_cnt <= 16'h0;
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else if(cur_state == PAT_IPG)
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ipg_cnt <= ipg_cnt + 1'b1;
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else
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ipg_cnt <= 8'h0;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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pat_cnt <= 16'h0;
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else if(cur_state != PAT_GEN)
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pat_cnt <= 16'h0;
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else if(tready == 1'b1)
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pat_cnt <= pat_cnt + 1'b1;
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end
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/*----------------------- Pattern Generator Region ----------------------------*/
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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tvalid <= 1'b0;
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else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1))
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tvalid <= 1'b1;
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else if((tready == 1'b1) && (tlast == 1'b1))
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tvalid <= 1'b0;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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tdata <= 8'h0;
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else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd42))
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case(pat_cnt[5:0])
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6'd0 : tdata <= dst_mac_r[5*8 +: 8];
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6'd1 : tdata <= dst_mac_r[4*8 +: 8];
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6'd2 : tdata <= dst_mac_r[3*8 +: 8];
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6'd3 : tdata <= dst_mac_r[2*8 +: 8];
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6'd4 : tdata <= dst_mac_r[1*8 +: 8];
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6'd5 : tdata <= dst_mac_r[0*8 +: 8];
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6'd6 : tdata <= src_mac_r[5*8 +: 8];
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6'd7 : tdata <= src_mac_r[4*8 +: 8];
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6'd8 : tdata <= src_mac_r[3*8 +: 8];
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6'd9 : tdata <= src_mac_r[2*8 +: 8];
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6'd10 : tdata <= src_mac_r[1*8 +: 8];
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6'd11 : tdata <= src_mac_r[0*8 +: 8];
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6'd12 : tdata <= 8'h08;
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6'd13 : tdata <= 8'h00;
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6'd14 : tdata <= {VER,IHL};
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6'd15 : tdata <= TOS;
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6'd16 : tdata <= ip_len[15:8];
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6'd17 : tdata <= ip_len[7:0];
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6'd18 : tdata <= ip_id[15:8];
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6'd19 : tdata <= ip_id[7:0];
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6'd20 : tdata <= {FLG,ip_ofs[12:8]};
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6'd21 : tdata <= ip_ofs[7:0];
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6'd22 : tdata <= TTL;
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|
6'd23 : tdata <= PTC;
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|
6'd24 : tdata <= ip_chksum[15:8];
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|
6'd25 : tdata <= ip_chksum[7:0];
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|
6'd26 : tdata <= src_ip_r[3*8 +: 8];
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|
6'd27 : tdata <= src_ip_r[2*8 +: 8];
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|
6'd28 : tdata <= src_ip_r[1*8 +: 8];
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|
6'd29 : tdata <= src_ip_r[0*8 +: 8];
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|
6'd30 : tdata <= dst_ip_r[3*8 +: 8];
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|
6'd31 : tdata <= dst_ip_r[2*8 +: 8];
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|
6'd32 : tdata <= dst_ip_r[1*8 +: 8];
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|
6'd33 : tdata <= dst_ip_r[0*8 +: 8];
|
|
6'd34 : tdata <= src_port_r[15:8];
|
|
6'd35 : tdata <= src_port_r[7:0];
|
|
6'd36 : tdata <= dst_port_r[15:8];
|
|
6'd37 : tdata <= dst_port_r[7:0];
|
|
6'd38 : tdata <= udp_len[15:8];
|
|
6'd39 : tdata <= udp_len[7:0];
|
|
6'd40 : tdata <= udp_chksum[15:8];
|
|
6'd41 : tdata <= udp_chksum[7:0];
|
|
6'd42 : tdata <= 8'h0;//UDP First Data
|
|
default : tdata <= tdata + 1'b1;
|
|
endcase
|
|
else if((cur_state == PAT_GEN) && (tready == 1'b1))
|
|
tdata <= tdata + 1'b1;
|
|
end
|
|
|
|
always @(posedge clk or negedge rstn)
|
|
begin
|
|
if(rstn == 1'b0)
|
|
tlast <= 1'b0;
|
|
else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == ip_len+16'd13))
|
|
tlast <= 1'b1;
|
|
else if(tready == 1'b1)
|
|
tlast <= 1'b0;
|
|
end
|
|
|
|
endmodule
|