334 lines
9.7 KiB
Verilog
334 lines
9.7 KiB
Verilog
/////////////////////////////////////////////////////////////////////////////
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// _____
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// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
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// / / \
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// / / .. /
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// / / .' /
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// __/ /.' /
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// __ \ /
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// /_/ /\ \_____/ /
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// ____/ \_______/
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//
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// *******************************
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// Revisions:
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// 1.0 Initial rev
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//
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// *******************************
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`timescale 1 ns / 1 ns
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module reg_apb3#(
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parameter ADDR_WTH = 10
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)
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(
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//Globle Signals
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//
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//APB3 Slave Interface
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input s_apb3_clk,
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input s_apb3_rstn,
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input [ADDR_WTH-1:0] s_apb3_paddr,
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input s_apb3_psel,
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input s_apb3_penable,
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output reg s_apb3_pready,
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input s_apb3_pwrite,//0:rd; 1:wr;
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input [31:0] s_apb3_pwdata,
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output reg [31:0] s_apb3_prdata,
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output wire s_apb3_pslverror,
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//Cfg Space Registers
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//--Example Registers Field
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output reg mac_sw_rst,
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output reg axi4_st_mux_select,
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output reg pat_mux_select,
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output reg udp_pat_gen_en,
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output reg mac_pat_gen_en,
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output reg [15:0] pat_gen_num,
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output reg [15:0] pat_gen_ipg,
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output reg [47:0] pat_dst_mac,
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output reg [47:0] pat_src_mac,
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output reg [15:0] pat_mac_dlen,
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output reg [31:0] pat_src_ip,
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output reg [31:0] pat_dst_ip,
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output reg [15:0] pat_src_port,
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output reg [15:0] pat_dst_port,
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output reg [15:0] pat_udp_dlen,
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output reg [1:0] clkmux_sel
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);
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// Parameter Define
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// Register Define
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reg [ADDR_WTH-3:0] loc_addr;
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reg loc_wr_vld;
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reg loc_rd_vld;
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// Wire Define
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/*----------------------------------------------------------------------------------*\
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The main code
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\*----------------------------------------------------------------------------------*/
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//apb3 interface
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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loc_addr <= {ADDR_WTH-2{1'b0}};
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else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0))
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loc_addr <= s_apb3_paddr[2+:ADDR_WTH-2];
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end
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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loc_wr_vld <= 1'b0;
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else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
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loc_wr_vld <= 1'b1;
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else
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loc_wr_vld <= 1'b0;
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end
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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loc_rd_vld <= 1'b0;
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else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0))
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loc_rd_vld <= 1'b1;
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else
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loc_rd_vld <= 1'b0;
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end
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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s_apb3_pready <= 1'b0;
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else if((loc_wr_vld == 1'b1) || (loc_rd_vld == 1'b1))
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s_apb3_pready <= 1'b1;
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else
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s_apb3_pready <= 1'b0;
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end
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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s_apb3_prdata <= 32'h0;
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else if(loc_rd_vld == 1'b1)
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begin
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case(loc_addr)
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//Example Registers Field
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'h080 : s_apb3_prdata <= {31'h0,mac_sw_rst};
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'h081 : s_apb3_prdata <= {30'h0,pat_mux_select,axi4_st_mux_select};
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'h082 : s_apb3_prdata <= {30'h0,mac_pat_gen_en,udp_pat_gen_en};
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'h083 : s_apb3_prdata <= {pat_gen_ipg,pat_gen_num};
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'h084 : s_apb3_prdata <= pat_dst_mac[31:0];
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'h085 : s_apb3_prdata <= {16'h0,pat_dst_mac[47:32]};
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'h086 : s_apb3_prdata <= pat_src_mac[31:0];
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'h087 : s_apb3_prdata <= {16'h0,pat_src_mac[47:32]};
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'h088 : s_apb3_prdata <= {16'h0,pat_mac_dlen};
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'h089 : s_apb3_prdata <= pat_src_ip;
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'h08a : s_apb3_prdata <= pat_dst_ip;
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'h08b : s_apb3_prdata <= {pat_dst_port,pat_src_port};
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'h08c : s_apb3_prdata <= {16'h0,pat_udp_dlen};
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'h08d : s_apb3_prdata <= {30'h0,clkmux_sel};
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endcase
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end
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end
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assign s_apb3_pslverror = 1'b0;
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/*----------------------------------------------------------------------------------*\
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Register Space -- Example Registers Field
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\*----------------------------------------------------------------------------------*/
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//loc_addr = 0x080; axi_addr = 0x200; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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mac_sw_rst <= 1'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h080))
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begin
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mac_sw_rst <= s_apb3_pwdata[0];
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end
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end
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//loc_addr = 0x081; axi_addr = 0x204; RW;
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//[axi4_st_mux_select] 0:pat tx mode; 1:rx2tx loopback mode;
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//[pat_mux_select] 0:udp pat; 1:mac pat;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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axi4_st_mux_select <= 1'h0;
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pat_mux_select <= 1'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h081))
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begin
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axi4_st_mux_select <= s_apb3_pwdata[0];
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pat_mux_select <= s_apb3_pwdata[1];
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end
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end
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//loc_addr = 0x082; axi_addr = 0x208; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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udp_pat_gen_en <= 1'h0;
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mac_pat_gen_en <= 1'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h082))
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begin
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udp_pat_gen_en <= s_apb3_pwdata[0];
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mac_pat_gen_en <= s_apb3_pwdata[1];
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end
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end
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//loc_addr = 0x083; axi_addr = 0x20c; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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pat_gen_num <= 16'h0;
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pat_gen_ipg <= 16'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h083))
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begin
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pat_gen_num <= s_apb3_pwdata[15:0];
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pat_gen_ipg <= s_apb3_pwdata[31:16];
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end
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end
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//loc_addr = 0x084; axi_addr = 0x210; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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pat_dst_mac[31:0] <= 32'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h084))
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begin
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pat_dst_mac[31:0] <= s_apb3_pwdata[31:0];
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end
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end
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//loc_addr = 0x085; axi_addr = 0x214; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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pat_dst_mac[47:32] <= 16'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h085))
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begin
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pat_dst_mac[47:32] <= s_apb3_pwdata[15:0];
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end
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end
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//loc_addr = 0x086; axi_addr = 0x218; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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pat_src_mac[31:0] <= 32'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h086))
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begin
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pat_src_mac[31:0] <= s_apb3_pwdata[31:0];
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end
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end
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//loc_addr = 0x087; axi_addr = 0x21c; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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pat_src_mac[47:32] <= 16'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h087))
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begin
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pat_src_mac[47:32] <= s_apb3_pwdata[15:0];
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end
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end
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//loc_addr = 0x088; axi_addr = 0x220; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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pat_mac_dlen <= 16'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h088))
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begin
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pat_mac_dlen <= s_apb3_pwdata[15:0];
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end
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end
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//loc_addr = 0x089; axi_addr = 0x224; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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pat_src_ip <= 32'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h089))
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begin
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pat_src_ip <= s_apb3_pwdata[31:0];
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end
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end
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//loc_addr = 0x08a; axi_addr = 0x228; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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pat_dst_ip <= 32'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08a))
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begin
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pat_dst_ip <= s_apb3_pwdata[31:0];
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end
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end
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//loc_addr = 0x08b; axi_addr = 0x22c; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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pat_src_port <= 16'h0;
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pat_dst_port <= 16'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08b))
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begin
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pat_src_port <= s_apb3_pwdata[15:0];
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pat_dst_port <= s_apb3_pwdata[31:16];
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end
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end
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//loc_addr = 0x08c; axi_addr = 0x230; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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pat_udp_dlen <= 16'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08c))
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begin
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pat_udp_dlen <= s_apb3_pwdata[15:0];
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end
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end
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//loc_addr = 0x08d; axi_addr = 0x234; RW;
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always @(posedge s_apb3_clk or negedge s_apb3_rstn)
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begin
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if(s_apb3_rstn == 1'b0)
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begin
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clkmux_sel <= 2'h0;
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end
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else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08d))
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begin
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clkmux_sel <= s_apb3_pwdata[1:0];
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end
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end
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/*----------------------------------------------------------------------------------*\
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Register Space -- The End
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\*----------------------------------------------------------------------------------*/
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endmodule
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