997 lines
32 KiB
Verilog
997 lines
32 KiB
Verilog
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`timescale 1 ns / 1 ns
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module tseCore #(
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parameter ADDR_WIDTH = 10
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) (
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input io_peripheralClk,
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input io_peripheralReset,
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input io_tseClk,
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input pll_locked,
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output phy_sw_rst,
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output mac_ext_rst,
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output dma_rx_rst,
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output dma_tx_rst,
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input dma_tx_descriptorUpdate,
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output [1:0] dma_interrupts,
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output [2:0] eth_speed,
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// MAC RGMII Interface
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output [3:0] rgmii_txd_HI,
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output [3:0] rgmii_txd_LO,
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output rgmii_tx_ctl_HI,
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output rgmii_tx_ctl_LO,
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output rgmii_txc_HI,
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output rgmii_txc_LO,
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input [3:0] rgmii_rxd_HI,
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input [3:0] rgmii_rxd_LO,
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input rgmii_rx_ctl_HI,
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input rgmii_rx_ctl_LO,
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input rgmii_rxc,
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// PHY MDIO Interface
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input phy_mdi,
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output phy_mdo,
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output phy_mdo_en,
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output phy_mdc,
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// AXI CSR
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input [31:0] s_axi_awaddr,
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input s_axi_awvalid,
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output s_axi_awready,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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output s_axi_wlast,
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input s_axi_wvalid,
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output s_axi_wready,
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output [1:0] s_axi_bresp,
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output s_axi_bvalid,
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input s_axi_bready,
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input [31:0] s_axi_araddr,
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input s_axi_arvalid,
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output s_axi_arready,
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output [1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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output s_axi_rlast,
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output s_axi_rvalid,
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input s_axi_rready,
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// MAC Stream
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input s_eth_tx_tvalid,
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output s_eth_tx_tready,
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input [7:0] s_eth_tx_tdata,
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input [0:0] s_eth_tx_tkeep,
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input [3:0] s_eth_tx_tdest,
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input s_eth_tx_tlast,
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output m_eth_rx_tvalid,
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input m_eth_rx_tready,
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output [7:0] m_eth_rx_tdata,
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output [0:0] m_eth_rx_tstrb,
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output m_eth_rx_tlast
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);
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////////////////////////////////////////////////////////////////////////////////////////////
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localparam TSE_DEV = 2;
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localparam MAC = 0;
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localparam CMN = 1;
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// Switch between MAC and CMN
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wire [(TSE_DEV*32)-1:0] gTSE_m_awaddr;
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wire [(TSE_DEV*8)-1:0] gTSE_m_awlen;
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wire [(TSE_DEV*3)-1:0] gTSE_m_awsize;
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wire [(TSE_DEV*2)-1:0] gTSE_m_awburst;
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wire [(TSE_DEV*2)-1:0] gTSE_m_awlock;
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wire [TSE_DEV-1:0] gTSE_m_awvalid;
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wire [TSE_DEV-1:0] gTSE_m_awready;
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wire [(TSE_DEV*32)-1:0] gTSE_m_wdata;
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wire [(TSE_DEV*4)-1:0] gTSE_m_wstrb;
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wire [TSE_DEV-1:0] gTSE_m_wvalid;
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wire [TSE_DEV-1:0] gTSE_m_wlast;
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wire [TSE_DEV-1:0] gTSE_m_wready;
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wire [(TSE_DEV*2)-1:0] gTSE_m_bresp;
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wire [TSE_DEV-1:0] gTSE_m_bvalid;
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wire [TSE_DEV-1:0] gTSE_m_bready;
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wire [(TSE_DEV*32)-1:0] gTSE_m_araddr;
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wire [(TSE_DEV*8)-1:0] gTSE_m_arlen;
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wire [(TSE_DEV*3)-1:0] gTSE_m_arsize;
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wire [(TSE_DEV*2)-1:0] gTSE_m_arburst;
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wire [(TSE_DEV*2)-1:0] gTSE_m_arlock;
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wire [TSE_DEV-1:0] gTSE_m_arvalid;
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wire [TSE_DEV-1:0] gTSE_m_arready;
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wire [(TSE_DEV*32)-1:0] gTSE_m_rdata;
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wire [(TSE_DEV*2)-1:0] gTSE_m_rresp;
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wire [TSE_DEV-1:0] gTSE_m_rlast;
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wire [TSE_DEV-1:0] gTSE_m_rvalid;
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wire [TSE_DEV-1:0] gTSE_m_rready;
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// clock reset
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wire mac_sw_rst;
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wire proto_reset;
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wire mac_ext_srst;
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wire rx_axis_clk;
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wire tx_axis_clk;
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// Stream control
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wire m_eth_tx_tvalid;
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wire m_eth_tx_tready;
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wire [7:0] m_eth_tx_tdata;
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wire [3:0] m_eth_tx_tdest;
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wire m_eth_tx_tlast;
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wire s_eth_rx_tvalid;
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wire s_eth_rx_tready;
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wire [7:0] s_eth_rx_tdata;
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wire [0:0] s_eth_rx_tkeep;
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wire [3:0] s_eth_rx_tdest;
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wire s_eth_rx_tlast;
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////////////////////////////////////////////////////////////////////////////////////////////
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assign mac_ext_rst = ~pll_locked;
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assign rx_axis_clk = io_tseClk;
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assign tx_axis_clk = io_tseClk;
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reset_ctrl #(
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.NUM_RST (2),
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.CYCLE (2),
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.IN_RST_ACTIVE (2'b11),
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.OUT_RST_ACTIVE (2'b11)
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) inst_reset_ctrl (
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.i_arst ({mac_sw_rst, mac_ext_rst}),
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.i_clk ({2{io_tseClk}}),
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.o_srst ({proto_reset, mac_ext_srst})
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);
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gTSE_1to2_switch u_gTSE_1to2_switch
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(
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.rst_n ( ~io_peripheralReset ),
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.clk ( io_peripheralClk ),
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.s_axi_awvalid ( s_axi_awvalid ),
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.s_axi_awready ( s_axi_awready ),
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.s_axi_awaddr ( {16'd0, s_axi_awaddr[15:0]} ),
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.s_axi_awlock ( 2'b00 ),
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.s_axi_wready ( s_axi_wready ),
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.s_axi_wvalid ( s_axi_wvalid ),
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.s_axi_wstrb ( s_axi_wstrb ),
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.s_axi_wdata ( s_axi_wdata ),
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.s_axi_wlast ( s_axi_wlast ),
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.s_axi_wid ( 8'h00 ),
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.s_axi_bvalid ( s_axi_bvalid ),
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.s_axi_bready ( s_axi_bready ),
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.s_axi_bid ( ),
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.s_axi_bresp ( s_axi_bresp ),
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.s_axi_arvalid ( s_axi_arvalid ),
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.s_axi_arready ( s_axi_arready ),
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.s_axi_araddr ( {16'd0, s_axi_araddr[15:0]} ),
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.s_axi_arlock ( 2'b00 ),
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.s_axi_rvalid ( s_axi_rvalid ),
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.s_axi_rready ( s_axi_rready ),
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.s_axi_rid ( ),
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.s_axi_rdata ( s_axi_rdata ),
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.s_axi_rlast ( ),
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.s_axi_rresp ( s_axi_rresp ),
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.m_axi_awvalid ( gTSE_m_awvalid ),
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.m_axi_awready ( gTSE_m_awready ),
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.m_axi_awaddr ( gTSE_m_awaddr ),
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.m_axi_awlock ( ),
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.m_axi_wvalid ( gTSE_m_wvalid ),
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.m_axi_wready ( gTSE_m_wready ),
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.m_axi_wlast ( gTSE_m_wlast ),
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.m_axi_wstrb ( gTSE_m_wstrb ),
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.m_axi_wdata ( gTSE_m_wdata ),
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.m_axi_bvalid ( gTSE_m_bvalid ),
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.m_axi_bready ( gTSE_m_bready ),
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.m_axi_bresp ( gTSE_m_bresp ),
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.m_axi_bid ( {TSE_DEV{8'h00}} ),
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.m_axi_arvalid ( gTSE_m_arvalid ),
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.m_axi_araddr ( gTSE_m_araddr ),
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.m_axi_arlock ( ),
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.m_axi_arready ( gTSE_m_arready ),
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.m_axi_rvalid ( gTSE_m_rvalid ),
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.m_axi_rready ( gTSE_m_rready ),
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.m_axi_rid ( {TSE_DEV{8'h00}} ),
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.m_axi_rdata ( gTSE_m_rdata ),
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.m_axi_rlast ( gTSE_m_rlast ),
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.m_axi_rresp ( gTSE_m_rresp )
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);
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assign s_axi_rlast = 1'b1;
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assign gTSE_m_wlast = 2'b11;
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assign gTSE_m_rlast = 2'b11;
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gTSE_streamControl #(
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.ADDR_WIDTH (ADDR_WIDTH)
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) u_gTSE_streamControl (
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.s_axi_aclk ( io_peripheralClk ),
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.s_axi_aresetn ( ~io_peripheralReset ),
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.s_axi_awaddr ( gTSE_m_awaddr[CMN*32 +: ADDR_WIDTH] ),
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.s_axi_awvalid ( gTSE_m_awvalid[CMN*1 +: 1] ),
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.s_axi_awready ( gTSE_m_awready[CMN*1 +: 1] ),
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.s_axi_wdata ( gTSE_m_wdata[CMN*32 +: 32] ),
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.s_axi_wvalid ( gTSE_m_wvalid[CMN*1 +: 1] ),
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.s_axi_wready ( gTSE_m_wready[CMN*1 +: 1] ),
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.s_axi_bvalid ( gTSE_m_bvalid[CMN*1 +: 1] ),
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.s_axi_bready ( gTSE_m_bready[CMN*1 +: 1 ]),
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.s_axi_bresp ( gTSE_m_bresp[CMN*2 +: 2] ),
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.s_axi_araddr ( gTSE_m_araddr[CMN*32 +: ADDR_WIDTH] ),
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.s_axi_arvalid ( gTSE_m_arvalid[CMN*1 +: 1] ),
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.s_axi_arready ( gTSE_m_arready[CMN*1 +: 1] ),
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.s_axi_rdata ( gTSE_m_rdata[CMN*32 +: 32] ),
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.s_axi_rvalid ( gTSE_m_rvalid[CMN*1 +: 1] ),
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.s_axi_rready ( gTSE_m_rready[CMN*1 +: 1] ),
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.s_axi_rresp ( gTSE_m_rresp[CMN*2 +: 2] ),
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.mac_ext_rst ( mac_ext_rst || mac_sw_rst ),
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.s_eth_tx_clk ( tx_axis_clk ),
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.s_eth_tx_tvalid ( s_eth_tx_tvalid ),
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.s_eth_tx_tready ( s_eth_tx_tready ),
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.s_eth_tx_tdata ( s_eth_tx_tdata ),
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.s_eth_tx_tkeep ( s_eth_tx_tkeep ),
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.s_eth_tx_tdest ( s_eth_tx_tdest ),
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.s_eth_tx_tlast ( s_eth_tx_tlast ),
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.m_eth_tx_tvalid ( m_eth_tx_tvalid ),
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.m_eth_tx_tready ( m_eth_tx_tready ),
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.m_eth_tx_tdata ( m_eth_tx_tdata ),
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.m_eth_tx_tdest ( m_eth_tx_tdest ),
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.m_eth_tx_tlast ( m_eth_tx_tlast ),
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.mac_sw_rst ( mac_sw_rst ),
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.phy_sw_rst ( phy_sw_rst ),
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.dma_rx_rst ( dma_rx_rst ),
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.dma_tx_rst ( dma_tx_rst ),
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.error ( ),
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.dma_descriptor_update (dma_tx_descriptorUpdate)
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);
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wire lso_eth_tx_tvalid;
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wire lso_eth_tx_tready;
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wire [7:0] lso_eth_tx_tdata;
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wire lso_eth_tx_tlast;
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MacTxLso lso0
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(
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.io_input_valid(m_eth_tx_tvalid),
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.io_input_ready(m_eth_tx_tready),
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.io_input_payload_last(m_eth_tx_tlast),
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.io_input_payload_fragment_data(m_eth_tx_tdata),
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.io_output_valid(lso_eth_tx_tvalid),
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.io_output_ready(lso_eth_tx_tready),
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.io_output_payload_last(lso_eth_tx_tlast),
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.io_output_payload_fragment_data(lso_eth_tx_tdata),
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.clk(tx_axis_clk),
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.reset(mac_ext_srst)
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);
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wire rx0_eth_rx_tvalid;
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wire rx0_eth_rx_tready;
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wire [7:0] rx0_eth_rx_tdata;
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wire rx0_eth_rx_tlast;
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MacRxCheckSumChecker rx0
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(
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.io_input_valid(rx0_eth_rx_tvalid),
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.io_input_ready(rx0_eth_rx_tready),
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.io_input_payload_last(rx0_eth_rx_tlast),
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.io_input_payload_fragment_error(1'b0),
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.io_input_payload_fragment_data(rx0_eth_rx_tdata),
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.io_output_valid(s_eth_rx_tvalid),
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.io_output_ready(s_eth_rx_tready),
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.io_output_payload_last(s_eth_rx_tlast),
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.io_output_payload_fragment_error(),
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.io_output_payload_fragment_data(s_eth_rx_tdata),
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.clk(rgmii_rxc),
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.reset(mac_ext_srst)
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);
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gTSE u_gTSE (
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.mac_reset ( mac_ext_srst ),
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.proto_reset ( mac_ext_srst || proto_reset ),
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.tx_mac_aclk ( io_tseClk ),
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.rx_mac_aclk (),
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.eth_speed ( eth_speed ),
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// MAC RX
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.rx_axis_clk ( rgmii_rxc ),
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.rx_axis_mac_tdata ( rx0_eth_rx_tdata ),
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.rx_axis_mac_tvalid ( rx0_eth_rx_tvalid ),
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.rx_axis_mac_tstrb ( s_eth_rx_tstrb ),
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.rx_axis_mac_tlast ( rx0_eth_rx_tlast ),
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.rx_axis_mac_tuser ( ),
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.rx_axis_mac_tready ( rx0_eth_rx_tready ),
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// MAC TX
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.tx_axis_clk ( tx_axis_clk ),
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.tx_axis_mac_tdata ( lso_eth_tx_tdata ),
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.tx_axis_mac_tvalid ( lso_eth_tx_tvalid ),
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.tx_axis_mac_tstrb ( 1'b1 ),
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.tx_axis_mac_tlast ( lso_eth_tx_tlast ),
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.tx_axis_mac_tuser ( 1'b0 ),
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.tx_axis_mac_tready ( lso_eth_tx_tready ),
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// AXI CSR
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.s_axi_aclk ( io_peripheralClk ),
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.s_axi_awaddr ( gTSE_m_awaddr[MAC*32 +: ADDR_WIDTH] ),
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.s_axi_awvalid ( gTSE_m_awvalid[MAC*1 +:1 ] ),
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.s_axi_awready ( gTSE_m_awready[MAC*1 +: 1] ),
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.s_axi_wdata ( gTSE_m_wdata[MAC*32 +: 32] ),
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.s_axi_wvalid ( gTSE_m_wvalid[MAC*1 +: 1] ),
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.s_axi_wready ( gTSE_m_wready[MAC*1 +: 1] ),
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.s_axi_bresp ( gTSE_m_bresp[MAC*2 +: 2] ),
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.s_axi_bvalid ( gTSE_m_bvalid[MAC*1 +: 1] ),
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.s_axi_bready ( gTSE_m_bready[MAC*1 +: 1] ),
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.s_axi_araddr ( gTSE_m_araddr[MAC*32 +: ADDR_WIDTH] ),
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.s_axi_arvalid ( gTSE_m_arvalid[MAC*1 +: 1] ),
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.s_axi_arready ( gTSE_m_arready[MAC*1 +: 1] ),
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.s_axi_rresp ( gTSE_m_rresp[MAC*2 +: 2] ),
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.s_axi_rdata ( gTSE_m_rdata[MAC*32 +: 32] ),
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.s_axi_rvalid ( gTSE_m_rvalid[MAC*1 +: 1] ),
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.s_axi_rready ( gTSE_m_rready[MAC*1 +: 1] ),
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// RGMII
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.rgmii_txd_HI ( rgmii_txd_HI ),
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.rgmii_txd_LO ( rgmii_txd_LO ),
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.rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ),
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.rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ),
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.rgmii_txc_HI ( rgmii_txc_HI ),
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.rgmii_txc_LO ( rgmii_txc_LO ),
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.rgmii_rxd_HI ( rgmii_rxd_HI ),
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.rgmii_rxd_LO ( rgmii_rxd_LO ),
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.rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ),
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.rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ),
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.rgmii_rxc ( rgmii_rxc ),
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// MDIO
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.Mdo ( phy_mdo ),
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.MdoEn ( phy_mdo_en ),
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.Mdi ( phy_mdi ),
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.Mdc ( phy_mdc )
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);
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assign m_eth_rx_tvalid = s_eth_rx_tvalid;
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assign m_eth_rx_tdata = s_eth_rx_tdata;
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assign m_eth_rx_tkeep = 1'b1;
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assign m_eth_rx_tlast = s_eth_rx_tlast;
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assign s_eth_rx_tready = m_eth_rx_tready;
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endmodule
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module gTSE_streamControl#(
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parameter ADDR_WIDTH = 10,
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parameter NUM_REG = 5,
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parameter NUM_FRAME = 10,
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parameter MAC_RX_CLK_FREQ = 100,
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parameter COALESCE_US = 4000
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)
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(
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input s_axi_aclk, //AXI Bus Clock.
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input s_axi_aresetn, //AXI Reset. Active-Low.
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input [ADDR_WIDTH-1:0] s_axi_awaddr, //Write Address. byte address.
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input s_axi_awvalid, //Write address valid.
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output reg s_axi_awready, //Write address ready.
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input [31:0] s_axi_wdata, //Write data bus.
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input s_axi_wvalid, //Write valid.
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output reg s_axi_wready, //Write ready.
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output wire [1:0] s_axi_bresp, //Write response.
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output reg s_axi_bvalid, //Write response valid.
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input s_axi_bready, //Response ready.
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input [ADDR_WIDTH-1:0] s_axi_araddr, //Read address. byte address.
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input s_axi_arvalid, //Read address valid.
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output reg s_axi_arready, //Read address ready.
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output wire [1:0] s_axi_rresp, //Read response.
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output reg [31:0] s_axi_rdata, //Read data.
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output reg s_axi_rvalid, //Read valid.
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input s_axi_rready, //Read ready.
|
|
input s_eth_tx_clk,
|
|
input s_eth_tx_tvalid,
|
|
output s_eth_tx_tready,
|
|
input [7:0] s_eth_tx_tdata,
|
|
input [0:0] s_eth_tx_tkeep,
|
|
input [3:0] s_eth_tx_tdest,
|
|
input s_eth_tx_tlast,
|
|
output m_eth_tx_tvalid,
|
|
input m_eth_tx_tready,
|
|
output [7:0] m_eth_tx_tdata,
|
|
output [3:0] m_eth_tx_tdest,
|
|
output m_eth_tx_tlast,
|
|
input mac_ext_rst,
|
|
output reg mac_sw_rst,
|
|
output reg phy_sw_rst,
|
|
output reg dma_rx_rst,
|
|
output reg dma_tx_rst,
|
|
output reg error,
|
|
input dma_descriptor_update
|
|
|
|
);
|
|
// Parameter Define
|
|
localparam DATA_DEPTH = NUM_FRAME*1540;
|
|
localparam SIZE_DEPTH = NUM_FRAME*5;
|
|
localparam DATA_DEPTH_WID = $clog2(DATA_DEPTH);
|
|
localparam SIZE_DEPTH_WID = $clog2(SIZE_DEPTH);
|
|
localparam COALESCE_CNT = (COALESCE_US * MAC_RX_CLK_FREQ);
|
|
// Register Define
|
|
// Cfg Space Registers
|
|
|
|
// Other Registers
|
|
reg [ADDR_WIDTH-3:0] loc_waddr;
|
|
reg loc_waddr_vld;
|
|
reg [31:0] loc_wdata;
|
|
reg loc_wdata_vld;
|
|
reg [ADDR_WIDTH-3:0] loc_raddr;
|
|
reg loc_raddr_vld;
|
|
// Wire Define
|
|
wire loc_wrdy;
|
|
wire loc_rrdy;
|
|
wire w_eth_mac_rst;
|
|
wire [9:0] w_trans_rdcnt;
|
|
wire w_trans_rst_busy;
|
|
wire w_trans_full;
|
|
wire w_trans_empty;
|
|
wire [12:0] w_txdata_rd_datacount;
|
|
wire w_tx_full;
|
|
wire w_tx_empty;
|
|
wire w_eth_tx_tlast;
|
|
wire w_eth_tx_tkeep;
|
|
wire [3:0] w_eth_tx_tdest;
|
|
wire [7:0] w_eth_tx_tdata;
|
|
reg r_eth_tx_tlast;
|
|
reg [3:0] r_eth_tx_tdest;
|
|
reg [7:0] r_eth_tx_tdata;
|
|
reg r_eth_tx_tvalid;
|
|
wire w_rd_en;
|
|
reg [15:0] write_cnt;
|
|
wire [15:0] write_cnt_rd;
|
|
wire [15:0] write_cnt_next;
|
|
reg [15:0] read_cnt;
|
|
reg [1:0] rd_state;
|
|
reg [1:0] next_rd_state;
|
|
|
|
/*----------------------------------------------------------------------------------*\
|
|
The main code
|
|
\*----------------------------------------------------------------------------------*/
|
|
//axi4-lite interface
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
loc_waddr <= {ADDR_WIDTH-2{1'b0}};
|
|
else if((s_axi_awvalid == 1'b1) && (s_axi_awready == 1'b1))
|
|
loc_waddr <= s_axi_awaddr[2+:ADDR_WIDTH-2];
|
|
end
|
|
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
loc_waddr_vld <= 1'b0;
|
|
else if((s_axi_awvalid == 1'b1) && (s_axi_awready == 1'b1))
|
|
loc_waddr_vld <= 1'b1;
|
|
else if((loc_waddr_vld == 1'b1) && (loc_wdata_vld == 1'b1) && (loc_wrdy == 1'b1))
|
|
loc_waddr_vld <= 1'b0;
|
|
end
|
|
|
|
assign loc_wrdy = 1'b1;
|
|
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
s_axi_awready <= 1'b0;
|
|
else if((s_axi_awvalid == 1'b1) && (s_axi_awready == 1'b1))
|
|
s_axi_awready <= 1'b0;
|
|
else if(loc_waddr_vld == 1'b0)
|
|
s_axi_awready <= 1'b1;
|
|
end
|
|
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
loc_wdata <= 32'h0;
|
|
else if((s_axi_wvalid == 1'b1) && (s_axi_wready == 1'b1))
|
|
loc_wdata <= s_axi_wdata;
|
|
end
|
|
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
loc_wdata_vld <= 1'b0;
|
|
else if((s_axi_wvalid == 1'b1) && (s_axi_wready == 1'b1))
|
|
loc_wdata_vld <= 1'b1;
|
|
else if((loc_waddr_vld == 1'b1) && (loc_wdata_vld == 1'b1) && (loc_wrdy == 1'b1))
|
|
loc_wdata_vld <= 1'b0;
|
|
end
|
|
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
s_axi_wready <= 1'b0;
|
|
else if((s_axi_wvalid == 1'b1) && (s_axi_wready == 1'b1))
|
|
s_axi_wready <= 1'b0;
|
|
else if(loc_wdata_vld == 1'b0)
|
|
s_axi_wready <= 1'b1;
|
|
end
|
|
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
s_axi_bvalid <= 1'b0;
|
|
else if((loc_waddr_vld == 1'b1) && (loc_wdata_vld == 1'b1) && (loc_wrdy == 1'b1))
|
|
s_axi_bvalid <= 1'b1;
|
|
else if(s_axi_bready == 1'b1)
|
|
s_axi_bvalid <= 1'b0;
|
|
end
|
|
|
|
assign s_axi_bresp = 2'h0;
|
|
|
|
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
loc_raddr <= {ADDR_WIDTH-2{1'b0}};
|
|
else if((s_axi_arvalid == 1'b1) && (s_axi_arready == 1'b1))
|
|
loc_raddr <= s_axi_araddr[2+:ADDR_WIDTH-2];
|
|
end
|
|
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
loc_raddr_vld <= 1'b0;
|
|
else if((s_axi_arvalid == 1'b1) && (s_axi_arready == 1'b1))
|
|
loc_raddr_vld <= 1'b1;
|
|
else if((loc_raddr_vld == 1'b1) && (loc_rrdy == 1'b1))
|
|
loc_raddr_vld <= 1'b0;
|
|
end
|
|
|
|
assign loc_rrdy = 1'b1;
|
|
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
s_axi_arready <= 1'b0;
|
|
else if((s_axi_arvalid == 1'b1) && (s_axi_arready == 1'b1))
|
|
s_axi_arready <= 1'b0;
|
|
else if(loc_raddr_vld == 1'b0)
|
|
s_axi_arready <= 1'b1;
|
|
end
|
|
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
s_axi_rdata <= 32'h0;
|
|
else if((loc_raddr_vld == 1'b1) && (loc_rrdy == 1'b1))
|
|
begin
|
|
case(loc_raddr)
|
|
//Base Configuration Registers Field
|
|
'h080:s_axi_rdata <= {31'd0, mac_sw_rst};
|
|
'h081:s_axi_rdata <= {31'd0, phy_sw_rst};
|
|
'h082:s_axi_rdata <= {31'd0, dma_rx_rst};
|
|
'h083:s_axi_rdata <= {31'd0, dma_tx_rst};
|
|
default:s_axi_rdata <= 32'hEEEE_1111;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
s_axi_rvalid <= 1'b0;
|
|
else if((loc_raddr_vld == 1'b1) && (loc_rrdy == 1'b1))
|
|
s_axi_rvalid <= 1'b1;
|
|
else if(s_axi_rready == 1'b1)
|
|
s_axi_rvalid <= 1'b0;
|
|
end
|
|
|
|
assign s_axi_rresp = 2'h0;
|
|
|
|
/*----------------------------------------------------------------------------------*\
|
|
Register Space -- Base Configuration Registers Field
|
|
\*----------------------------------------------------------------------------------*/
|
|
|
|
//loc_addr = 0x000; axi_addr = 0x000; RW;
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
begin
|
|
mac_sw_rst <= 1'b0;
|
|
end
|
|
else if((s_axi_bvalid == 1'b1) && (loc_waddr == 'h080))
|
|
begin
|
|
mac_sw_rst <= loc_wdata[0];
|
|
end
|
|
end
|
|
|
|
//loc_addr = 0x001; axi_addr = 0x004; RW;
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
begin
|
|
phy_sw_rst <= 1'b0;
|
|
end
|
|
else if((s_axi_bvalid == 1'b1) && (loc_waddr == 'h081))
|
|
begin
|
|
phy_sw_rst <= loc_wdata[0];
|
|
end
|
|
end
|
|
|
|
//loc_addr = 0x002; axi_addr = 0x008; RW;
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
begin
|
|
dma_rx_rst <= 1'b0;
|
|
end
|
|
else if((s_axi_bvalid == 1'b1) && (loc_waddr == 'h082))
|
|
begin
|
|
dma_rx_rst <= loc_wdata[0];
|
|
end
|
|
end
|
|
|
|
|
|
//loc_addr = 0x003; axi_addr = 0x00C; RW;
|
|
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
|
|
begin
|
|
if(s_axi_aresetn == 1'b0)
|
|
begin
|
|
dma_tx_rst <= 1'b0;
|
|
end
|
|
else if((s_axi_bvalid == 1'b1) && (loc_waddr == 'h083))
|
|
begin
|
|
dma_tx_rst <= loc_wdata[0];
|
|
end
|
|
end
|
|
|
|
|
|
/*----------------------------------------------------------------------------------*\
|
|
Register Space -- The End
|
|
\*----------------------------------------------------------------------------------*/
|
|
reset #(
|
|
.IN_RST_ACTIVE ("HIGH"),
|
|
.OUT_RST_ACTIVE ("HIGH"),
|
|
.CYCLE (2)
|
|
) inst_reset (
|
|
.i_arst (mac_ext_rst),
|
|
.i_clk (s_eth_tx_clk),
|
|
.o_srst (w_eth_mac_rst)
|
|
|
|
);
|
|
|
|
assign w_rd_en = (next_rd_state == 1);
|
|
assign write_cnt_next = (s_eth_tx_tkeep ? write_cnt + 1 : write_cnt);
|
|
assign s_eth_tx_tready = !w_tx_full;
|
|
assign m_eth_tx_tvalid = rd_state != 0;
|
|
assign m_eth_tx_tdata = w_eth_tx_tdata;
|
|
assign m_eth_tx_tdest = w_eth_tx_tdest;
|
|
assign m_eth_tx_tlast = r_eth_tx_tlast;
|
|
|
|
always @(posedge s_eth_tx_clk or posedge w_eth_mac_rst)
|
|
begin
|
|
if (w_eth_mac_rst)
|
|
begin
|
|
write_cnt <= 16'd0;
|
|
end
|
|
else begin
|
|
if (s_eth_tx_tvalid && s_eth_tx_tready)
|
|
begin
|
|
if (s_eth_tx_tlast)
|
|
begin
|
|
write_cnt <= 16'd0;
|
|
end
|
|
else if (s_eth_tx_tkeep)
|
|
begin
|
|
write_cnt <= write_cnt + 1'b1;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(*)
|
|
begin
|
|
case (rd_state)
|
|
2'b00:
|
|
begin
|
|
if (!w_trans_empty)
|
|
begin
|
|
next_rd_state = 2'b01;
|
|
end else
|
|
begin
|
|
next_rd_state = 2'b00;
|
|
end
|
|
end
|
|
2'b01:
|
|
begin
|
|
if (!m_eth_tx_tready)
|
|
begin
|
|
next_rd_state = 2'b10;
|
|
end else if (m_eth_tx_tlast)
|
|
begin
|
|
next_rd_state = 2'b00;
|
|
end else
|
|
begin
|
|
next_rd_state = 2'b01;
|
|
end
|
|
end
|
|
2'b10:
|
|
begin
|
|
if (m_eth_tx_tvalid && m_eth_tx_tready)
|
|
begin
|
|
if (m_eth_tx_tlast)
|
|
next_rd_state = 2'b00;
|
|
else
|
|
next_rd_state = 2'b01;
|
|
end else
|
|
begin
|
|
next_rd_state = 2'b10;
|
|
end
|
|
end
|
|
default:
|
|
begin
|
|
next_rd_state = 2'b00;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(posedge s_eth_tx_clk or posedge w_eth_mac_rst)
|
|
begin
|
|
if (w_eth_mac_rst)
|
|
begin
|
|
rd_state = 2'b00;
|
|
read_cnt = 16'd0;
|
|
r_eth_tx_tlast <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
rd_state <= next_rd_state;
|
|
if (next_rd_state == 2'b00)
|
|
begin
|
|
read_cnt <= 16'd0;
|
|
r_eth_tx_tlast <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
if (w_rd_en)
|
|
begin
|
|
read_cnt <= read_cnt + 1'b1;
|
|
if ((read_cnt + 1'b1) == write_cnt_rd)
|
|
begin
|
|
r_eth_tx_tlast <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
gTSE_core_fifo_data u_standard_tx_fifo_trans (
|
|
.a_rst_i (w_eth_mac_rst),
|
|
.wr_clk_i (s_eth_tx_clk),
|
|
.wr_en_i (s_eth_tx_tvalid && s_eth_tx_tready && s_eth_tx_tkeep),
|
|
.wdata ({s_eth_tx_tkeep,s_eth_tx_tdest, s_eth_tx_tdata}),
|
|
.rd_clk_i (s_eth_tx_clk),
|
|
.rd_en_i (w_rd_en),
|
|
.rdata ({w_eth_tx_tkeep, w_eth_tx_tdest, w_eth_tx_tdata}),
|
|
.full_o (w_tx_full),
|
|
.empty_o (w_tx_empty),
|
|
.wr_datacount_o (),
|
|
.rd_datacount_o (w_txdata_rd_datacount),
|
|
.rst_busy (w_tx_size_busy)
|
|
);
|
|
|
|
gTSE_core_fifo_ctrl u_fwft_tx_fifo_data (
|
|
.a_rst_i (w_eth_mac_rst),
|
|
.wr_clk_i (s_eth_tx_clk),
|
|
.wr_en_i (s_eth_tx_tvalid && s_eth_tx_tready && s_eth_tx_tlast),
|
|
.wdata (write_cnt_next),
|
|
.rd_clk_i (s_eth_tx_clk),
|
|
.rd_en_i (m_eth_tx_tvalid && m_eth_tx_tready && m_eth_tx_tlast),
|
|
.rdata (write_cnt_rd),
|
|
.full_o (w_trans_full),
|
|
.empty_o (w_trans_empty),
|
|
.wr_datacount_o (),
|
|
.rd_datacount_o (w_trans_rdcnt),
|
|
.rst_busy (w_trans_rst_busy)
|
|
);
|
|
|
|
always @(posedge s_eth_tx_clk or posedge w_eth_mac_rst)
|
|
begin
|
|
if (w_eth_mac_rst)
|
|
begin
|
|
error <= 1'b0;
|
|
end else
|
|
begin
|
|
if ((w_trans_full && s_eth_tx_tvalid && s_eth_tx_tready && s_eth_tx_tlast ) || w_trans_rst_busy || (w_trans_empty && w_rd_en))
|
|
error <= 1'b1;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////
|
|
module reset
|
|
#(
|
|
parameter IN_RST_ACTIVE = "LOW",
|
|
parameter OUT_RST_ACTIVE = "HIGH",
|
|
parameter CYCLE = 1
|
|
)
|
|
(
|
|
input i_arst,
|
|
input i_clk,
|
|
|
|
output o_srst
|
|
);
|
|
|
|
(* async_reg = "true" *) reg [CYCLE-1:0]r_srst_1P;
|
|
|
|
genvar i;
|
|
generate
|
|
if (IN_RST_ACTIVE == "LOW")
|
|
begin
|
|
if (OUT_RST_ACTIVE == "LOW")
|
|
begin
|
|
always@(negedge i_arst or posedge i_clk)
|
|
begin
|
|
if (~i_arst)
|
|
r_srst_1P[0] <= 1'b0;
|
|
else
|
|
r_srst_1P[0] <= 1'b1;
|
|
end
|
|
|
|
for (i=0; i<CYCLE-1; i=i+1)
|
|
begin
|
|
always@(negedge i_arst or posedge i_clk)
|
|
begin
|
|
if (~i_arst)
|
|
r_srst_1P[i+1] <= 1'b0;
|
|
else
|
|
r_srst_1P[i+1] <= r_srst_1P[i];
|
|
end
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
always@(negedge i_arst or posedge i_clk)
|
|
begin
|
|
if (~i_arst)
|
|
r_srst_1P[0] <= 1'b1;
|
|
else
|
|
r_srst_1P[0] <= 1'b0;
|
|
end
|
|
|
|
for (i=0; i<CYCLE-1; i=i+1)
|
|
begin
|
|
always@(negedge i_arst or posedge i_clk)
|
|
begin
|
|
if (~i_arst)
|
|
r_srst_1P[i+1] <= 1'b1;
|
|
else
|
|
r_srst_1P[i+1] <= r_srst_1P[i];
|
|
end
|
|
end
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (OUT_RST_ACTIVE == "LOW")
|
|
begin
|
|
always@(posedge i_arst or posedge i_clk)
|
|
begin
|
|
if (i_arst)
|
|
r_srst_1P[0] <= 1'b0;
|
|
else
|
|
r_srst_1P[0] <= 1'b1;
|
|
end
|
|
|
|
for (i=0; i<CYCLE-1; i=i+1)
|
|
begin
|
|
always@(posedge i_arst or posedge i_clk)
|
|
begin
|
|
if (i_arst)
|
|
r_srst_1P[i+1] <= 1'b0;
|
|
else
|
|
r_srst_1P[i+1] <= r_srst_1P[i];
|
|
end
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
always@(posedge i_arst or posedge i_clk)
|
|
begin
|
|
if (i_arst)
|
|
r_srst_1P[0] <= 1'b1;
|
|
else
|
|
r_srst_1P[0] <= 1'b0;
|
|
end
|
|
|
|
for (i=0; i<CYCLE-1; i=i+1)
|
|
begin
|
|
always@(posedge i_arst or posedge i_clk)
|
|
begin
|
|
if (i_arst)
|
|
r_srst_1P[i+1] <= 1'b1;
|
|
else
|
|
r_srst_1P[i+1] <= r_srst_1P[i];
|
|
end
|
|
end
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
assign o_srst = r_srst_1P[CYCLE-1];
|
|
|
|
endmodule
|
|
|
|
module reset_ctrl
|
|
#(
|
|
parameter NUM_RST = 1,
|
|
parameter CYCLE = 1,
|
|
parameter IN_RST_ACTIVE = 1'b1,
|
|
parameter OUT_RST_ACTIVE = 1'b1
|
|
)
|
|
(
|
|
input [NUM_RST-1:0] i_arst,
|
|
input [NUM_RST-1:0] i_clk,
|
|
output [NUM_RST-1:0] o_srst
|
|
);
|
|
|
|
genvar i;
|
|
generate
|
|
for (i=0; i<NUM_RST; i=i+1)
|
|
begin
|
|
if (IN_RST_ACTIVE & (1'b1 << i))
|
|
begin
|
|
if (OUT_RST_ACTIVE & (1'b1 << i))
|
|
begin
|
|
reset
|
|
#(
|
|
.IN_RST_ACTIVE ("HIGH"),
|
|
.OUT_RST_ACTIVE ("HIGH"),
|
|
.CYCLE (CYCLE)
|
|
)
|
|
inst_sysclk_rstn
|
|
(
|
|
.i_arst (i_arst[i]),
|
|
.i_clk (i_clk[i]),
|
|
.o_srst (o_srst[i])
|
|
);
|
|
end
|
|
else
|
|
begin
|
|
reset
|
|
#(
|
|
.IN_RST_ACTIVE ("HIGH"),
|
|
.OUT_RST_ACTIVE ("LOW"),
|
|
.CYCLE (CYCLE)
|
|
)
|
|
inst_sysclk_rstn
|
|
(
|
|
.i_arst (i_arst[i]),
|
|
.i_clk (i_clk[i]),
|
|
.o_srst (o_srst[i])
|
|
);
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if (OUT_RST_ACTIVE & (1'b1 << i))
|
|
begin
|
|
reset
|
|
#(
|
|
.IN_RST_ACTIVE ("LOW"),
|
|
.OUT_RST_ACTIVE ("HIGH"),
|
|
.CYCLE (CYCLE)
|
|
)
|
|
inst_sysclk_rstn
|
|
(
|
|
.i_arst (i_arst[i]),
|
|
.i_clk (i_clk[i]),
|
|
.o_srst (o_srst[i])
|
|
);
|
|
end
|
|
else
|
|
begin
|
|
reset
|
|
#(
|
|
.IN_RST_ACTIVE ("LOW"),
|
|
.OUT_RST_ACTIVE ("LOW"),
|
|
.CYCLE (CYCLE)
|
|
)
|
|
inst_sysclk_rstn
|
|
(
|
|
.i_arst (i_arst[i]),
|
|
.i_clk (i_clk[i]),
|
|
.o_srst (o_srst[i])
|
|
);
|
|
end
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
////////////////////////////////////////////////////////////////////////////////////////////
|
|
|