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Merge branch '41-remove-addr-decode-and-properly-rename-clk_2-in-fpga' into 'master'

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Resolve "Remove addr decode and properly rename clk_2 in fpga"

Closes #41

See merge request bslathi19/super6502!34
This commit is contained in:
Byron Lathi
2023-10-16 04:46:14 +00:00
parent fd4dbfaf81 b179997da8
commit 0f8241f30f
5 changed files with 251 additions and 122 deletions
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144
hw/efinix_fpga/debug_profile.wizard.json
View File

@@ -8,7 +8,7 @@
"trigout_en": false,
"auto_inserted": true,
"capture_control": false,
"data_depth": 16384,
"data_depth": 8192,
"input_pipeline": 1,
"probes": [
{
@@ -35,6 +35,11 @@
"name": "cpu_rdy",
"width": 1,
"probe_type": 1
},
{
"name": "w_sdram_addr",
"width": 25,
"probe_type": 1
}
]
}
@@ -299,6 +304,131 @@
"name": "la0_probe4",
"net": "cpu_rdy",
"path": []
},
{
"name": "la0_probe5[0]",
"net": "w_sdram_addr[0]",
"path": []
},
{
"name": "la0_probe5[1]",
"net": "w_sdram_addr[1]",
"path": []
},
{
"name": "la0_probe5[2]",
"net": "w_sdram_addr[2]",
"path": []
},
{
"name": "la0_probe5[3]",
"net": "w_sdram_addr[3]",
"path": []
},
{
"name": "la0_probe5[4]",
"net": "w_sdram_addr[4]",
"path": []
},
{
"name": "la0_probe5[5]",
"net": "w_sdram_addr[5]",
"path": []
},
{
"name": "la0_probe5[6]",
"net": "w_sdram_addr[6]",
"path": []
},
{
"name": "la0_probe5[7]",
"net": "w_sdram_addr[7]",
"path": []
},
{
"name": "la0_probe5[8]",
"net": "w_sdram_addr[8]",
"path": []
},
{
"name": "la0_probe5[9]",
"net": "w_sdram_addr[9]",
"path": []
},
{
"name": "la0_probe5[10]",
"net": "w_sdram_addr[10]",
"path": []
},
{
"name": "la0_probe5[11]",
"net": "w_sdram_addr[11]",
"path": []
},
{
"name": "la0_probe5[12]",
"net": "w_sdram_addr[12]",
"path": []
},
{
"name": "la0_probe5[13]",
"net": "w_sdram_addr[13]",
"path": []
},
{
"name": "la0_probe5[14]",
"net": "w_sdram_addr[14]",
"path": []
},
{
"name": "la0_probe5[15]",
"net": "w_sdram_addr[15]",
"path": []
},
{
"name": "la0_probe5[16]",
"net": "w_sdram_addr[16]",
"path": []
},
{
"name": "la0_probe5[17]",
"net": "w_sdram_addr[17]",
"path": []
},
{
"name": "la0_probe5[18]",
"net": "w_sdram_addr[18]",
"path": []
},
{
"name": "la0_probe5[19]",
"net": "w_sdram_addr[19]",
"path": []
},
{
"name": "la0_probe5[20]",
"net": "w_sdram_addr[20]",
"path": []
},
{
"name": "la0_probe5[21]",
"net": "w_sdram_addr[21]",
"path": []
},
{
"name": "la0_probe5[22]",
"net": "w_sdram_addr[22]",
"path": []
},
{
"name": "la0_probe5[23]",
"net": "w_sdram_addr[23]",
"path": []
},
{
"name": "la0_probe5[24]",
"net": "w_sdram_addr[24]",
"path": []
}
]
}
@@ -312,7 +442,7 @@
],
"session": {
"wizard": {
"data_depth": 16384,
"data_depth": 8192,
"capture_control": false,
"selected_nets": [
{
@@ -358,6 +488,16 @@
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
},
{
"name": "w_sdram_addr",
"width": 25,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": [],
"net_idx_left": 24,
"net_idx_right": 0
}
],
"top_module": "super6502",

28
hw/efinix_fpga/src/addr_decode.sv
View File

@@ -1,28 +0,0 @@
module addr_decode
(
input logic [15:0] i_addr,
output logic o_rom_cs,
output logic o_leds_cs,
output logic o_timer_cs,
output logic o_multiplier_cs,
output logic o_divider_cs,
output logic o_uart_cs,
output logic o_spi_cs,
output logic o_sdram_cs
);
// assign o_rom_cs = '1;
always_comb begin
o_rom_cs = (i_addr >= 16'hf000) ? 1 : 0;
end
assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff;
assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffb;
assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7;
assign o_divider_cs = i_addr >= 16'hefe8 && i_addr <= 16'hefef;
assign o_uart_cs = i_addr >= 16'hefe6 && i_addr <= 16'hefe7;
assign o_spi_cs = i_addr >= 16'hefd8 && i_addr <= 16'hefdb;
assign o_leds_cs = i_addr == 16'hefff;
assign o_sdram_cs = i_addr < 16'he000;
endmodule

31
hw/efinix_fpga/src/super6502.sv
View File

@@ -1,4 +1,8 @@
module super6502
#(
parameter CONTROL_REG_START = 16'h0a00,
parameter CONTROL_REG_SIZE = 16'h0600
)
(
input logic i_sysclk, // Controller Clock (100MHz)
input logic i_sdrclk, // t_su and t_wd clock (200MHz)
@@ -71,6 +75,14 @@ always @(posedge clk_cpu) begin
end
end
logic w_control_reg_cs;
// 0a00 - 0xffff
assign w_control_reg_cs = (cpu_addr >= CONTROL_REG_START && cpu_addr < CONTROL_REG_START + CONTROL_REG_SIZE);
// The w_control_reg_cs is redundant but whatever
assign o_mapper_cs = (cpu_addr >= 16'h0a00 && cpu_addr <= 25'h0a20) && w_control_reg_cs;
logic w_rom_cs;
logic w_leds_cs;
@@ -79,6 +91,7 @@ logic w_timer_cs;
logic w_multiplier_cs;
logic w_divider_cs;
logic w_uart_cs;
logic w_mapper_cs;
logic w_spi_cs;
@@ -89,6 +102,7 @@ logic [7:0] w_multiplier_data_out;
logic [7:0] w_divider_data_out;
logic [7:0] w_uart_data_out;
logic [7:0] w_spi_data_out;
logic [7:0] w_mapper_data_out;
logic [7:0] w_sdram_data_out;
always_comb begin
@@ -118,10 +132,15 @@ always_comb begin
cpu_data_out = w_spi_data_out;
else if (w_sdram_cs)
cpu_data_out = w_sdram_data_out;
else if (w_mapper_cs)
cpu_data_out = w_mapper_data_out;
else
cpu_data_out = 'x;
end
logic [24:0] w_sdram_addr;
rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
.addr(cpu_addr[11:0]),
.clk(clk_cpu),
@@ -146,7 +165,7 @@ timer u_timer(
.o_data(w_timer_data_out),
.cs(w_timer_cs),
.rwb(cpu_rwb),
.addr(cpu_addr[1:0]),
.addr(w_sdram_addr[1:0]),
.irqb(w_timer_irqb)
);
@@ -157,7 +176,7 @@ multiplier u_multiplier(
.o_data(w_multiplier_data_out),
.cs(w_multiplier_cs),
.rwb(cpu_rwb),
.addr(cpu_addr[2:0])
.addr(w_sdram_addr[2:0])
);
divider_wrapper u_divider(
@@ -168,7 +187,7 @@ divider_wrapper u_divider(
.o_data(w_divider_data_out),
.cs(w_divider_cs),
.rwb(cpu_rwb),
.addr(cpu_addr[2:0])
.addr(w_sdram_addr[2:0])
);
logic w_uart_irqb;
@@ -181,7 +200,7 @@ uart_wrapper u_uart(
.o_data(w_uart_data_out),
.cs(w_uart_cs),
.rwb(cpu_rwb),
.addr(cpu_addr[0]),
.addr(w_sdram_addr[0]),
.rx_i(uart_rx),
.tx_o(uart_tx),
.irqb(w_uart_irqb)
@@ -192,7 +211,7 @@ spi_controller spi_controller(
.i_rst(~cpu_resb),
.i_cs(w_spi_cs),
.i_rwb(cpu_rwb),
.i_addr(cpu_addr[1:0]),
.i_addr(w_sdram_addr[1:0]),
.i_data(cpu_data_in),
.o_data(w_spi_data_out),
@@ -213,7 +232,7 @@ sdram_adapter u_sdram_adapter(
.i_cs(w_sdram_cs),
.i_rwb(cpu_rwb),
.i_addr(cpu_addr),
.i_addr(w_sdram_addr),
.i_data(cpu_data_in),
.o_data(w_sdram_data_out),

4
hw/efinix_fpga/super6502.peri.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2023.1.150" db_version="20231999" last_change_date="Sat Jul 22 17:30:06 2023" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" version="2022.2.322" db_version="20231999" last_change_date="Sun Oct 15 21:05:41 2023" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
@@ -336,7 +336,7 @@
<efxpt:pll_info>
<efxpt:pll name="pll_cpu_clk" pll_def="PLL_TR1" ref_clock_name="i_sysclk" ref_clock_freq="100.0000" multiplier="16" pre_divider="2" post_divider="4" reset_name="pll_cpu_reset" locked_name="pll_cpu_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:output_clock name="clk_50" number="0" out_divider="4" adv_out_phase_shift="0"/>
<efxpt:output_clock name="clk_2" number="1" out_divider="100" adv_out_phase_shift="0"/>
<efxpt:output_clock name="clk_cpu" number="1" out_divider="100" adv_out_phase_shift="0"/>
<efxpt:adv_prop ref_clock_mode="core" ref_clock1_name="" ext_ref_clock_id="2" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
</efxpt:pll>
<efxpt:pll name="pll_sdram_clk" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.0000" multiplier="8" pre_divider="4" post_divider="2" reset_name="o_pll_reset" locked_name="i_pll_locked" is_ipfrz="false" is_bypass_lock="true">

166
hw/efinix_fpga/super6502.xml
View File

@@ -1,106 +1,104 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Sun October 15 2023 13:52:14" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Sun Oct 15 2023 09:26:48 PM" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
<efx:timing_model name="C4"/>
<efx:family name="Trion" />
<efx:device name="T20F256" />
<efx:timing_model name="C4" />
</efx:device_info>
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
<efx:top_module name="super6502"/>
<efx:design_file name="src/super6502.sv" version="default" library="default"/>
<efx:design_file name="src/leds.sv" version="default" library="default"/>
<efx:design_file name="src/addr_decode.sv" version="default" library="default"/>
<efx:design_file name="src/sdram_adapter.sv" version="default" library="default"/>
<efx:design_file name="src/timer.sv" version="default" library="default"/>
<efx:design_file name="src/interrupt_controller.sv" version="default" library="default"/>
<efx:design_file name="src/multiplier.sv" version="default" library="default"/>
<efx:design_file name="src/divider_wrapper.sv" version="default" library="default"/>
<efx:design_file name="src/uart_wrapper.sv" version="default" library="default"/>
<efx:design_file name="src/sd_controller.sv" version="default" library="default"/>
<efx:design_file name="src/crc7.sv" version="default" library="default"/>
<efx:design_file name="src/rom.sv" version="default" library="default"/>
<efx:design_file name="src/spi_controller.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
<efx:top_module name="super6502" />
<efx:design_file name="src/super6502.sv" version="default" library="default" />
<efx:design_file name="src/leds.sv" version="default" library="default" />
<efx:design_file name="src/sdram_adapter.sv" version="default" library="default" />
<efx:design_file name="src/timer.sv" version="default" library="default" />
<efx:design_file name="src/interrupt_controller.sv" version="default" library="default" />
<efx:design_file name="src/multiplier.sv" version="default" library="default" />
<efx:design_file name="src/divider_wrapper.sv" version="default" library="default" />
<efx:design_file name="src/uart_wrapper.sv" version="default" library="default" />
<efx:design_file name="src/sd_controller.sv" version="default" library="default" />
<efx:design_file name="src/crc7.sv" version="default" library="default" />
<efx:design_file name="src/rom.sv" version="default" library="default" />
<efx:design_file name="src/spi_controller.sv" version="default" library="default" />
<efx:top_vhdl_arch name="" />
</efx:design_info>
<efx:constraint_info>
<efx:sdc_file name="constraints/super6502.pt.sdc"/>
<efx:inter_file name=""/>
<efx:sdc_file name="constraints/super6502.pt.sdc" />
<efx:inter_file name="" />
</efx:constraint_info>
<efx:sim_info/>
<efx:misc_info/>
<efx:sim_info />
<efx:misc_info />
<efx:ip_info>
<efx:ip instance_name="sdram_controller" path="ip/sdram_controller/settings.json">
<efx:ip_src_file name="sdram_controller.v"/>
<efx:ip_src_file name="sdram_controller.v" />
</efx:ip>
<efx:ip instance_name="divider" path="ip/divider/settings.json">
<efx:ip_src_file name="divider.v"/>
<efx:ip_src_file name="divider.v" />
</efx:ip>
<efx:ip instance_name="uart" path="ip/uart/settings.json">
<efx:ip_src_file name="uart.v"/>
<efx:ip_src_file name="uart.v" />
</efx:ip>
</efx:ip_info>
<efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
<efx:param name="mode" value="speed" value_type="e_option"/>
<efx:param name="max_ram" value="-1" value_type="e_integer"/>
<efx:param name="max_mult" value="-1" value_type="e_integer"/>
<efx:param name="infer-clk-enable" value="3" value_type="e_option"/>
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/>
<efx:param name="fanout-limit" value="0" value_type="e_integer"/>
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="retiming" value="1" value_type="e_option"/>
<efx:param name="seq_opt" value="1" value_type="e_option"/>
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/>
<efx:param name="operator-sharing" value="0" value_type="e_option"/>
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="min-sr-fanout" value="0" value_type="e_option"/>
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/>
<efx:param name="blackbox-error" value="1" value_type="e_option"/>
<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
<efx:param name="mult-decomp-retime" value="0" value_type="e_option"/>
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option"/>
<efx:param name="include" value="ip/sdram_controller" value_type="e_string"/>
<efx:param name="include" value="ip/divider" value_type="e_string"/>
<efx:param name="include" value="ip/uart" value_type="e_string"/>
<efx:param name="work_dir" value="work_syn" value_type="e_string" />
<efx:param name="write_efx_verilog" value="on" value_type="e_bool" />
<efx:param name="mode" value="speed" value_type="e_option" />
<efx:param name="max_ram" value="-1" value_type="e_integer" />
<efx:param name="max_mult" value="-1" value_type="e_integer" />
<efx:param name="infer-clk-enable" value="3" value_type="e_option" />
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option" />
<efx:param name="fanout-limit" value="0" value_type="e_integer" />
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="retiming" value="1" value_type="e_option" />
<efx:param name="seq_opt" value="1" value_type="e_option" />
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option" />
<efx:param name="operator-sharing" value="0" value_type="e_option" />
<efx:param name="optimize-adder-tree" value="0" value_type="e_option" />
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option" />
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option" />
<efx:param name="min-sr-fanout" value="0" value_type="e_option" />
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option" />
<efx:param name="blackbox-error" value="1" value_type="e_option" />
<efx:param name="allow-const-ram-index" value="0" value_type="e_option" />
<efx:param name="hdl-compile-unit" value="1" value_type="e_option" />
<efx:param name="create-onehot-fsms" value="0" value_type="e_option" />
<efx:param name="min-ce-fanout" value="0" value_type="e_integer" />
<efx:param name="mult-decomp-retime" value="0" value_type="e_option" />
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option" />
<efx:param name="include" value="ip/sdram_controller" value_type="e_string" />
<efx:param name="include" value="ip/divider" value_type="e_string" />
<efx:param name="include" value="ip/uart" value_type="e_string" />
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
<efx:param name="verbose" value="off" value_type="e_bool"/>
<efx:param name="load_delaym" value="on" value_type="e_bool"/>
<efx:param name="optimization_level" value="NULL" value_type="e_option"/>
<efx:param name="seed" value="1" value_type="e_integer"/>
<efx:param name="placer_effort_level" value="2" value_type="e_option"/>
<efx:param name="max_threads" value="-1" value_type="e_integer"/>
<efx:param name="work_dir" value="work_pnr" value_type="e_string" />
<efx:param name="verbose" value="off" value_type="e_bool" />
<efx:param name="load_delaym" value="on" value_type="e_bool" />
<efx:param name="optimization_level" value="NULL" value_type="e_option" />
<efx:param name="seed" value="1" value_type="e_integer" />
<efx:param name="placer_effort_level" value="2" value_type="e_option" />
<efx:param name="max_threads" value="-1" value_type="e_integer" />
</efx:place_and_route>
<efx:bitstream_generation tool_name="efx_pgm">
<efx:param name="mode" value="active" value_type="e_option"/>
<efx:param name="width" value="1" value_type="e_option"/>
<efx:param name="enable_roms" value="smart" value_type="e_option"/>
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
<efx:param name="bitstream_compression" value="off" value_type="e_bool"/>
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option"/>
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
<efx:param name="cold_boot" value="off" value_type="e_bool"/>
<efx:param name="cascade" value="off" value_type="e_option"/>
<efx:param name="generate_bit" value="on" value_type="e_bool"/>
<efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
<efx:param name="generate_hex" value="on" value_type="e_bool"/>
<efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
<efx:param name="four_byte_addressing" value="off" value_type="e_bool"/>
<efx:param name="mode" value="active" value_type="e_option" />
<efx:param name="width" value="1" value_type="e_option" />
<efx:param name="enable_roms" value="smart" value_type="e_option" />
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool" />
<efx:param name="io_weak_pullup" value="on" value_type="e_bool" />
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option" />
<efx:param name="bitstream_compression" value="off" value_type="e_bool" />
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool" />
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option" />
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string" />
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool" />
<efx:param name="cold_boot" value="off" value_type="e_bool" />
<efx:param name="cascade" value="off" value_type="e_option" />
<efx:param name="generate_bit" value="on" value_type="e_bool" />
<efx:param name="generate_bitbin" value="off" value_type="e_bool" />
<efx:param name="generate_hex" value="on" value_type="e_bool" />
<efx:param name="generate_hexbin" value="off" value_type="e_bool" />
<efx:param name="four_byte_addressing" value="off" value_type="e_bool" />
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
<efx:param name="work_dir" value="work_dbg" value_type="e_string" />
<efx:param name="auto_instantiation" value="off" value_type="e_bool" />
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string" />
</efx:debugger>
</efx:project>
</efx:project>