bslathi19/super6502
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Ignore all output files

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This commit is contained in:
Byron Lathi
2022-03-14 16:58:44 -05:00
parent ac3f5a0fca
commit a627d38778
3 changed files with 1 additions and 23 deletions
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2
hw/fpga/.gitignore vendored
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@@ -70,6 +70,6 @@ greybox_tmp/
*/*_sim/
incremental_db/
db/
_output_files/
output_files/
PLLJ_PLLSPE_INFO.txt

13
hw/fpga/output_files/super6502.cdf
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@@ -1,13 +0,0 @@
/* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(10M50DAF484) Path("/home/byron/Projects/super6502/hw/fpga/output_files/") File("super6502.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

9
hw/fpga/output_files/super6502.sld
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@@ -1,9 +0,0 @@
<sld_project_info>
<sld_infos>
<sld_info hpath="sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:instrumentation_fabric" library="alt_sld_fab" name="instrumentation_fabric">
<assignment_values>
<assignment_value text="QSYS_NAME alt_sld_fab HAS_SOPCINFO 1"/>
</assignment_values>
</sld_info>
</sld_infos>
</sld_project_info>