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Add LED module and address decoding; disable LA

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The Logic analyzer isn't that useful anyway since it does not track
rising and falling edges.
This commit is contained in:
Byron Lathi
2022-12-20 19:26:24 -05:00
parent aefa3d23f3
commit b8161e3082
8 changed files with 181 additions and 39 deletions
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12
hw/efinix_fpga/addr_decode.sv Normal file
View File

@@ -0,0 +1,12 @@
module addr_decode
(
input [15:0] i_addr,
output o_rom_cs,
output o_leds_cs
);
assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff;
assign o_leds_cs = i_addr == 16'hefff;
endmodule

74
hw/efinix_fpga/debug_profile.wizard.json
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@@ -3,7 +3,7 @@
{
"name": "la0",
"type": "la",
"uuid": "244dbd2d34ea40fba571b257d0a2bb75",
"uuid": "7ac38c47d15d4906b7e4dfa4b8e0f620",
"trigin_en": false,
"trigout_en": false,
"auto_inserted": true,
@@ -19,42 +19,52 @@
{
"name": "cpu_addr",
"width": 16,
"probe_type": 1
"probe_type": 2
},
{
"name": "button_reset",
"width": 1,
"probe_type": 1
"probe_type": 2
},
{
"name": "cpu_data_in",
"width": 8,
"probe_type": 1
"probe_type": 2
},
{
"name": "cpu_rwb",
"width": 1,
"probe_type": 1
"probe_type": 2
},
{
"name": "cpu_sync",
"width": 1,
"probe_type": 1
"probe_type": 2
},
{
"name": "cpu_data_out",
"width": 8,
"probe_type": 1
"probe_type": 2
},
{
"name": "cpu_data_oe",
"width": 8,
"probe_type": 1
"probe_type": 2
},
{
"name": "cpu_phi2",
"width": 1,
"probe_type": 1
"probe_type": 2
},
{
"name": "w_rom_cs",
"width": 1,
"probe_type": 2
},
{
"name": "boot_rom/re",
"width": 1,
"probe_type": 2
}
]
}
@@ -409,6 +419,18 @@
"name": "la0_probe8",
"net": "cpu_phi2",
"path": []
},
{
"name": "la0_probe9",
"net": "w_rom_cs",
"path": []
},
{
"name": "la0_probe10",
"net": "re",
"path": [
"boot_rom"
]
}
]
}
@@ -437,7 +459,7 @@
"name": "cpu_addr",
"width": 16,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"selected_probe_type": "DATA ONLY",
"child": [],
"path": [],
"net_idx_left": 15,
@@ -447,7 +469,7 @@
"name": "button_reset",
"width": 1,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"selected_probe_type": "DATA ONLY",
"child": [],
"path": []
},
@@ -455,7 +477,7 @@
"name": "cpu_data_in",
"width": 8,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"selected_probe_type": "DATA ONLY",
"child": [],
"path": [],
"net_idx_left": 7,
@@ -465,7 +487,7 @@
"name": "cpu_rwb",
"width": 1,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"selected_probe_type": "DATA ONLY",
"child": [],
"path": []
},
@@ -473,7 +495,7 @@
"name": "cpu_sync",
"width": 1,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"selected_probe_type": "DATA ONLY",
"child": [],
"path": []
},
@@ -481,7 +503,7 @@
"name": "cpu_data_out",
"width": 8,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"selected_probe_type": "DATA ONLY",
"child": [],
"path": [],
"net_idx_left": 7,
@@ -491,7 +513,7 @@
"name": "cpu_data_oe",
"width": 8,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"selected_probe_type": "DATA ONLY",
"child": [],
"path": [],
"net_idx_left": 7,
@@ -501,9 +523,27 @@
"name": "cpu_phi2",
"width": 1,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"selected_probe_type": "DATA ONLY",
"child": [],
"path": []
},
{
"name": "w_rom_cs",
"width": 1,
"clk_domain": "clk_2",
"selected_probe_type": "DATA ONLY",
"child": [],
"path": []
},
{
"name": "re",
"width": 1,
"clk_domain": "clk_2",
"selected_probe_type": "DATA ONLY",
"child": [],
"path": [
"boot_rom"
]
}
],
"top_module": "super6502",

4
hw/efinix_fpga/ip/bram/bram_ini.vh
View File

@@ -4,7 +4,7 @@ input integer index;//Mode type
input integer val_; //Port A index, Port B Index, Number of Items in Loop, Port A Start, Port B Start, reserved
case (index)
0: bram_ini_table=
(val_== 0)?256'h0000000000000000000000000000000000000000000000000000010004c000ea:
(val_== 0)?256'h00000000000000000fe00080000fa000d00003a000ef000ff0008d000ff000a9:
(val_== 1)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 2)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_== 3)?256'h0000000000000000000000000000000000000000000000000000000000000000:
@@ -23,7 +23,7 @@ case (index)
(val_==16)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==17)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==18)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==19)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==19)?256'h0000000000000ff0000000000000000000000000000000000000000000000000:
(val_==20)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==21)?256'h0000000000000000000000000000000000000000000000000000000000000000:
(val_==22)?256'h0000000000000000000000000000000000000000000000000000000000000000:

22
hw/efinix_fpga/ip/bram/init_hex.mem
View File

@@ -1,14 +1,13 @@
ea
4c
01
00
00
00
00
00
00
00
00
a9
ff
8d
ff
ef
3a
d0
fa
80
fe
00
00
00
@@ -252,5 +251,6 @@ ea
00
00
00
ff
00
00

29
hw/efinix_fpga/leds.sv Normal file
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@@ -0,0 +1,29 @@
module leds
(
input clk,
input [7:0] i_data,
output logic [7:0] o_data,
input cs,
input rwb,
output logic [7:0] o_leds
);
logic re, we;
assign re = rwb & cs;
assign we = ~rwb & cs;
logic [7:0] _data;
assign o_leds = ~_data;
always @(negedge clk) begin
if (re) begin
o_data <= _data;
end
else if (we) begin
_data <= i_data;
end
end
endmodule

27
hw/efinix_fpga/super6502.peri.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2022.1.226" db_version="20221999" last_change_date="Tue Dec 20 12:11:38 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2022.1.226" db_version="20221999" last_change_date="Tue Dec 20 17:56:46 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
@@ -130,12 +130,37 @@
<efxpt:gpio name="cpu_sync" gpio_def="GPIOL_67" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_sync" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="leds[0]" gpio_def="GPIOR_104" mode="output" bus_name="leds" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="leds[0]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="leds[1]" gpio_def="GPIOR_105" mode="output" bus_name="leds" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="leds[1]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="leds[2]" gpio_def="GPIOR_117" mode="output" bus_name="leds" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="leds[2]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="leds[3]" gpio_def="GPIOR_118" mode="output" bus_name="leds" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="leds[3]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="leds[4]" gpio_def="GPIOR_153" mode="output" bus_name="leds" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="leds[4]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="leds[5]" gpio_def="GPIOR_154" mode="output" bus_name="leds" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="leds[5]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="leds[6]" gpio_def="GPIOR_155" mode="output" bus_name="leds" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="leds[6]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="leds[7]" gpio_def="GPIOR_156" mode="output" bus_name="leds" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="leds[7]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="pll_in" gpio_def="GPIOR_157" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="pll_in" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:global_unused_config state="input with weak pullup"/>
<efxpt:bus name="cpu_data" mode="inout" msb="7" lsb="0"/>
<efxpt:bus name="cpu_addr" mode="input" msb="15" lsb="0"/>
<efxpt:bus name="leds" mode="output" msb="7" lsb="0"/>
</efxpt:gpio_info>
<efxpt:pll_info>
<efxpt:pll name="pll_cpu_clk" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.0000" multiplier="16" pre_divider="1" post_divider="8" reset_name="pll_cpu_reset" locked_name="pll_cpu_locked" is_ipfrz="false" is_bypass_lock="true">

46
hw/efinix_fpga/super6502.sv
View File

@@ -16,7 +16,9 @@ module super6502
output logic cpu_rdy,
output logic cpu_resb,
output logic pll_cpu_reset,
output logic cpu_phi2
output logic cpu_phi2,
output logic [7:0] leds
);
assign pll_cpu_reset = '1;
@@ -39,15 +41,47 @@ always @(posedge clk_2) begin
end
end
logic w_rom_cs;
logic w_leds_cs;
addr_decode u_addr_decode(
.i_addr(cpu_addr),
.o_rom_cs(w_rom_cs),
.o_leds_cs(w_leds_cs)
);
logic [7:0] w_rom_data_out;
logic [7:0] w_leds_data_out;
always_comb begin
if (w_rom_cs)
cpu_data_out = w_rom_data_out;
else if (w_leds_cs)
cpu_data_out= w_leds_data_out;
else
cpu_data_out = 'x;
end
efx_single_port_ram boot_rom(
.clk(clk_2), // clock input for one clock mode
.addr(cpu_addr[7:0]), // address input
.wclke('0), // Write clock-enable input
.byteen('0), // Byteen input
.we('0), // Write-enable input
.wclke('0), // Write clock-enable input
.byteen('0), // Byteen input
.we('0), // Write-enable input
.re(cpu_rwb), // Read-enable input
.rdata(cpu_data_out) // Read data output
.re(cpu_rwb & w_rom_cs), // Read-enable input
.rdata(w_rom_data_out) // Read data output
);
leds u_leds(
.clk(clk_2),
.i_data(cpu_data_in),
.o_data(w_leds_data_out),
.cs(w_leds_cs),
.rwb(cpu_rwb),
.o_leds(leds)
);
endmodule

6
hw/efinix_fpga/super6502.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Tue December 20 2022 17:26:24" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="change" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Tue December 20 2022 19:24:38" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
@@ -13,6 +13,8 @@
<efx:design_file name="ip/bram/bram_ini.vh" version="verilog_2k" library="default"/>
<efx:design_file name="ip/bram/efx_single_port_ram.v" version="verilog_2k" library="default"/>
<efx:design_file name="ip/bram/bram_wrapper_mwm.v" version="verilog_2k" library="default"/>
<efx:design_file name="leds.sv" version="default" library="default"/>
<efx:design_file name="addr_decode.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
</efx:design_info>
<efx:constraint_info>
@@ -77,7 +79,7 @@
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
<efx:param name="auto_instantiation" value="on" value_type="e_bool"/>
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
</efx:debugger>
</efx:project>