bslathi19/super6502
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add sim cpu

Browse Source
This commit is contained in:
Byron Lathi
2023-09-18 23:27:54 -07:00
parent b30e4c73fb
commit d37e32ec64
3 changed files with 16 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
.gitmodules vendored
View File

@@ -1,3 +1,6 @@
[submodule "sw/cc65"] [submodule "sw/cc65"]
path = sw/cc65 path = sw/cc65
url = https://git.byronlathi.com/bslathi19/cc65 url = https://git.byronlathi.com/bslathi19/cc65
[submodule "hw/efinix_fpga/simulation/verilog-6502"]
path = hw/efinix_fpga/simulation/verilog-6502
url = https://git.byronlathi.com/bslathi19/verilog-6502

12
hw/efinix_fpga/simulation/sim_top.sv Normal file
View File

@@ -0,0 +1,12 @@
module sim_top();
//TODO: this
cpu_65c02 u_cpu();
//TODO: also this
super6502 u_dut();
//TODO: decide what to do here
memory u_mem();
endmodule

1
hw/efinix_fpga/simulation/verilog-6502 Submodule

Submodule hw/efinix_fpga/simulation/verilog-6502 added at a5f605d00d