2 Commits

Author	SHA1	Message	Date
Byron Lathi	61f6e53327	Updates based on fpga test ... 1. in SD mode, CMD0 does not have a response, so we specifically ignore it. 2. The penable signal was messed up, although it looks like this doesn't matter anyway 3. The SD clock should be out of phase from the data signal by 180 degrees, so that we get max hold time	2024-03-10 22:09:55 -07:00
Byron Lathi	da41e60ee7	integrate sd controller and super simple tb	2024-03-10 11:31:07 -07:00