Byron Lathi
61f6e53327
Updates based on fpga test
...
1. in SD mode, CMD0 does not have a response, so we specifically ignore
it.
2. The penable signal was messed up, although it looks like this doesn't
matter anyway
3. The SD clock should be out of phase from the data signal by 180
degrees, so that we get max hold time
2024-03-10 22:09:55 -07:00
Byron Lathi
3c0bf9740c
Delete init hex on clean
2024-03-10 21:56:48 -07:00
Byron Lathi
142759ff59
Require python3.11
2024-03-10 16:42:21 -07:00
Byron Lathi
d3914b3a51
Add sd io pins
2024-03-10 16:09:12 -07:00
Byron Lathi
8f6d074255
Re-order init script to fix python import issue in synthesis
2024-03-10 12:55:38 -07:00
Byron Lathi
cb426670cd
Do synthesis with sd controller
2024-03-10 12:29:08 -07:00
Byron Lathi
da41e60ee7
integrate sd controller and super simple tb
2024-03-10 11:31:07 -07:00
Byron Lathi
81382925f8
Update rtl common and sd controller submodules
2024-03-10 10:24:50 -07:00
Byron Lathi
96e014567d
Add sd controller submodule
2024-03-04 00:06:29 -08:00
Byron Lathi
cf693a28d6
Merge branch '79-add-sdram' into 'AXI-Rewrite'
...
Resolve "Add SDRAM"
Closes #79
See merge request bslathi19/super6502!69
2024-03-04 07:38:13 +00:00
Byron Lathi
38c64e5551
Add sdram io to fpga
2024-03-03 23:35:25 -08:00
Byron Lathi
358dfdbe75
Add sdram io to fpga
2024-03-03 23:31:02 -08:00
Byron Lathi
aee04b777a
Fix sdram sim
...
Just need to add the RTL_SIM define
2024-03-03 21:33:28 -08:00
Byron Lathi
10a72d8e1f
Add sdram, don't think it works though
2024-03-03 20:43:37 -08:00
Byron Lathi
78dfb01bd7
Merge branch '81-add-simulation' into 'AXI-Rewrite'
...
Resolve "Add simulation"
Closes #81
See merge request bslathi19/super6502!68
2024-03-04 01:24:49 +00:00
Byron Lathi
12f54e7358
Merge branch '78-add-basic-software' into 81-add-simulation
2024-03-03 17:17:13 -08:00
Byron Lathi
01b1ecbcac
Add basic sim
2024-03-03 17:09:17 -08:00
Byron Lathi
3a9b967a5d
Merge branch '78-add-basic-software' into 'AXI-Rewrite'
...
Resolve "Add Basic Software"
Closes #78
See merge request bslathi19/super6502!67
2024-03-03 23:17:39 +00:00
Byron Lathi
ab9da189d1
Build software correctly, ignore debugger files
2024-03-03 14:50:40 -08:00
Byron Lathi
a343b23ddd
Make a venv in build
2024-03-03 13:13:41 -08:00
Byron Lathi
d60d7a25b2
Build everything in ci
2024-03-03 13:06:56 -08:00
Byron Lathi
42fbc17a2a
Add test code and top level Makefile
2024-03-03 12:52:44 -08:00
Byron Lathi
0ba5888aa1
Merge branch '77-add-axi-cpu-and-ram' into 'AXI-Rewrite'
...
Resolve "Add axi cpu and ram"
Closes #77
See merge request bslathi19/super6502!66
2024-03-03 19:38:10 +00:00
Byron Lathi
cd1dfa39cb
Fix PLL settings, add cpu output clock
2024-03-03 09:45:04 -08:00
Byron Lathi
6213d2a227
Use relative submodule paths for ci
2024-03-02 23:47:13 -08:00
Byron Lathi
31b3fdcfc9
Add basic ci and separate hw from all target
2024-03-02 22:55:39 -08:00
Byron Lathi
0752220b0e
Add basic project with cpu, ram and rom
2024-03-02 22:46:48 -08:00
Byron Lathi
0a0394ae33
Delete everything
2024-03-02 20:11:33 -08:00
Byron Lathi
273484b994
Merge branch '15-parse-the-read-only-file-system' into 'master'
...
Resolve "Parse the read-only file system"
Closes #15
See merge request bslathi19/super6502!64
2023-12-09 07:28:55 +00:00
Byron Lathi
0aca4af272
Add fixes for multiple sectors per cluster
2023-12-08 23:11:52 -08:00
Byron Lathi
5259fa8e65
Clear the carry flag, not the interrupt flag...
2023-12-08 08:12:50 -08:00
Byron Lathi
15e9b44318
Try clearing carry flag, that always helps. Also don't need verilog image anymore
2023-12-07 23:29:18 -08:00
Byron Lathi
6f16ac4daf
Add close, add filesystem code to main kernel for hardware testing
2023-12-07 08:10:45 -08:00
Byron Lathi
0327ab6a2b
Handle non-aligned reads
2023-12-06 21:02:41 -08:00
Byron Lathi
066bb0ee8c
Get read working a little bit more. Need to handle edge cases!
2023-12-05 23:29:00 -08:00
Byron Lathi
4c3c3fd731
Get something working with read
...
It is not reading offset correctly
2023-12-05 22:47:24 -08:00
Byron Lathi
48b39eb92d
Hack together open()
2023-12-05 19:10:27 -08:00
Byron Lathi
9ae1593957
Read out very long file, but not very long name
2023-12-05 08:29:44 -08:00
Byron Lathi
13738fc0d8
Read a little bit of the data from the file
2023-12-05 08:15:24 -08:00
Byron Lathi
946234381d
Look through files without trying too hard
2023-12-05 08:08:20 -08:00
Byron Lathi
2859055f98
Add some basic code, build kernel stuff in tree
2023-12-04 23:06:00 -08:00
Byron Lathi
902b1b5bb9
Save root cluster number
2023-12-04 21:57:36 -08:00
Byron Lathi
84814f05f9
Calculate data start
2023-12-04 18:40:21 -08:00
Byron Lathi
16a7f4db4d
Update cc65 pointer with PVSeek
2023-12-04 00:18:18 -08:00
Byron Lathi
5c74d161d4
Add some basic fat32 code
2023-12-03 23:27:45 -08:00
Byron Lathi
184c58b962
Add dumb multiplier code test
2023-12-02 20:31:59 -08:00
Byron Lathi
2f8290bfb0
Merge branch '16-realtime-clock-driver' into 'master'
...
Resolve "realtime clock driver"
Closes #16
See merge request bslathi19/super6502!62
2023-12-02 07:15:50 +00:00
Byron Lathi
de804ac3ca
Use tmp1 instead of y register
...
popa clobbers y
2023-12-01 22:53:41 -08:00
Byron Lathi
e8452eb98c
Add rtc_set
2023-12-01 08:28:38 -08:00
Byron Lathi
2cdd260a87
Change kicad library commit
...
Needs to be a commit in kicad-library-2
2023-12-01 07:57:38 -08:00
