Adds a 16x16 divider to go with the multiplier.
The divider is a single stage with no pipelining, which works at the
slow 2MHz frequency. Doing this lowers the maximum clock frequency to 5.
This is acceptable for now but means that the cpu can't be run at 14,
which is the maximum frequency.
I think that previously, I had not actually commited any of this to git.
This adds all of the new effinix stuff that I had been working on for
months.
The gist of all of this is that the intel fpga is expensive and does not
exist, whereas the effinix ones are not as expensive and more existant.
This redoes the project to use the dev board, as well as a custom board
that I may or may not make.
