Byron Lathi
|
c1f7b33dda
|
Update sd card emu
|
2023-10-03 23:08:56 -07:00 |
|
Byron Lathi
|
3a211faed7
|
Don't have sd wait in simulation
need to figure out how to set that RTL_SIM flag only when we are
compiling code for the sim
also bro the sim is like 8000x slower than irl.
|
2023-09-30 17:40:01 -07:00 |
|
Byron Lathi
|
cc32430f2a
|
Refactor makefile, update verilog-sd-emulator
|
2023-09-29 23:48:28 -07:00 |
|
Byron Lathi
|
913351efd4
|
Add sd emulator as submodule
|
2023-09-28 23:09:47 -07:00 |
|
Byron Lathi
|
4d0abbb508
|
Add sim uart
|
2023-09-27 22:15:27 -07:00 |
|
Byron Lathi
|
9e19a1eb72
|
Disable sdr debug, initialize uart status
|
2023-09-27 21:14:09 -07:00 |
|
Byron Lathi
|
ec4c3bab86
|
Update verilog-6502 bslathi19/verilog-6502@aaf4c084ef
|
2023-09-26 23:15:22 -07:00 |
|
Byron Lathi
|
c2dd5d616b
|
Gate rdy behind sdram_cs #28
|
2023-09-25 23:45:23 -07:00 |
|
Byron Lathi
|
4ee21f23b6
|
Up the sim time
|
2023-09-25 19:13:06 -07:00 |
|
Byron Lathi
|
95e05292cc
|
Fix clocks, define RTL_SIM
|
2023-09-24 23:58:32 -07:00 |
|
Byron Lathi
|
be68b4c9f9
|
Change sdrclk and sysclk to have aligned rising edges
|
2023-09-24 14:53:38 -07:00 |
|
Byron Lathi
|
13ea5ca71b
|
Add memory
|
2023-09-24 10:06:23 -07:00 |
|
Byron Lathi
|
d3aa195adf
|
Add updated sim cpu with fix
|
2023-09-23 10:49:44 -07:00 |
|
Byron Lathi
|
00173f4e89
|
Add submodule back
|
2023-09-23 09:59:39 -07:00 |
|
Byron Lathi
|
77dd4f1002
|
remove sim submodule
|
2023-09-23 09:59:09 -07:00 |
|
Byron Lathi
|
bc0ab7eb54
|
Fix infinite loop
|
2023-09-22 19:46:25 -07:00 |
|
Byron Lathi
|
5e03795c09
|
Get something simulated
Infinite loop being caused somewhere
|
2023-09-21 23:22:17 -07:00 |
|
Byron Lathi
|
1f503b2d80
|
update sim environment
|
2023-09-21 20:35:52 -07:00 |
|