bslathi19/super6502
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super6502/hw/fpga/simulation/modelsim
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Byron Lathi 38566f7b4a add testbench for SD command tx 
Sends a few commands which we know the proper checksum for and makes
sure that the bits on the output are correct.
2022-04-08 12:29:15 -05:00
..
.gitignore
Ignore more modelsim files
2022-03-13 19:39:14 -05:00
bb_spi_testbench.do
Add bb_spi_controller
2022-03-08 15:26:01 -06:00
crc7_testbench.do
Add tests for crc7
2022-04-08 00:56:14 -05:00
cs_testbench.do
Add addr_decode and testbench
2022-03-05 20:11:47 -06:00
irq_testbench.do
Add irq status register
2022-03-14 13:16:09 -05:00
mm_testbench.do
Update mm_testbench
2022-04-07 10:48:10 -05:00
sd_cmd_testbench.do
add testbench for SD command tx
2022-04-08 12:29:15 -05:00
super6502_run_msim_rtl_verilog.do
Add basic UART device
2022-03-13 19:42:41 -05:00
uart.do
Add write and puts tasks to the uart testbench
2022-03-14 00:04:04 -05:00