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ptp: Add PTP clock module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
343
rtl/ptp/taxi_ptp_clock.sv
Normal file
343
rtl/ptp/taxi_ptp_clock.sv
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@@ -0,0 +1,343 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2015-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PTP clock module
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*/
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module taxi_ptp_clock #
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(
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parameter PERIOD_NS_W = 4,
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parameter OFFSET_NS_W = 4,
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parameter FNS_W = 16,
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parameter PERIOD_NS_NUM = 32,
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parameter PERIOD_NS_DENOM = 5,
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parameter PIPELINE_OUTPUT = 0
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* Timestamp inputs for synchronization
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*/
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input wire logic [95:0] input_ts_tod,
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input wire logic input_ts_tod_valid,
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input wire logic [63:0] input_ts_rel,
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input wire logic input_ts_rel_valid,
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/*
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* Period adjustment
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*/
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input wire logic [PERIOD_NS_W-1:0] input_period_ns,
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input wire logic [FNS_W-1:0] input_period_fns,
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input wire logic input_period_valid,
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/*
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* Offset adjustment
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*/
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input wire logic [OFFSET_NS_W-1:0] input_adj_ns,
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input wire logic [FNS_W-1:0] input_adj_fns,
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input wire logic [15:0] input_adj_count,
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input wire logic input_adj_valid,
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output wire logic input_adj_active,
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/*
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* Drift adjustment
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*/
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input wire logic [FNS_W-1:0] input_drift_num,
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input wire logic [15:0] input_drift_denom,
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input wire logic input_drift_valid,
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/*
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* Timestamp outputs
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*/
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output wire logic [95:0] output_ts_tod,
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output wire logic output_ts_tod_step,
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output wire logic [63:0] output_ts_rel,
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output wire logic output_ts_rel_step,
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/*
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* PPS output
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*/
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output wire logic output_pps,
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output wire logic output_pps_str
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);
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localparam PERIOD_NS = PERIOD_NS_NUM / PERIOD_NS_DENOM;
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localparam PERIOD_NS_REM = PERIOD_NS_NUM - PERIOD_NS*PERIOD_NS_DENOM;
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localparam PERIOD_FNS = (PERIOD_NS_REM * {32'd1, {FNS_W{1'b0}}}) / (32+FNS_W)'(PERIOD_NS_DENOM);
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localparam PERIOD_FNS_REM = (PERIOD_NS_REM * {32'd1, {FNS_W{1'b0}}}) - PERIOD_FNS*PERIOD_NS_DENOM;
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localparam INC_NS_W = $clog2(2**PERIOD_NS_W + 2**OFFSET_NS_W);
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localparam [30:0] NS_PER_S = 31'd1_000_000_000;
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logic [PERIOD_NS_W-1:0] period_ns_reg = PERIOD_NS_W'(PERIOD_NS);
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logic [FNS_W-1:0] period_fns_reg = FNS_W'(PERIOD_FNS);
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logic [OFFSET_NS_W-1:0] adj_ns_reg = '0;
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logic [FNS_W-1:0] adj_fns_reg = '0;
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logic [15:0] adj_count_reg = '0;
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logic adj_active_reg = '0;
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logic [FNS_W-1:0] drift_num_reg = FNS_W'(PERIOD_FNS_REM);
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logic [15:0] drift_denom_reg = 16'(PERIOD_NS_DENOM);
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logic [15:0] drift_cnt_reg = '0;
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logic drift_apply_reg = 1'b0;
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logic [INC_NS_W-1:0] ts_inc_ns_reg = '0;
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logic [FNS_W-1:0] ts_inc_fns_reg = '0;
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logic [INC_NS_W-1:0] ts_inc_ns_delay_reg = '0;
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logic [FNS_W-1:0] ts_inc_fns_delay_reg = '0;
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logic [30:0] ts_inc_ns_ovf_reg = '0;
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logic [FNS_W-1:0] ts_inc_fns_ovf_reg = '0;
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logic [47:0] ts_tod_s_reg = '0;
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logic [29:0] ts_tod_ns_reg = '0;
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logic [FNS_W-1:0] ts_tod_fns_reg = '0;
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logic [29:0] ts_tod_ns_inc_reg = '0;
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logic [FNS_W-1:0] ts_tod_fns_inc_reg = '0;
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logic [30:0] ts_tod_ns_ovf_reg = '1;
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logic [FNS_W-1:0] ts_tod_fns_ovf_reg = '1;
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logic [47:0] ts_rel_ns_reg = '0;
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logic [FNS_W-1:0] ts_rel_fns_reg = '0;
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logic ts_tod_step_reg = 1'b0;
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logic ts_rel_step_reg = 1'b0;
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logic [47:0] temp;
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logic pps_reg = 0;
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logic pps_str_reg = 0;
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assign input_adj_active = adj_active_reg;
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if (PIPELINE_OUTPUT > 0) begin
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// pipeline
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(* shreg_extract = "no" *)
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logic [95:0] output_ts_tod_reg[0:PIPELINE_OUTPUT-1];
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(* shreg_extract = "no" *)
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logic output_ts_tod_step_reg[0:PIPELINE_OUTPUT-1];
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(* shreg_extract = "no" *)
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logic [63:0] output_ts_rel_reg[0:PIPELINE_OUTPUT-1];
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(* shreg_extract = "no" *)
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logic output_ts_rel_step_reg[0:PIPELINE_OUTPUT-1];
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(* shreg_extract = "no" *)
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logic output_pps_reg[0:PIPELINE_OUTPUT-1];
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(* shreg_extract = "no" *)
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logic output_pps_str_reg[0:PIPELINE_OUTPUT-1];
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assign output_ts_tod = output_ts_tod_reg[PIPELINE_OUTPUT-1];
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assign output_ts_tod_step = output_ts_tod_step_reg[PIPELINE_OUTPUT-1];
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assign output_ts_rel = output_ts_rel_reg[PIPELINE_OUTPUT-1];
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assign output_ts_rel_step = output_ts_rel_step_reg[PIPELINE_OUTPUT-1];
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assign output_pps = output_pps_reg[PIPELINE_OUTPUT-1];
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assign output_pps_str = output_pps_str_reg[PIPELINE_OUTPUT-1];
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initial begin
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for (integer i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin
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output_ts_tod_reg[i] = '0;
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output_ts_tod_step_reg[i] = 1'b0;
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output_ts_rel_reg[i] = '0;
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output_ts_rel_step_reg[i] = 1'b0;
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output_pps_reg[i] = 1'b0;
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output_pps_str_reg[i] = 1'b0;
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end
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end
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always_ff @(posedge clk) begin
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output_ts_tod_reg[0][95:48] <= ts_tod_s_reg;
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output_ts_tod_reg[0][47:46] <= 2'b00;
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output_ts_tod_reg[0][45:16] <= ts_tod_ns_reg;
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output_ts_tod_reg[0][15:0] <= {ts_tod_fns_reg, 16'd0} >> FNS_W;
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output_ts_tod_step_reg[0] <= ts_tod_step_reg;
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output_ts_rel_reg[0][63:16] <= ts_rel_ns_reg;
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output_ts_rel_reg[0][15:0] <= {ts_rel_fns_reg, 16'd0} >> FNS_W;
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output_ts_rel_step_reg[0] <= ts_rel_step_reg;
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output_pps_reg[0] <= pps_reg;
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output_pps_str_reg[0] <= pps_str_reg;
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for (integer i = 0; i < PIPELINE_OUTPUT-1; i = i + 1) begin
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output_ts_tod_reg[i+1] <= output_ts_tod_reg[i];
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output_ts_tod_step_reg[i+1] <= output_ts_tod_step_reg[i];
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output_ts_rel_reg[i+1] <= output_ts_rel_reg[i];
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output_ts_rel_step_reg[i+1] <= output_ts_rel_step_reg[i];
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output_pps_reg[i+1] <= output_pps_reg[i];
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output_pps_str_reg[i+1] <= output_pps_str_reg[i];
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end
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if (rst) begin
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for (integer i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin
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output_ts_tod_reg[i] <= '0;
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output_ts_tod_step_reg[i] <= 1'b0;
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output_ts_rel_reg[i] <= '0;
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output_ts_rel_step_reg[i] <= 1'b0;
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output_pps_reg[i] <= 1'b0;
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output_pps_str_reg[i] <= 1'b0;
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end
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end
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end
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end else begin
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assign output_ts_tod[95:48] = ts_tod_s_reg;
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assign output_ts_tod[47:46] = 2'b00;
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assign output_ts_tod[45:16] = ts_tod_ns_reg;
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assign output_ts_tod[15:0] = 16'({ts_tod_fns_reg, 16'd0} >> FNS_W);
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assign output_ts_tod_step = ts_tod_step_reg;
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assign output_ts_rel[63:16] = ts_rel_ns_reg;
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assign output_ts_rel[15:0] = 16'({ts_rel_fns_reg, 16'd0} >> FNS_W);
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assign output_ts_rel_step = ts_rel_step_reg;
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assign output_pps = pps_reg;
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assign output_pps_str = pps_str_reg;
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end
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always_ff @(posedge clk) begin
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ts_tod_step_reg <= 1'b0;
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ts_rel_step_reg <= 1'b0;
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drift_apply_reg <= 1'b0;
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pps_reg <= 1'b0;
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// latch parameters
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if (input_period_valid) begin
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period_ns_reg <= input_period_ns;
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period_fns_reg <= input_period_fns;
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end
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if (input_adj_valid) begin
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adj_ns_reg <= input_adj_ns;
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adj_fns_reg <= input_adj_fns;
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adj_count_reg <= input_adj_count;
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end
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if (input_drift_valid) begin
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drift_num_reg <= input_drift_num;
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drift_denom_reg <= input_drift_denom;
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end
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// timestamp increment calculation
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{ts_inc_ns_reg, ts_inc_fns_reg} <= $signed({1'b0, period_ns_reg, period_fns_reg}) +
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(adj_active_reg ? (INC_NS_W+FNS_W)'($signed({adj_ns_reg, adj_fns_reg})) : '0) +
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(drift_apply_reg ? (INC_NS_W+FNS_W)'($signed(drift_num_reg)) : '0);
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// offset adjust counter
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if (adj_count_reg != 0) begin
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adj_count_reg <= adj_count_reg - 1;
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adj_active_reg <= 1;
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ts_tod_step_reg <= 1;
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ts_rel_step_reg <= 1;
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end else begin
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adj_active_reg <= 0;
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end
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// drift counter
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if (drift_cnt_reg != 0) begin
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drift_cnt_reg <= drift_cnt_reg - 1;
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end else begin
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drift_cnt_reg <= drift_denom_reg-1;
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drift_apply_reg <= 1'b1;
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end
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// 96 bit timestamp
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{ts_inc_ns_delay_reg, ts_inc_fns_delay_reg} <= {ts_inc_ns_reg, ts_inc_fns_reg};
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{ts_inc_ns_ovf_reg, ts_inc_fns_ovf_reg} <= {NS_PER_S, {FNS_W{1'b0}}} - (31+FNS_W)'({ts_inc_ns_reg, ts_inc_fns_reg});
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{ts_tod_ns_inc_reg, ts_tod_fns_inc_reg} <= {ts_tod_ns_inc_reg, ts_tod_fns_inc_reg} + (30+FNS_W)'({ts_inc_ns_delay_reg, ts_inc_fns_delay_reg});
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{ts_tod_ns_ovf_reg, ts_tod_fns_ovf_reg} <= {ts_tod_ns_inc_reg, ts_tod_fns_inc_reg} - (31+FNS_W)'({ts_inc_ns_ovf_reg[29:0], ts_inc_fns_ovf_reg});
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{ts_tod_ns_reg, ts_tod_fns_reg} <= {ts_tod_ns_inc_reg, ts_tod_fns_inc_reg};
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if (ts_tod_ns_reg[29]) begin
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pps_str_reg <= 1'b0;
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end
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if (!ts_tod_ns_ovf_reg[30]) begin
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// if the overflow lookahead did not borrow, one second has elapsed
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// increment seconds field, pre-compute normal increment, force overflow lookahead borrow bit set
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{ts_tod_ns_inc_reg, ts_tod_fns_inc_reg} <= (30+FNS_W)'({ts_tod_ns_ovf_reg[29:0], ts_tod_fns_ovf_reg} + {ts_inc_ns_delay_reg, ts_inc_fns_delay_reg});
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ts_tod_ns_ovf_reg[30] <= 1'b1;
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{ts_tod_ns_reg, ts_tod_fns_reg} <= {ts_tod_ns_ovf_reg[29:0], ts_tod_fns_ovf_reg};
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ts_tod_s_reg <= ts_tod_s_reg + 1;
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pps_reg <= 1'b1;
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pps_str_reg <= 1'b1;
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end
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if (input_ts_tod_valid) begin
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// load timestamp
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ts_tod_s_reg <= input_ts_tod[95:48];
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ts_tod_ns_reg <= input_ts_tod[45:16];
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ts_tod_ns_inc_reg <= input_ts_tod[45:16];
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ts_tod_ns_ovf_reg[30] <= 1'b1;
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ts_tod_fns_reg <= FNS_W > 16 ? input_ts_tod[15:0] << (FNS_W-16) : input_ts_tod[15:0] >> (16-FNS_W);
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ts_tod_fns_inc_reg <= FNS_W > 16 ? input_ts_tod[15:0] << (FNS_W-16) : input_ts_tod[15:0] >> (16-FNS_W);
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ts_tod_step_reg <= 1;
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end
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// 64 bit timestamp
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{ts_rel_ns_reg, ts_rel_fns_reg} <= {ts_rel_ns_reg, ts_rel_fns_reg} + (48+FNS_W)'({ts_inc_ns_reg, ts_inc_fns_reg});
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if (input_ts_rel_valid) begin
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// load timestamp
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{ts_rel_ns_reg, ts_rel_fns_reg} <= input_ts_rel;
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ts_rel_step_reg <= 1;
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end
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if (rst) begin
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period_ns_reg <= PERIOD_NS_W'(PERIOD_NS);
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period_fns_reg <= FNS_W'(PERIOD_FNS);
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adj_ns_reg <= '0;
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adj_fns_reg <= '0;
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adj_count_reg <= '0;
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adj_active_reg <= '0;
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drift_num_reg <= FNS_W'(PERIOD_FNS_REM);
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drift_denom_reg <= 16'(PERIOD_NS_DENOM);
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drift_cnt_reg <= '0;
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drift_apply_reg <= 1'b0;
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ts_tod_s_reg <= '0;
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ts_tod_ns_reg <= '0;
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ts_tod_fns_reg <= '0;
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ts_tod_ns_inc_reg <= '0;
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ts_tod_fns_inc_reg <= '0;
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ts_tod_ns_ovf_reg[30] <= 1'b1;
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ts_tod_step_reg <= '0;
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ts_rel_ns_reg <= '0;
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ts_rel_fns_reg <= '0;
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ts_rel_step_reg <= '0;
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pps_reg <= '0;
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pps_str_reg <= '0;
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end
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end
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endmodule
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`resetall
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50
tb/ptp/taxi_ptp_clock/Makefile
Normal file
50
tb/ptp/taxi_ptp_clock/Makefile
Normal file
@@ -0,0 +1,50 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2020-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = taxi_ptp_clock
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = $(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += ../../../rtl/ptp/$(DUT).sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_PERIOD_NS_W := 4
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export PARAM_OFFSET_NS_W := 4
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export PARAM_FNS_W := 16
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export PARAM_PERIOD_NS_NUM := 32
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export PARAM_PERIOD_NS_DENOM := 5
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export PARAM_PIPELINE_OUTPUT := 0
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
401
tb/ptp/taxi_ptp_clock/test_taxi_ptp_clock.py
Normal file
401
tb/ptp/taxi_ptp_clock/test_taxi_ptp_clock.py
Normal file
@@ -0,0 +1,401 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
from decimal import Decimal
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
from cocotb.utils import get_sim_time
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
|
||||
|
||||
dut.input_ts_tod.setimmediatevalue(0)
|
||||
dut.input_ts_tod_valid.setimmediatevalue(0)
|
||||
dut.input_ts_rel.setimmediatevalue(0)
|
||||
dut.input_ts_rel_valid.setimmediatevalue(0)
|
||||
|
||||
dut.input_period_ns.setimmediatevalue(0)
|
||||
dut.input_period_fns.setimmediatevalue(0)
|
||||
dut.input_period_valid.setimmediatevalue(0)
|
||||
|
||||
dut.input_adj_ns.setimmediatevalue(0)
|
||||
dut.input_adj_fns.setimmediatevalue(0)
|
||||
dut.input_adj_count.setimmediatevalue(0)
|
||||
dut.input_adj_valid.setimmediatevalue(0)
|
||||
dut.input_adj_active.setimmediatevalue(0)
|
||||
|
||||
dut.input_drift_num.setimmediatevalue(0)
|
||||
dut.input_drift_denom.setimmediatevalue(0)
|
||||
dut.input_drift_valid.setimmediatevalue(0)
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
def get_output_ts_tod_ns(self):
|
||||
ts = self.dut.output_ts_tod.value.integer
|
||||
return Decimal(ts >> 48).scaleb(9) + (Decimal(ts & 0xffffffffffff) / Decimal(2**16))
|
||||
|
||||
def get_output_ts_tod_s(self):
|
||||
return self.get_output_ts_tod_ns().scaleb(-9)
|
||||
|
||||
def get_output_ts_rel_ns(self):
|
||||
ts = self.dut.output_ts_rel.value.integer
|
||||
return Decimal(ts) / Decimal(2**16)
|
||||
|
||||
def get_output_ts_rel_s(self):
|
||||
return self.get_output_ts_rel_ns().scaleb(-9)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_default_rate(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
start_time = Decimal(get_sim_time('fs')).scaleb(-6)
|
||||
start_ts_tod = tb.get_output_ts_tod_ns()
|
||||
start_ts_rel = tb.get_output_ts_rel_ns()
|
||||
|
||||
for k in range(10000):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
stop_time = Decimal(get_sim_time('fs')).scaleb(-6)
|
||||
stop_ts_tod = tb.get_output_ts_tod_ns()
|
||||
stop_ts_rel = tb.get_output_ts_rel_ns()
|
||||
|
||||
time_delta = stop_time-start_time
|
||||
ts_tod_delta = stop_ts_tod-start_ts_tod
|
||||
ts_rel_delta = stop_ts_rel-start_ts_rel
|
||||
|
||||
tb.log.info("sim time delta : %s ns", time_delta)
|
||||
tb.log.info("ToD ts delta : %s ns", ts_tod_delta)
|
||||
tb.log.info("Rel ts delta : %s ns", ts_rel_delta)
|
||||
|
||||
ts_tod_diff = time_delta - ts_tod_delta
|
||||
ts_rel_diff = time_delta - ts_rel_delta
|
||||
|
||||
tb.log.info("ToD ts diff : %s ns", ts_tod_diff)
|
||||
tb.log.info("Rel ts diff : %s ns", ts_rel_diff)
|
||||
|
||||
assert abs(ts_tod_diff) < 1e-3
|
||||
assert abs(ts_rel_diff) < 1e-3
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_load_timestamps(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
dut.input_ts_tod.value = 12345678
|
||||
dut.input_ts_tod_valid.value = 1
|
||||
dut.input_ts_rel.value = 12345678
|
||||
dut.input_ts_rel_valid.value = 1
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
dut.input_ts_tod_valid.value = 0
|
||||
dut.input_ts_rel_valid.value = 0
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
assert dut.output_ts_tod.value.integer == 12345678
|
||||
assert dut.output_ts_tod_step.value.integer == 1
|
||||
assert dut.output_ts_rel.value.integer == 12345678
|
||||
assert dut.output_ts_rel_step.value.integer == 1
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
start_time = Decimal(get_sim_time('fs')).scaleb(-6)
|
||||
start_ts_tod = tb.get_output_ts_tod_ns()
|
||||
start_ts_rel = tb.get_output_ts_rel_ns()
|
||||
|
||||
for k in range(2000):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
stop_time = Decimal(get_sim_time('fs')).scaleb(-6)
|
||||
stop_ts_tod = tb.get_output_ts_tod_ns()
|
||||
stop_ts_rel = tb.get_output_ts_rel_ns()
|
||||
|
||||
time_delta = stop_time-start_time
|
||||
ts_tod_delta = stop_ts_tod-start_ts_tod
|
||||
ts_rel_delta = stop_ts_rel-start_ts_rel
|
||||
|
||||
tb.log.info("sim time delta : %s ns", time_delta)
|
||||
tb.log.info("ToD ts delta : %s ns", ts_tod_delta)
|
||||
tb.log.info("Rel ts delta : %s ns", ts_rel_delta)
|
||||
|
||||
ts_tod_diff = time_delta - ts_tod_delta
|
||||
ts_rel_diff = time_delta - ts_rel_delta
|
||||
|
||||
tb.log.info("ToD ts diff : %s ns", ts_tod_diff)
|
||||
tb.log.info("Rel ts diff : %s ns", ts_rel_diff)
|
||||
|
||||
assert abs(ts_tod_diff) < 1e-3
|
||||
assert abs(ts_rel_diff) < 1e-3
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_seconds_increment(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
dut.input_ts_tod.value = 999990000 << 16
|
||||
dut.input_ts_tod_valid.value = 1
|
||||
dut.input_ts_rel.value = 999990000 << 16
|
||||
dut.input_ts_rel_valid.value = 1
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
dut.input_ts_tod_valid.value = 0
|
||||
dut.input_ts_rel_valid.value = 0
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
start_time = Decimal(get_sim_time('fs')).scaleb(-6)
|
||||
start_ts_tod = tb.get_output_ts_tod_ns()
|
||||
start_ts_rel = tb.get_output_ts_rel_ns()
|
||||
|
||||
saw_pps = False
|
||||
|
||||
for k in range(3000):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
if dut.output_pps.value.integer:
|
||||
saw_pps = True
|
||||
tb.log.info("Got PPS with sink ToD TS %s", tb.get_output_ts_tod_ns())
|
||||
assert (tb.get_output_ts_tod_s() - 1) < 6.4e-9
|
||||
|
||||
assert saw_pps
|
||||
|
||||
stop_time = Decimal(get_sim_time('fs')).scaleb(-6)
|
||||
stop_ts_tod = tb.get_output_ts_tod_ns()
|
||||
stop_ts_rel = tb.get_output_ts_rel_ns()
|
||||
|
||||
time_delta = stop_time-start_time
|
||||
ts_tod_delta = stop_ts_tod-start_ts_tod
|
||||
ts_rel_delta = stop_ts_rel-start_ts_rel
|
||||
|
||||
tb.log.info("sim time delta : %s ns", time_delta)
|
||||
tb.log.info("ToD ts delta : %s ns", ts_tod_delta)
|
||||
tb.log.info("Rel ts delta : %s ns", ts_rel_delta)
|
||||
|
||||
ts_tod_diff = time_delta - ts_tod_delta
|
||||
ts_rel_diff = time_delta - ts_rel_delta
|
||||
|
||||
tb.log.info("ToD ts diff : %s ns", ts_tod_diff)
|
||||
tb.log.info("Rel ts diff : %s ns", ts_rel_diff)
|
||||
|
||||
assert abs(ts_tod_diff) < 1e-3
|
||||
assert abs(ts_rel_diff) < 1e-3
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_frequency_adjustment(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
dut.input_period_ns.value = 0x6
|
||||
dut.input_period_fns.value = 0x6624
|
||||
dut.input_period_valid.value = 1
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
dut.input_period_valid.value = 0
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
start_time = Decimal(get_sim_time('fs')).scaleb(-6)
|
||||
start_ts_tod = tb.get_output_ts_tod_ns()
|
||||
start_ts_rel = tb.get_output_ts_rel_ns()
|
||||
|
||||
for k in range(10000):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
stop_time = Decimal(get_sim_time('fs')).scaleb(-6)
|
||||
stop_ts_tod = tb.get_output_ts_tod_ns()
|
||||
stop_ts_rel = tb.get_output_ts_rel_ns()
|
||||
|
||||
time_delta = stop_time-start_time
|
||||
ts_tod_delta = stop_ts_tod-start_ts_tod
|
||||
ts_rel_delta = stop_ts_rel-start_ts_rel
|
||||
|
||||
tb.log.info("sim time delta : %s ns", time_delta)
|
||||
tb.log.info("ToD ts delta : %s ns", ts_tod_delta)
|
||||
tb.log.info("Rel ts delta : %s ns", ts_rel_delta)
|
||||
|
||||
ts_tod_diff = time_delta - ts_tod_delta * Decimal(6.4/(6+(0x6624+2/5)/2**16))
|
||||
ts_rel_diff = time_delta - ts_rel_delta * Decimal(6.4/(6+(0x6624+2/5)/2**16))
|
||||
|
||||
tb.log.info("ToD ts diff : %s ns", ts_tod_diff)
|
||||
tb.log.info("Rel ts diff : %s ns", ts_rel_diff)
|
||||
|
||||
assert abs(ts_tod_diff) < 1e-3
|
||||
assert abs(ts_rel_diff) < 1e-3
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_drift_adjustment(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.reset()
|
||||
|
||||
dut.input_drift_num.value = 20
|
||||
dut.input_drift_denom.value = 5
|
||||
dut.input_drift_valid.value = 1
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
dut.input_drift_valid.value = 0
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
start_time = Decimal(get_sim_time('fs')).scaleb(-6)
|
||||
start_ts_tod = tb.get_output_ts_tod_ns()
|
||||
start_ts_rel = tb.get_output_ts_rel_ns()
|
||||
|
||||
for k in range(10000):
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
stop_time = Decimal(get_sim_time('fs')).scaleb(-6)
|
||||
stop_ts_tod = tb.get_output_ts_tod_ns()
|
||||
stop_ts_rel = tb.get_output_ts_rel_ns()
|
||||
|
||||
time_delta = stop_time-start_time
|
||||
ts_tod_delta = stop_ts_tod-start_ts_tod
|
||||
ts_rel_delta = stop_ts_rel-start_ts_rel
|
||||
|
||||
tb.log.info("sim time delta : %s ns", time_delta)
|
||||
tb.log.info("ToD ts delta : %s ns", ts_tod_delta)
|
||||
tb.log.info("Rel ts delta : %s ns", ts_rel_delta)
|
||||
|
||||
ts_tod_diff = time_delta - ts_tod_delta * Decimal(6.4/(6+(0x6666+20/5)/2**16))
|
||||
ts_rel_diff = time_delta - ts_rel_delta * Decimal(6.4/(6+(0x6666+20/5)/2**16))
|
||||
|
||||
tb.log.info("ToD ts diff : %s ns", ts_tod_diff)
|
||||
tb.log.info("Rel ts diff : %s ns", ts_rel_diff)
|
||||
|
||||
assert abs(ts_tod_diff) < 1e-3
|
||||
assert abs(ts_rel_diff) < 1e-3
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_taxi_ptp_clock(request):
|
||||
dut = "taxi_ptp_clock"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, "ptp", f"{dut}.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['PERIOD_NS_W'] = 4
|
||||
parameters['OFFSET_NS_W'] = 4
|
||||
parameters['FNS_W'] = 16
|
||||
parameters['PERIOD_NS_NUM'] = 32
|
||||
parameters['PERIOD_NS_DENOM'] = 5
|
||||
parameters['PIPELINE_OUTPUT'] = 0
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Reference in New Issue
Block a user