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Use string type for string parameters

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-21 19:14:28 -08:00
parent 6154506c0a
commit 6a294cef2c
30 changed files with 60 additions and 60 deletions
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4
example/Arty/fpga/rtl/fpga.sv
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@@ -20,9 +20,9 @@ module fpga #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "artix7"
parameter string FAMILY = "artix7"
)
(
/*

4
example/Arty/fpga/rtl/fpga_core.sv
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@@ -20,9 +20,9 @@ module fpga_core #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "artix7"
parameter string FAMILY = "artix7"
)
(
/*

4
example/HTG940/fpga/rtl/fpga.sv
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@@ -20,9 +20,9 @@ module fpga #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "zynquplus",
parameter string FAMILY = "zynquplus",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b0
)

4
example/HTG940/fpga/rtl/fpga_core.sv
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@@ -20,9 +20,9 @@ module fpga_core #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "zynquplus",
parameter string FAMILY = "zynquplus",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b1
)

4
example/KC705/fpga/rtl/fpga.sv
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@@ -20,9 +20,9 @@ module fpga #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "kintex7",
parameter string FAMILY = "kintex7",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b1,
// BASE-T PHY type (GMII, RGMII, SGMII)

4
example/KC705/fpga/rtl/fpga_core.sv
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@@ -20,9 +20,9 @@ module fpga_core #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "kintex7",
parameter string FAMILY = "kintex7",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b1,
// BASE-T PHY type (GMII, RGMII, SGMII)

4
example/KR260/fpga/rtl/fpga.sv
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@@ -20,9 +20,9 @@ module fpga #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "zynquplus",
parameter string FAMILY = "zynquplus",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b1
)

4
example/KR260/fpga/rtl/fpga_core.sv
View File

@@ -20,9 +20,9 @@ module fpga_core #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "zynquplus",
parameter string FAMILY = "zynquplus",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b1
)