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Use string type for string parameters

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-21 19:14:28 -08:00
parent 6154506c0a
commit 6a294cef2c
30 changed files with 60 additions and 60 deletions
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4
example/Arty/fpga/rtl/fpga.sv
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@@ -20,9 +20,9 @@ module fpga #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "artix7"
parameter string FAMILY = "artix7"
)
(
/*

4
example/Arty/fpga/rtl/fpga_core.sv
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@@ -20,9 +20,9 @@ module fpga_core #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "artix7"
parameter string FAMILY = "artix7"
)
(
/*

4
example/HTG940/fpga/rtl/fpga.sv
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@@ -20,9 +20,9 @@ module fpga #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "zynquplus",
parameter string FAMILY = "zynquplus",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b0
)

4
example/HTG940/fpga/rtl/fpga_core.sv
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@@ -20,9 +20,9 @@ module fpga_core #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "zynquplus",
parameter string FAMILY = "zynquplus",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b1
)

4
example/KC705/fpga/rtl/fpga.sv
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@@ -20,9 +20,9 @@ module fpga #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "kintex7",
parameter string FAMILY = "kintex7",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b1,
// BASE-T PHY type (GMII, RGMII, SGMII)

4
example/KC705/fpga/rtl/fpga_core.sv
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@@ -20,9 +20,9 @@ module fpga_core #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "kintex7",
parameter string FAMILY = "kintex7",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b1,
// BASE-T PHY type (GMII, RGMII, SGMII)

4
example/KR260/fpga/rtl/fpga.sv
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@@ -20,9 +20,9 @@ module fpga #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "zynquplus",
parameter string FAMILY = "zynquplus",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b1
)

4
example/KR260/fpga/rtl/fpga_core.sv
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@@ -20,9 +20,9 @@ module fpga_core #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "zynquplus",
parameter string FAMILY = "zynquplus",
// Use 90 degree clock for RGMII transmit
parameter logic USE_CLK90 = 1'b1
)

4
rtl/eth/taxi_eth_mac_1g_gmii.sv
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@@ -18,8 +18,8 @@ Authors:
module taxi_eth_mac_1g_gmii #
(
parameter logic SIM = 1'b0,
parameter VENDOR = "XILINX",
parameter FAMILY = "virtex7",
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtex7",
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter logic PTP_TS_EN = 1'b0,

4
rtl/eth/taxi_eth_mac_1g_gmii_fifo.sv
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@@ -18,8 +18,8 @@ Authors:
module taxi_eth_mac_1g_gmii_fifo #
(
parameter logic SIM = 1'b0,
parameter VENDOR = "XILINX",
parameter FAMILY = "virtex7",
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtex7",
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter TX_FIFO_DEPTH = 4096,

4
rtl/eth/taxi_eth_mac_1g_rgmii.sv
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@@ -18,8 +18,8 @@ Authors:
module taxi_eth_mac_1g_rgmii #
(
parameter logic SIM = 1'b0,
parameter VENDOR = "XILINX",
parameter FAMILY = "virtex7",
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtex7",
parameter logic USE_CLK90 = 1'b1,
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,

4
rtl/eth/taxi_eth_mac_1g_rgmii_fifo.sv
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@@ -18,8 +18,8 @@ Authors:
module taxi_eth_mac_1g_rgmii_fifo #
(
parameter logic SIM = 1'b0,
parameter VENDOR = "XILINX",
parameter FAMILY = "virtex7",
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtex7",
parameter logic USE_CLK90 = 1'b1,
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,

4
rtl/eth/taxi_eth_mac_mii.sv
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@@ -18,8 +18,8 @@ Authors:
module taxi_eth_mac_mii #
(
parameter logic SIM = 1'b0,
parameter VENDOR = "XILINX",
parameter FAMILY = "virtex7",
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtex7",
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter logic PTP_TS_EN = 1'b0,

4
rtl/eth/taxi_eth_mac_mii_fifo.sv
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@@ -18,8 +18,8 @@ Authors:
module taxi_eth_mac_mii_fifo #
(
parameter logic SIM = 1'b0,
parameter VENDOR = "XILINX",
parameter FAMILY = "virtex7",
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtex7",
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter TX_FIFO_DEPTH = 4096,

4
rtl/io/taxi_iddr.sv
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@@ -20,9 +20,9 @@ module taxi_iddr #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "virtex7",
parameter string FAMILY = "virtex7",
// Width of register in bits
parameter WIDTH = 1
)

4
rtl/io/taxi_oddr.sv
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@@ -20,9 +20,9 @@ module taxi_oddr #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "virtex7",
parameter string FAMILY = "virtex7",
// Width of register in bits
parameter WIDTH = 1
)

4
rtl/io/taxi_ssio_ddr_in.sv
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@@ -20,9 +20,9 @@ module taxi_ssio_ddr_in #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "virtex7",
parameter string FAMILY = "virtex7",
// Width of register in bits
parameter WIDTH = 1
)

4
rtl/io/taxi_ssio_ddr_in_diff.sv
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@@ -20,9 +20,9 @@ module taxi_ssio_ddr_in_diff #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "virtex7",
parameter string FAMILY = "virtex7",
// Width of register in bits
parameter WIDTH = 1
)

4
rtl/io/taxi_ssio_ddr_out.sv
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@@ -20,9 +20,9 @@ module taxi_ssio_ddr_out #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "virtex7",
parameter string FAMILY = "virtex7",
// Use 90 degree clock for transmit
parameter logic USE_CLK90 = 1'b1,
// Width of register in bits

4
rtl/io/taxi_ssio_ddr_out_diff.sv
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@@ -20,9 +20,9 @@ module taxi_ssio_ddr_out_diff #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "virtex7",
parameter string FAMILY = "virtex7",
// Use 90 degree clock for transmit
parameter logic USE_CLK90 = 1'b1,
// Width of register in bits

4
rtl/io/taxi_ssio_sdr_in.sv
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@@ -20,9 +20,9 @@ module taxi_ssio_sdr_in #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "virtex7",
parameter string FAMILY = "virtex7",
// Width of register in bits
parameter WIDTH = 1
)

4
rtl/io/taxi_ssio_sdr_in_diff.sv
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@@ -20,9 +20,9 @@ module ssio_sdr_in_diff #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "virtex7",
parameter string FAMILY = "virtex7",
// Width of register in bits
parameter WIDTH = 1
)

4
rtl/io/taxi_ssio_sdr_out.sv
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@@ -20,9 +20,9 @@ module taxi_ssio_sdr_out #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "virtex7",
parameter string FAMILY = "virtex7",
// Width of register in bits
parameter WIDTH = 1
)

4
rtl/io/taxi_ssio_sdr_out_diff.sv
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@@ -20,9 +20,9 @@ module taxi_ssio_sdr_out_diff #
// simulation (set to avoid vendor primitives)
parameter logic SIM = 1'b0,
// vendor ("GENERIC", "XILINX", "ALTERA")
parameter VENDOR = "XILINX",
parameter string VENDOR = "XILINX",
// device family
parameter FAMILY = "virtex7",
parameter string FAMILY = "virtex7",
// Width of register in bits
parameter WIDTH = 1
)

4
tb/eth/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv
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@@ -19,8 +19,8 @@ module test_taxi_eth_mac_1g_gmii #
(
/* verilator lint_off WIDTHTRUNC */
parameter logic SIM = 1'b1,
parameter VENDOR = "XILINX",
parameter FAMILY = "virtex7",
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtex7",
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter logic PTP_TS_EN = 1'b0,

4
tb/eth/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv
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@@ -19,8 +19,8 @@ module test_taxi_eth_mac_1g_gmii_fifo #
(
/* verilator lint_off WIDTHTRUNC */
parameter logic SIM = 1'b1,
parameter VENDOR = "XILINX",
parameter FAMILY = "virtex7",
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtex7",
parameter AXIS_DATA_W = 8,
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,

4
tb/eth/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv
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@@ -19,8 +19,8 @@ module test_taxi_eth_mac_1g_rgmii #
(
/* verilator lint_off WIDTHTRUNC */
parameter logic SIM = 1'b1,
parameter VENDOR = "XILINX",
parameter FAMILY = "virtex7",
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtex7",
parameter logic USE_CLK90 = 1'b1,
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,

4
tb/eth/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv
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@@ -19,8 +19,8 @@ module test_taxi_eth_mac_1g_rgmii_fifo #
(
/* verilator lint_off WIDTHTRUNC */
parameter logic SIM = 1'b1,
parameter VENDOR = "XILINX",
parameter FAMILY = "virtex7",
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtex7",
parameter logic USE_CLK90 = 1'b1,
parameter AXIS_DATA_W = 8,
parameter logic PADDING_EN = 1'b1,

4
tb/eth/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv
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@@ -19,8 +19,8 @@ module test_taxi_eth_mac_mii #
(
/* verilator lint_off WIDTHTRUNC */
parameter logic SIM = 1'b1,
parameter VENDOR = "XILINX",
parameter FAMILY = "virtex7",
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtex7",
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
parameter logic PTP_TS_EN = 1'b0,

4
tb/eth/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv
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@@ -19,8 +19,8 @@ module test_taxi_eth_mac_mii_fifo #
(
/* verilator lint_off WIDTHTRUNC */
parameter logic SIM = 1'b1,
parameter VENDOR = "XILINX",
parameter FAMILY = "virtex7",
parameter string VENDOR = "XILINX",
parameter string FAMILY = "virtex7",
parameter AXIS_DATA_W = 8,
parameter logic PADDING_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,