axis: Add COBS decoder module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>

rtl/axis/taxi_axis_cobs_decode.sv

@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2016-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream consistent overhead byte stuffing (COBS) decoder
+ */
+module taxi_axis_cobs_decode
+(
+    input  wire logic  clk,
+    input  wire logic  rst,
+
+    /*
+     * AXI4-Stream input (sink)
+     */
+    taxi_axis_if.snk   s_axis,
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    taxi_axis_if.src   m_axis
+);
+
+// check configuration
+if (m_axis.DATA_W != 8 || s_axis.DATA_W != 8)
+    $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
+
+// state register
+localparam [1:0]
+    STATE_IDLE = 2'd0,
+    STATE_SEGMENT = 2'd1,
+    STATE_NEXT_SEGMENT = 2'd2;
+
+logic [1:0] state_reg = STATE_IDLE, state_next;
+
+logic [7:0] count_reg = 8'd0, count_next;
+logic suppress_zero_reg = 1'b0, suppress_zero_next;
+
+logic [7:0] temp_tdata_reg = 8'd0, temp_tdata_next;
+logic temp_tvalid_reg = 1'b0, temp_tvalid_next;
+
+// internal datapath
+logic [7:0] m_axis_tdata_int;
+logic       m_axis_tvalid_int;
+logic       m_axis_tready_int_reg = 1'b0;
+logic       m_axis_tlast_int;
+logic       m_axis_tuser_int;
+wire        m_axis_tready_int_early;
+
+logic s_axis_tready_reg = 1'b0, s_axis_tready_next;
+
+assign s_axis.tready = s_axis_tready_reg;
+
+always_comb begin
+    state_next = STATE_IDLE;
+
+    count_next = count_reg;
+    suppress_zero_next = suppress_zero_reg;
+
+    temp_tdata_next = temp_tdata_reg;
+    temp_tvalid_next = temp_tvalid_reg;
+
+    m_axis_tdata_int = 8'd0;
+    m_axis_tvalid_int = 1'b0;
+    m_axis_tlast_int = 1'b0;
+    m_axis_tuser_int = 1'b0;
+
+    s_axis_tready_next = 1'b0;
+
+    case (state_reg)
+        STATE_IDLE: begin
+            // idle state
+            s_axis_tready_next = m_axis_tready_int_early || !temp_tvalid_reg;
+
+            // output final word
+            m_axis_tdata_int = temp_tdata_reg;
+            m_axis_tvalid_int = temp_tvalid_reg;
+            m_axis_tlast_int = temp_tvalid_reg;
+            temp_tvalid_next = temp_tvalid_reg && !m_axis_tready_int_reg;
+
+            if (s_axis.tready && s_axis.tvalid) begin
+                // valid input data
+                // skip any leading zeros
+                if (s_axis.tdata != 8'd0) begin
+                    // store count value and zero suppress
+                    count_next = s_axis.tdata-1;
+                    suppress_zero_next = (s_axis.tdata == 8'd255);
+                    s_axis_tready_next = m_axis_tready_int_early;
+                    if (s_axis.tdata == 8'd1) begin
+                        // next byte will be count value
+                        state_next = STATE_NEXT_SEGMENT;
+                    end else begin
+                        // next byte will be data
+                        state_next = STATE_SEGMENT;
+                    end
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_SEGMENT: begin
+            // receive segment
+            s_axis_tready_next = m_axis_tready_int_early;
+
+            if (s_axis.tready && s_axis.tvalid) begin
+                // valid input data
+                // store in temp register
+                temp_tdata_next = s_axis.tdata;
+                temp_tvalid_next = 1'b1;
+                // move temp to output
+                m_axis_tdata_int = temp_tdata_reg;
+                m_axis_tvalid_int = temp_tvalid_reg;
+                // decrement count
+                count_next = count_reg - 1;
+                if (s_axis.tdata == 8'd0) begin
+                    // got a zero byte in a frame - mark it as an error and re-sync
+                    temp_tvalid_next = 1'b0;
+                    m_axis_tvalid_int = 1'b1;
+                    m_axis_tuser_int = 1'b1;
+                    m_axis_tlast_int = 1'b1;
+                    s_axis_tready_next = 1'b1;
+                    state_next = STATE_IDLE;
+                end else if (s_axis.LAST_EN && s_axis.tlast) begin
+                    // end of frame
+                    if (count_reg == 8'd1 && (!s_axis.USER_EN || !s_axis.tuser)) begin
+                        // end of frame indication at correct time, go to idle to output final byte
+                        state_next = STATE_IDLE;
+                    end else begin
+                        // end of frame indication at invalid time or tuser assert, so mark as an error and re-sync
+                        temp_tvalid_next = 1'b0;
+                        m_axis_tvalid_int = 1'b1;
+                        m_axis_tuser_int = 1'b1;
+                        m_axis_tlast_int = 1'b1;
+                        s_axis_tready_next = 1'b1;
+                        state_next = STATE_IDLE;
+                    end
+                end else if (count_reg == 8'd1) begin
+                    // next byte will be count value
+                    state_next = STATE_NEXT_SEGMENT;
+                end else begin
+                    // next byte will be data
+                    state_next = STATE_SEGMENT;
+                end
+            end else begin
+                state_next = STATE_SEGMENT;
+            end
+        end
+        STATE_NEXT_SEGMENT: begin
+            // next segment
+            s_axis_tready_next = m_axis_tready_int_early;
+
+            if (s_axis.tready && s_axis.tvalid) begin
+                // valid input data
+                // store zero in temp if not suppressed
+                temp_tdata_next = 8'd0;
+                temp_tvalid_next = !suppress_zero_reg;
+                // move temp to output
+                m_axis_tdata_int = temp_tdata_reg;
+                m_axis_tvalid_int = temp_tvalid_reg;
+                if (s_axis.tdata == 8'd0) begin
+                    // got a zero byte delineating the end of the frame, so mark as such and re-sync
+                    temp_tvalid_next = 1'b0;
+                    m_axis_tuser_int = s_axis.tuser;
+                    m_axis_tlast_int = 1'b1;
+                    s_axis_tready_next = 1'b1;
+                    state_next = STATE_IDLE;
+                end else if (s_axis.LAST_EN && s_axis.tlast) begin
+                    if (s_axis.tdata == 8'd1 && (!s_axis.USER_EN || !s_axis.tuser)) begin
+                        // end of frame indication at correct time, go to idle to output final byte
+                        state_next = STATE_IDLE;
+                    end else begin
+                        // end of frame indication at invalid time or tuser assert, so mark as an error and re-sync
+                        temp_tvalid_next = 1'b0;
+                        m_axis_tvalid_int = 1'b1;
+                        m_axis_tuser_int = 1'b1;
+                        m_axis_tlast_int = 1'b1;
+                        s_axis_tready_next = 1'b1;
+                        state_next = STATE_IDLE;
+                    end
+                end else begin
+                    // otherwise, store count value and zero suppress
+                    count_next = s_axis.tdata-1;
+                    suppress_zero_next = (s_axis.tdata == 8'd255);
+                    s_axis_tready_next = m_axis_tready_int_early;
+                    if (s_axis.tdata == 8'd1) begin
+                        // next byte will be count value
+                        state_next = STATE_NEXT_SEGMENT;
+                    end else begin
+                        // next byte will be data
+                        state_next = STATE_SEGMENT;
+                    end
+                end
+            end else begin
+                state_next = STATE_NEXT_SEGMENT;
+            end
+        end
+        default: begin
+            // invalid state
+            state_next = STATE_IDLE;
+        end
+    endcase
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    count_reg <= count_next;
+    suppress_zero_reg <= suppress_zero_next;
+
+    temp_tdata_reg <= temp_tdata_next;
+    temp_tvalid_reg <= temp_tvalid_next;
+
+    s_axis_tready_reg <= s_axis_tready_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        temp_tvalid_reg <= 1'b0;
+        s_axis_tready_reg <= 1'b0;
+    end
+end
+
+// output datapath logic
+logic [7:0] m_axis_tdata_reg = 8'd0;
+logic       m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
+logic       m_axis_tlast_reg = 1'b0;
+logic       m_axis_tuser_reg = 1'b0;
+
+logic [7:0] temp_m_axis_tdata_reg = 8'd0;
+logic       temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
+logic       temp_m_axis_tlast_reg = 1'b0;
+logic       temp_m_axis_tuser_reg = 1'b0;
+
+// datapath control
+logic store_axis_int_to_output;
+logic store_axis_int_to_temp;
+logic store_axis_temp_to_output;
+
+assign m_axis.tdata = m_axis_tdata_reg;
+assign m_axis.tkeep = 1'b1;
+assign m_axis.tstrb = m_axis.tkeep;
+assign m_axis.tvalid = m_axis_tvalid_reg;
+assign m_axis.tlast = m_axis_tlast_reg;
+assign m_axis.tid = '0;
+assign m_axis.tdest = '0;
+assign m_axis.tuser = m_axis_tuser_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+assign m_axis_tready_int_early = m_axis.tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+
+always_comb begin
+    // transfer sink ready state to source
+    m_axis_tvalid_next = m_axis_tvalid_reg;
+    temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
+
+    store_axis_int_to_output = 1'b0;
+    store_axis_int_to_temp = 1'b0;
+    store_axis_temp_to_output = 1'b0;
+
+    if (m_axis_tready_int_reg) begin
+        // input is ready
+        if (m_axis.tready || !m_axis_tvalid_reg) begin
+            // output is ready or currently not valid, transfer data to output
+            m_axis_tvalid_next = m_axis_tvalid_int;
+            store_axis_int_to_output = 1'b1;
+        end else begin
+            // output is not ready, store input in temp
+            temp_m_axis_tvalid_next = m_axis_tvalid_int;
+            store_axis_int_to_temp = 1'b1;
+        end
+    end else if (m_axis.tready) begin
+        // input is not ready, but output is ready
+        m_axis_tvalid_next = temp_m_axis_tvalid_reg;
+        temp_m_axis_tvalid_next = 1'b0;
+        store_axis_temp_to_output = 1'b1;
+    end
+end
+
+always_ff @(posedge clk) begin
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
+
+    // datapath
+    if (store_axis_int_to_output) begin
+        m_axis_tdata_reg <= m_axis_tdata_int;
+        m_axis_tlast_reg <= m_axis_tlast_int;
+        m_axis_tuser_reg <= m_axis_tuser_int;
+    end else if (store_axis_temp_to_output) begin
+        m_axis_tdata_reg <= temp_m_axis_tdata_reg;
+        m_axis_tlast_reg <= temp_m_axis_tlast_reg;
+        m_axis_tuser_reg <= temp_m_axis_tuser_reg;
+    end
+
+    if (store_axis_int_to_temp) begin
+        temp_m_axis_tdata_reg <= m_axis_tdata_int;
+        temp_m_axis_tlast_reg <= m_axis_tlast_int;
+        temp_m_axis_tuser_reg <= m_axis_tuser_int;
+    end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
+end
+
+endmodule
+
+`resetall

tb/axis/taxi_axis_cobs_decode/Makefile

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2021-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = taxi_axis_cobs_decode
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += ../../../rtl/axis/$(DUT).sv
+VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+#export PARAM_APPEND_ZERO := 0
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

tb/axis/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.py

@@ -0,0 +1,241 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
+
+
+def cobs_encode(block):
+    block = bytearray(block)
+    enc = bytearray()
+
+    seg = bytearray()
+    code = 1
+
+    new_data = True
+
+    for b in block:
+        if b == 0:
+            enc.append(code)
+            enc.extend(seg)
+            code = 1
+            seg = bytearray()
+            new_data = True
+        else:
+            code += 1
+            seg.append(b)
+            new_data = True
+            if code == 255:
+                enc.append(code)
+                enc.extend(seg)
+                code = 1
+                seg = bytearray()
+                new_data = False
+
+    if new_data:
+        enc.append(code)
+        enc.extend(seg)
+
+    return bytes(enc)
+
+
+def cobs_decode(block):
+    block = bytearray(block)
+    dec = bytearray()
+
+    code = 0
+
+    i = 0
+
+    if 0 in block:
+        return None
+
+    while i < len(block):
+        code = block[i]
+        i += 1
+        if i+code-1 > len(block):
+            return None
+        dec.extend(block[i:i+code-1])
+        i += code-1
+        if code < 255 and i < len(block):
+            dec.append(0)
+
+    return bytes(dec)
+
+
+def prbs31(state=0x7fffffff):
+    while True:
+        for i in range(8):
+            if bool(state & 0x08000000) ^ bool(state & 0x40000000):
+                state = ((state & 0x3fffffff) << 1) | 1
+            else:
+                state = (state & 0x3fffffff) << 1
+        yield state & 0xff
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.clk, dut.rst)
+        self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.clk, dut.rst)
+
+    def set_idle_generator(self, generator=None):
+        if generator:
+            self.source.set_pause_generator(generator())
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            self.sink.set_pause_generator(generator())
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.set_idle_generator(idle_inserter)
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+
+    for test_data in test_frames:
+        enc = cobs_encode(test_data)
+        test_frame = AxiStreamFrame(enc)
+        await tb.source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+
+        assert rx_frame.tdata == test_data
+        assert not rx_frame.tuser
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+def size_list():
+    return list(range(1, 33))+list(range(253, 259))+[512]+[1]*64
+
+
+def zero_payload(length):
+    return bytearray(length)
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def nonzero_incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(1, 256)), length))
+
+
+def nonzero_incrementing_payload_zero_framed(length):
+    return bytearray([0]+list(itertools.islice(itertools.cycle(range(1, 256)), length))+[0])
+
+
+def prbs_payload(length):
+    gen = prbs31()
+    return bytearray([next(gen) for x in range(length)])
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [zero_payload, nonzero_incrementing_payload, nonzero_incrementing_payload_zero_framed, prbs_payload])
+    factory.add_option("idle_inserter", [None, cycle_pause])
+    factory.add_option("backpressure_inserter", [None, cycle_pause])
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.dirname(__file__)
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_axis_cobs_decode(request):
+    dut = "taxi_axis_cobs_decode"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, "axis", f"{dut}.sv"),
+        os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

tb/axis/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.sv

@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream COBS decoder testbench
+ */
+module test_taxi_axis_cobs_decode();
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(
+    .DATA_W(8),
+    .LAST_EN(1),
+    .USER_EN(1),
+    .USER_W(1)
+) s_axis(), m_axis();
+
+taxi_axis_cobs_decode
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI4-Stream input (sink)
+     */
+    .s_axis(s_axis),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis(m_axis)
+);
+
+endmodule
+
+`resetall