Alex Forencich
|
2bb2710bbd
|
pcie: Add IRQ rate limit module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-03-08 17:38:04 -07:00 |
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Alex Forencich
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3ac7484e16
|
pcie: Clean up array init
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2026-03-08 14:42:31 -07:00 |
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Alex Forencich
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6cf03d6435
|
pcie: Use SV enums in PCIe logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-02-27 15:55:34 -08:00 |
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Alex Forencich
|
8d7cdaa689
|
pcie: Fix parametrization issues in MSI-X modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-02-27 10:42:07 -08:00 |
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Alex Forencich
|
a39c62f85a
|
pcie: Add MSI-X module with APB interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-02-27 00:06:42 -08:00 |
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Alex Forencich
|
896dff2fd1
|
pcie: Add MSI-X module with AXI lite interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-02-27 00:06:20 -08:00 |
|
Alex Forencich
|
5545602a26
|
pcie: Fix width cast
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-02-24 14:26:42 -08:00 |
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Alex Forencich
|
5d3aff95cc
|
pcie: Add VSEC AXIL register access extended capability implementation for UltraScale
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-02-24 12:20:02 -08:00 |
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Alex Forencich
|
7bb3f18fa3
|
pcie: Add VSEC APB register access extended capability implementation for UltraScale
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-02-24 12:19:54 -08:00 |
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Alex Forencich
|
be80d4e964
|
pcie: Tie off AXIL user signals in PCIe AXI lite master module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-02-21 02:48:18 -08:00 |
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Alex Forencich
|
9b55a08465
|
pcie: Cast widths in VPD implementation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-02-20 22:14:01 -08:00 |
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Alex Forencich
|
9630afce1d
|
pcie: Add VPD capability implementation for UltraScale+
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-02-16 13:37:35 -08:00 |
|
Alex Forencich
|
ddac834e99
|
pcie: Add configuration shim for UltraScale
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-02-05 14:35:01 -08:00 |
|
Alex Forencich
|
245e71551b
|
pcie: Add MSI shim for UltraScale
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-12-23 18:03:56 -08:00 |
|
Alex Forencich
|
004246608e
|
Use logic instead of reg
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-11-07 02:14:19 -08:00 |
|
Alex Forencich
|
9307e0df6c
|
pcie: Clean up casts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 15:17:46 -07:00 |
|
Alex Forencich
|
40908b1b92
|
Testbench cleanup for cocotb 2.0
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-07 10:59:38 -07:00 |
|
Alex Forencich
|
2ae5b5fae3
|
pcie: Remove TLP_HDR_W parameter from testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-09-01 22:08:18 -07:00 |
|
Alex Forencich
|
bf584147a1
|
pcie: Clean up AXI lite interface width handling in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-29 17:59:56 -07:00 |
|
Alex Forencich
|
b3441f6408
|
pcie: Rename enable to en in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-29 17:59:33 -07:00 |
|
Alex Forencich
|
63c961cab4
|
pcie: Fix some corner cases in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-29 16:50:31 -07:00 |
|
Alex Forencich
|
b5c9c02b03
|
pcie: Add UltraScale PCIe AXI Lite Master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-08-25 22:39:28 -07:00 |
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Alex Forencich
|
66b53d98a2
|
Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-05-18 12:25:59 -07:00 |
|