bslathi19/wireguard_fpga
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Byron Lathi 9f8654f03c Fix bug where parser data was not resetting at the start of packet
2026-08-13 19:50:27 -07:00
docs/core
Start work on parser
2026-08-13 08:35:49 -07:00
sim
Fix bug where parser data was not resetting at the start of packet
2026-08-13 19:50:27 -07:00
src
Fix bug where parser data was not resetting at the start of packet
2026-08-13 19:50:27 -07:00
Ti375C529_devkit
Start work on parser
2026-08-13 08:35:49 -07:00
.gitignore
Start work on parser
2026-08-13 08:35:49 -07:00
.gitmodules
commit
2026-08-08 21:41:43 -07:00
init_env.sh
commit
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LICENSE
Initial commit
2026-01-17 22:39:04 -08:00
README.md
Initial commit
2026-01-17 22:39:04 -08:00
requirements.txt
Add upstream ip check
2026-01-18 01:32:40 -08:00

README.md

wireguard_fpga

FPGA for wireguard

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Description
FPGA for wireguard
Readme GPL-3.0 3.9 MiB
Languages
C 60.1%
Verilog 32.4%
SystemVerilog 6.1%
VHDL 0.6%
Tcl 0.4%
Other 0.2%