Alex Mykyta
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e788e7cafd
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Remove excessive secondary counter saturation clamping logic. Counters will now be allowed to be set to values beyond their saturation point if loaded through non-increment/decrement mechanism. #114
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2024-12-19 21:41:20 -08:00 |
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Alex Mykyta
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a15178c719
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Use clog2 helper function to improve clarity. #116
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2024-12-19 19:47:41 -08:00 |
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Alex Mykyta
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80a46a082b
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Fix incorrect address width calculation for external blocks. #116
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2024-12-19 19:40:57 -08:00 |
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Alex Mykyta
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5f9d7308c2
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Add next_q storage element to reset clause to avoid synthesis issues with async resets. #113
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2024-12-19 19:30:30 -08:00 |
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Alex Mykyta
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ebd82dde1b
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Add peakrdl-cli optional dependency
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2024-12-19 19:04:48 -08:00 |
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Alex Mykyta
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809195a72a
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install mising test package
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2024-12-18 22:21:35 -08:00 |
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Alex Mykyta
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1d7d47f49c
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More type hint workarounds
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2024-12-18 22:20:35 -08:00 |
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Alex Mykyta
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5c1bc35799
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Type hint workarounds
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2024-12-18 22:13:51 -08:00 |
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Alex Mykyta
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e0295ae526
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Fixup test bitswap. mypy
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2024-12-18 22:04:12 -08:00 |
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Alex Mykyta
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11d9f65dff
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Fix incorrect bit-order in packed struct output of external registers. #111
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2024-12-18 21:17:31 -08:00 |
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Alex Mykyta
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399f942201
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Fix doc typos
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2024-12-18 20:29:17 -08:00 |
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Alex Mykyta
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faa57c93b9
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Add preprocessor ifndef around RTL assertions to allow exclusion. #104
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2024-12-17 22:31:30 -08:00 |
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Alex Mykyta
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ceb1f9b0c1
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Add contributing guidelines, issue templates, and PR template
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2024-05-04 18:04:52 -07:00 |
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Alex Mykyta
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a076609dad
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version
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2024-03-31 22:21:54 -07:00 |
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Alex Mykyta
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4dfd9b10d6
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Add support for CPUIFs to have parameters #80
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2024-03-29 22:39:45 -07:00 |
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Alex Mykyta
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f25ba60bfc
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Add packed struct overlay for external register bitfields. #84
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2024-03-29 22:16:24 -07:00 |
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Alex Mykyta
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840b54c6e1
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Use explicit logic type for user enum declarations. #91
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2024-03-29 21:22:34 -07:00 |
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Alex Mykyta
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653d4efc73
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version
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2024-03-20 20:02:40 -07:00 |
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Alex Mykyta
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555efdfcc0
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Remove use of in-scope initial assignments to automatics to work around bug in Spyglass lint tool. #87
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2024-03-20 19:57:50 -07:00 |
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Aylon Chaim Porat
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cf2be63c20
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read_buffering & write_buffering: get_trigger's accesswidth and regwidth should be taken from trigger when trigger is of RegNode type, not from node
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2024-03-20 19:15:33 -07:00 |
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motchy
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be8d84bba0
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fix: a typo in SV template
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2024-03-10 11:46:28 -07:00 |
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Alex Mykyta
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0d39774d22
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Fixup whitespace
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2024-01-05 21:12:25 -08:00 |
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Alex Mykyta
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6a550abc69
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Fix accidental blocking assignment in always_ff for read buffering storage elements
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2024-01-05 19:57:47 -08:00 |
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Alex Mykyta
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6433cd1fc8
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Fix typo in pyproject keywords
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2023-11-07 20:57:49 -08:00 |
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Alex Mykyta
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45999555cf
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Update to use trusted deploy
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2023-10-28 21:25:58 -07:00 |
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Alex Mykyta
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2fedef64aa
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Add validation check for write buffered registers that trigger off of their own field. #39
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2023-10-25 21:54:01 -07:00 |
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Alex Mykyta
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f2cb2425b3
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Migrate to pyproject.toml
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2023-10-24 23:03:39 -07:00 |
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Alex Mykyta
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62518b318b
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Implement new SVInt object to defer literal expansion and allow bit-fiddling operations. Fix invalid bit-slicing of literals if field reset value is a constant. #71
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2023-10-24 22:50:41 -07:00 |
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Alex Mykyta
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b5b1ba790e
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Simulator compatibility updates
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2023-10-22 20:43:34 -07:00 |
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Alex Mykyta
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d689bb7077
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Reorganize how tb infrstructure selects toolchains
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2023-10-22 11:04:43 -07:00 |
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Alex Mykyta
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683fc4d0ac
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Update version
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2023-10-11 22:04:34 -07:00 |
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Alex Mykyta
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1488b2c0ff
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Add missing doc req
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2023-10-11 22:00:22 -07:00 |
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Alex Mykyta
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0da6efe85c
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Fix hwif type name generation to properly handle parameterized component names. #70
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2023-10-11 21:58:10 -07:00 |
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Alex Mykyta
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c0e341579c
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fix typo
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2023-09-29 05:55:54 -07:00 |
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Alex Mykyta
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4fad6546fd
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docs yaml
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2023-09-28 23:21:11 -07:00 |
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Alex Mykyta
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333853b925
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Fix axi4-lite write strobe width. #68
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2023-09-28 21:18:11 -07:00 |
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Alex Mykyta
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639cafc28b
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Fix always_ff generation for non-reset fields and async default reset. #63
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2023-09-07 23:36:47 -07:00 |
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Alex Mykyta
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7bb6c0c41a
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Fix xsim compatibility quirk
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2023-09-07 23:16:58 -07:00 |
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Alex Mykyta
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ad7b09a2f5
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Remove implication operator to avoid xsim compatibility limitation. #57
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2023-09-07 22:42:42 -07:00 |
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Alex Mykyta
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49db496ac1
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Add parameters for data and addr width to package output
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2023-08-24 20:44:16 -07:00 |
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Alex Mykyta
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280c3aad17
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Discard LSbs of address for AXI4-Lite CPUIF to properly handle unaligned transfers. #60
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2023-08-24 20:36:28 -07:00 |
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Alex Mykyta
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eef8f7cdb4
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Doc updates
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2023-08-03 22:53:22 -07:00 |
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Alex Mykyta
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5c3dd6e6bb
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More test coverage
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2023-08-03 22:18:55 -07:00 |
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Alex Mykyta
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f9e0d1babc
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Coverage improvements
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2023-08-02 22:28:42 -07:00 |
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Alex Mykyta
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941871007b
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Omit unecessary hwif signals if an external register is read-only or write-only. #58
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2023-08-02 21:38:06 -07:00 |
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Alex Mykyta
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8a6f525ee2
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Add assertion for rogue external ack strobes. Clarify recommended external ack tieoff. #57
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2023-08-01 20:40:14 -07:00 |
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Alex Mykyta
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45eb47cdb1
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Add changelog
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2023-07-19 21:09:20 -07:00 |
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Alex Mykyta
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f884b91852
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version
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2023-07-19 21:02:10 -07:00 |
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Alex Mykyta
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211224116e
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Clean up ugly unconditional 'if(1)' conditionals in field logic. #50
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2023-07-19 20:49:38 -07:00 |
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Alex Mykyta
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da8ff4aaeb
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Make remaining interrupt conditional predicates single-bit. #54
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2023-07-19 20:17:46 -07:00 |
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