Add more register printout

requirements.txt

@@ -7,4 +7,5 @@ rtl-manifest
 build_fpga
 fpga-sim
 peakrdl
-
+peakrdl-python-regmap
+git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@taxi_apb

sim/alibaba_pcie.py

@@ -10,6 +10,8 @@ from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
 
 from baser import BaseRSerdesSource, BaseRSerdesSink
 
+from alibaba_pcie_top_regs import alibaba_pcie_top_regsClass
+
 CLK_PERIOD = 4
 
 class TB:
@@ -76,14 +78,14 @@ class TB:
             pf3_msix_pba_offset=0x00000000,
 
             # signals
-            user_clk=dut.clk_250,
+            user_clk=dut.u_pcie_top.clk_250,
-            user_reset=dut.rst_250,
+            user_reset=dut.u_pcie_top.rst_250,
-            user_lnk_up=dut.user_lnk_up,
+            user_lnk_up=dut.u_pcie_top.user_lnk_up,
 
-            rq_bus=AxiStreamBus.from_entity(dut.s_axis_rq),
+            rq_bus=AxiStreamBus.from_entity(dut.u_pcie_top.s_axis_rq),
-            rc_bus=AxiStreamBus.from_entity(dut.m_axis_rc),
+            rc_bus=AxiStreamBus.from_entity(dut.u_pcie_top.m_axis_rc),
-            cq_bus=AxiStreamBus.from_entity(dut.m_axis_cq),
+            cq_bus=AxiStreamBus.from_entity(dut.u_pcie_top.m_axis_cq),
-            cc_bus=AxiStreamBus.from_entity(dut.s_axis_cc),
+            cc_bus=AxiStreamBus.from_entity(dut.u_pcie_top.s_axis_cc),
         )
 
         self.dev.functions[0].configure_bar(0, 64*1024)
@@ -142,31 +144,40 @@ async def test_sanity(dut):
 
     dev_bar0 = dev.bar_window[0]
 
-    tb.log.info(dev_bar0.write)
-
     message = b"Hello, world! This is a long string of data with many letters and words."
 
     await mem.write(0, message)
 
-    await dev_bar0.write_dword(0x0, 0x00000000)
+    regmap = alibaba_pcie_top_regsClass()
-    await dev_bar0.write_dword(0x4, 0x00000000)
+    pcie_dma_rd = regmap.pcie_top_regs.pcie_dma_regs.dma_rd
-    await dev_bar0.write_dword(0x8, 0x00000000)
+    pcie_dma_wr = regmap.pcie_top_regs.pcie_dma_regs.dma_wr
-    await dev_bar0.write_dword(0xc, len(message))
+
-    await dev_bar0.write_dword(0x10, 0x00000001)
+    eth_dma_rd = regmap.eth_dma_wrapper_regs.pcie_dma_regs.dma_rd
+    eth_dma_wr = regmap.eth_dma_wrapper_regs.pcie_dma_regs.dma_wr
+
+
+    # DMA from host to dma memory
+    await dev_bar0.write_dword(pcie_dma_rd.src_addr_low.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_rd.src_addr_high.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_rd.dst_addr.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_rd.length.addr, len(message))
+    await dev_bar0.write_dword(pcie_dma_rd.trigger.addr, 0x00000001)
 
     await Timer(1, "us")
 
-    await dev_bar0.write_dword(0x40, 0x00000000)
+    # Set up stream to memory DMA to store ethernet frame
-    await dev_bar0.write_dword(0x44, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_wr.src_addr.addr, 0x00000000)
-    await dev_bar0.write_dword(0x48, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_wr.dst_addr_low.addr, 0x00000000)
-    await dev_bar0.write_dword(0x4c, len(message))
+    await dev_bar0.write_dword(eth_dma_wr.dst_addr_high.addr, 0x00000000)
-    await dev_bar0.write_dword(0x50, 0x00000001)
+    await dev_bar0.write_dword(eth_dma_wr.length.addr, len(message))
+    await dev_bar0.write_dword(eth_dma_wr.trigger.addr, 0x00000001)
 
-    await dev_bar0.write_dword(0x60, 0x00000000)
+    # Trigger memory to stream dma to send ethernet frame
-    await dev_bar0.write_dword(0x64, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_rd.src_addr_low.addr, 0x00000000)
-    await dev_bar0.write_dword(0x68, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_rd.src_addr_high.addr, 0x00000000)
-    await dev_bar0.write_dword(0x6c, len(message))
+    await dev_bar0.write_dword(eth_dma_rd.dst_addr.addr, 0x00000000)
-    await dev_bar0.write_dword(0x70, 0x00000001)
+    await dev_bar0.write_dword(eth_dma_rd.length.addr, len(message))
+    await dev_bar0.write_dword(eth_dma_rd.trigger.addr, 0x00000001)
 
     rx_frame = await tb.serdes_sinks[0].recv()
 
@@ -176,11 +187,12 @@ async def test_sanity(dut):
 
     await Timer(1, "us")
 
-    await dev_bar0.write_dword(0x20, 0x00000100)
+    # DMA from dma memory to host
-    await dev_bar0.write_dword(0x24, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_wr.src_addr.addr, 0x00000000)
-    await dev_bar0.write_dword(0x28, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_wr.dst_addr_low.addr, 0x00000000)
-    await dev_bar0.write_dword(0x2c, len(message))
+    await dev_bar0.write_dword(pcie_dma_wr.dst_addr_high.addr, 0x00000000)
-    await dev_bar0.write_dword(0x30, 0x00000001)
+    await dev_bar0.write_dword(pcie_dma_wr.length.addr, len(message))
+    await dev_bar0.write_dword(pcie_dma_wr.trigger.addr, 0x00000001)
 
     await Timer(1, "us")
 

sim/alibaba_pcie_top_regs.py

@@ -0,0 +1 @@
+../src/regs/alibaba_pcie_top_regs.py

sources.list

@@ -3,11 +3,15 @@ ip/taxi_eth_phy_25g_us_gty_ch/taxi_eth_phy_25g_us_gty_ch.xci
 ip/taxi_eth_phy_25g_us_gty_full/taxi_eth_phy_25g_us_gty_full.xci
 ip/taxi_eth_phy_25g_us_gty_ll_ch/taxi_eth_phy_25g_us_gty_ll_ch.xci
 ip/taxi_eth_phy_25g_us_gty_ll_full/taxi_eth_phy_25g_us_gty_ll_full.xci
-src/alibaba_cloud.xdc
+
-src/alibaba_pcie_top.sv
-src/regs/verilator.vlt
-src/regs/pcie_dma_regs_pkg.sv
-src/regs/pcie_dma_regs.sv
-src/pcie_dma_wrapper.sv
-src/eth_dma_wrapper.sv
 sub/taxi_sources.list
+
+src/pcie/sources.list
+src/eth/sources.list
+
+src/regs/verilator.vlt
+src/regs/alibaba_pcie_top_regs_pkg.sv
+src/regs/alibaba_pcie_top_regs.sv
+src/alibaba_pcie_top.sv
+
+src/alibaba_cloud.xdc

src/alibaba_pcie_top.sv

@@ -42,102 +42,24 @@ module alibaba_pcie(
 );
 
 
-
-logic clk_pcie_gt;
-logic clk_pcie;
-logic rst_pcie;
-
 logic clk_250;
 logic rst_250;
 
-logic user_lnk_up;
-logic phy_rdy_out;
-
-taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(33), .KEEP_W(8)) s_axis_cc();
-taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(88), .KEEP_W(8)) m_axis_cq();
-
-taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(62), .KEEP_W(8)) s_axis_rq();
-taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
-
 taxi_axil_if m_axil_rd();
 taxi_axil_if m_axil_wr();
 
-taxi_apb_if #(.ADDR_W(7)) s_apb();
+taxi_apb_if #(.ADDR_W(alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH)) s_apb();
 
-taxi_apb_if #(.ADDR_W(6)) m_apb[2]();
+taxi_apb_if #(.ADDR_W(pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH)) pcie_apb();
-
+taxi_apb_if #(.ADDR_W(eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH)) eth_apb();
-`ifndef SIM
-IBUFDS_GTE4 m_ibufds (
-    .CEB('0),
-    .I(pcie_mgt_refclk_p),
-    .IB(pcie_mgt_refclk_n),
-    .O(clk_pcie_gt),
-    .ODIV2(clk_pcie)
-);
-`endif
-
-assign Led_o[0] = user_lnk_up;
-assign Led_o[1] = phy_rdy_out; 
-
-
-taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_rd_if();
-taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_wr_if();
 
 taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_rd_if();
 taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_wr_if();
 
-taxi_apb_interconnect #(
+alibaba_pcie_top_regs u_alibaba_pcie_top_regs (
-    .M_CNT(2),
-    .ADDR_W(7),
-    .M_REGIONS(1),
-    .M_BASE_ADDR('0),
-    .M_ADDR_W({32'd6, 32'd6}),
-    .M_SECURE({2{1'b0}})
-) u_apb_interconnect (
-    .clk                            (clk_250),
-    .rst                            (rst_250),
-
     .s_apb                          (s_apb),
-
+    .m_apb_pcie_top_regs            (pcie_apb),
-    .m_apb                          (m_apb)
+    .m_apb_eth_dma_wrapper_regs     (eth_apb)
-);
-
-taxi_dma_psdpram #(
-    .SIZE(16384)
-) u_taxi_dma_tx_psdpram (
-    .clk                            (clk_250),
-    .rst                            (rst_250),
-
-    .dma_ram_wr                     (dma_ram_pcie_wr_if),
-    .dma_ram_rd                     (dma_ram_eth_rd_if)
-);
-
-taxi_dma_psdpram #(
-    .SIZE(16384)
-) u_taxi_dma_rx_psdpram(
-    .clk                            (clk_250),
-    .rst                            (rst_250),
-
-    .dma_ram_wr                     (dma_ram_eth_wr_if),
-    .dma_ram_rd                     (dma_ram_pcie_rd_if)
-);
-
-
-taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
-    .clk                (clk_250),
-    .rst                (rst_250),
-
-    .s_axis_cq          (m_axis_cq),
-    .m_axis_cc          (s_axis_cc),
-
-    .m_axil_wr          (m_axil_wr),
-    .m_axil_rd          (m_axil_rd),
-
-    .completer_id       ('0),
-    .completer_id_en    ('0),
-
-    .stat_err_cor       (),
-    .stat_err_uncor     ()
 );
 
 taxi_axil_apb_adapter u_taxi_axil_apb_adapter (
@@ -150,18 +72,6 @@ taxi_axil_apb_adapter u_taxi_axil_apb_adapter (
     .m_apb              (s_apb)
 );
 
-pcie_dma_wrapper u_pcie_dma_wrapper (
-    .clk                (clk_250),
-    .rst                (rst_250),
-
-    .m_axis_rq          (s_axis_rq),
-    .s_axis_rc          (m_axis_rc),
-
-    .wr_dma_mst         (dma_ram_pcie_wr_if),
-    .rd_dma_mst         (dma_ram_pcie_rd_if),
-
-    .s_apb              (m_apb[0])
-);
 
 eth_dma_wrapper u_eth_dma_wrapper (
     .clk_250            (clk_250),
@@ -178,73 +88,33 @@ eth_dma_wrapper u_eth_dma_wrapper (
     .wr_dma_mst         (dma_ram_eth_wr_if),
     .rd_dma_mst         (dma_ram_eth_rd_if),
 
-    .s_apb              (m_apb[1])
+    .s_apb              (eth_apb)
 );
 
-`ifndef SIM
+pcie_top u_pcie_top(
-pcie4_uscale_plus_0 u_pcie4_uscale_plus_0 (
+    .pci_exp_rxp        (pci_exp_rxp),
-    .pci_exp_txn(pci_exp_txn),
+    .pci_exp_rxn        (pci_exp_rxn),
-    .pci_exp_txp(pci_exp_txp),
+    .pci_exp_txp        (pci_exp_txp),
-    .pci_exp_rxn(pci_exp_rxn),
+    .pci_exp_txn        (pci_exp_txn),
-    .pci_exp_rxp(pci_exp_rxp),
 
-    .user_clk(clk_250),
+    .pcie_mgt_refclk_p  (pcie_mgt_refclk_p),
-    .user_reset(rst_250),
+    .pcie_mgt_refclk_n  (pcie_mgt_refclk_n),
-    .user_lnk_up(user_lnk_up),
 
-    .s_axis_rq_tdata(s_axis_rq.tdata),
+    .pcie_reset_n       (pcie_reset_n),
-    .s_axis_rq_tkeep(s_axis_rq.tkeep),
-    .s_axis_rq_tlast(s_axis_rq.tlast),
-    .s_axis_rq_tready(s_axis_rq.tready),
-    .s_axis_rq_tuser(s_axis_rq.tuser),
-    .s_axis_rq_tvalid(s_axis_rq.tvalid),
 
-    .m_axis_rc_tdata(m_axis_rc.tdata),
+    .user_lnk_up        (Led_o[0]),
-    .m_axis_rc_tkeep(m_axis_rc.tkeep),
+    .phy_rdy_out        (Led_o[1]),
-    .m_axis_rc_tlast(m_axis_rc.tlast),
-    .m_axis_rc_tready(m_axis_rc.tready),
-    .m_axis_rc_tuser(m_axis_rc.tuser),
-    .m_axis_rc_tvalid(m_axis_rc.tvalid),
 
-    .m_axis_cq_tdata(m_axis_cq.tdata),
+    .o_clk_250          (clk_250),
-    .m_axis_cq_tkeep(m_axis_cq.tkeep),
+    .o_rst_250          (rst_250),
-    .m_axis_cq_tlast(m_axis_cq.tlast),
-    .m_axis_cq_tready(m_axis_cq.tready),
-    .m_axis_cq_tuser(m_axis_cq.tuser),
-    .m_axis_cq_tvalid(m_axis_cq.tvalid),
 
-    .s_axis_cc_tdata(s_axis_cc.tdata),
+    .dma_ram_eth_wr_if  (dma_ram_eth_wr_if),
-    .s_axis_cc_tkeep(s_axis_cc.tkeep),
+    .dma_ram_eth_rd_if  (dma_ram_eth_rd_if),
-    .s_axis_cc_tlast(s_axis_cc.tlast),
-    .s_axis_cc_tready(s_axis_cc.tready),
-    .s_axis_cc_tuser(s_axis_cc.tuser),
-    .s_axis_cc_tvalid(s_axis_cc.tvalid),
 
-    .cfg_interrupt_int('0),
+    .m_axil_rd          (m_axil_rd),
-    .cfg_interrupt_pending(),
+    .m_axil_wr          (m_axil_wr),
-    .cfg_interrupt_sent('0),
-    .cfg_interrupt_msi_enable(),
-    .cfg_interrupt_msi_mmenable(),
-    .cfg_interrupt_msi_mask_update(),
-    .cfg_interrupt_msi_data(),
-    .cfg_interrupt_msi_select('0),
-    .cfg_interrupt_msi_int('0),
-    .cfg_interrupt_msi_pending_status('0),
-    .cfg_interrupt_msi_pending_status_data_enable('0),
-    .cfg_interrupt_msi_pending_status_function_num('0),
-    .cfg_interrupt_msi_sent(),
-    .cfg_interrupt_msi_fail(),
-    .cfg_interrupt_msi_attr('0),
-    .cfg_interrupt_msi_tph_present('0),
-    .cfg_interrupt_msi_tph_type('0),
-    .cfg_interrupt_msi_tph_st_tag('0),
-    .cfg_interrupt_msi_function_number('0),
 
-    .sys_clk(clk_pcie),
+    .s_apb              (pcie_apb)
-    .sys_clk_gt(clk_pcie_gt),
-    .sys_reset(pcie_reset_n),
-    .phy_rdy_out(phy_rdy_out)
 );
-`endif
 
 endmodule

src/eth/eth_dma_wrapper.sv

@@ -84,6 +84,53 @@ endgenerate
 
 taxi_axis_if axis_sfp_stat();
 
+taxi_apb_if #(.ADDR_W(pcie_dma_regs_pkg::PCIE_DMA_REGS_MIN_ADDR_WIDTH)) eth_dma_apb();
+taxi_apb_if #(.ADDR_W(eth_mac_25g_us_regs_pkg::ETH_MAC_25G_US_REGS_MIN_ADDR_WIDTH)) eth_mac_apb();
+
+eth_dma_wrapper_regs u_eth_dma_wrapper_regs (
+    .s_apb                          (s_apb),
+    .m_apb_eth_mac_25g_us_regs      (eth_mac_apb),
+    .m_apb_pcie_dma_regs            (eth_dma_apb)
+);
+
+eth_mac_25g_us_regs_pkg::eth_mac_25g_us_regs__in_t hwif_in;
+
+eth_mac_25g_us_regs u_eth_mac_25g_us_regs (
+    .clk                            (clk_250),
+    .rst                            (rst_250),
+
+    .s_apb_psel                     (eth_mac_apb.psel),
+    .s_apb_penable                  (eth_mac_apb.penable),
+    .s_apb_pwrite                   (eth_mac_apb.pwrite),
+    .s_apb_pprot                    (eth_mac_apb.pprot),
+    .s_apb_paddr                    (eth_mac_apb.paddr),
+    .s_apb_pwdata                   (eth_mac_apb.pwdata),
+    .s_apb_pstrb                    (eth_mac_apb.pstrb),
+    .s_apb_pready                   (eth_mac_apb.pready),
+    .s_apb_prdata                   (eth_mac_apb.prdata),
+    .s_apb_pslverr                  (eth_mac_apb.pslverr),
+
+    .hwif_in                        (hwif_in)
+);
+
+logic rx_block_lock[2];
+logic rx_status[2];
+
+logic xcvr_qpll0lock_out;
+logic xcvr_qpll1lock_out;
+
+always_comb begin
+    hwif_in.common.xcvr_gtpowergood_out.xcvr_gtpowergood_out.next = xcvr_gtpowergood;
+    hwif_in.common.xcvr_qpll0lock_out.xcvr_qpll0lock_out.next = xcvr_qpll0lock_out;
+    hwif_in.common.xcvr_qpll1lock_out.xcvr_qpll1lock_out.next = xcvr_qpll1lock_out;
+
+    for (int i = 0; i < 2; i++) begin
+        hwif_in.lanes[i].rx_block_lock.rx_block_lock.next = rx_block_lock[i];
+        hwif_in.lanes[i].rx_status.rx_status.next = rx_status[i];
+    end
+end
+
+
 taxi_eth_mac_25g_us #(
 `ifdef SIM
     .SIM('1),
@@ -106,14 +153,14 @@ taxi_eth_mac_25g_us #(
     .xcvr_qpll0pd_in                    (1'b0),
     .xcvr_qpll0reset_in                 (1'b0),
     .xcvr_qpll0pcierate_in              (3'd0),
-    .xcvr_qpll0lock_out                 (),
+    .xcvr_qpll0lock_out                 (xcvr_qpll0lock_out),
     .xcvr_qpll0clk_out                  (),
     .xcvr_qpll0refclk_out               (),
     .xcvr_gtrefclk01_in                 (sfp_mgt_refclk),
     .xcvr_qpll1pd_in                    (1'b0),
     .xcvr_qpll1reset_in                 (1'b0),
     .xcvr_qpll1pcierate_in              (3'd0),
-    .xcvr_qpll1lock_out                 (),
+    .xcvr_qpll1lock_out                 (xcvr_qpll1lock_out),
     .xcvr_qpll1clk_out                  (),
     .xcvr_qpll1refclk_out               (),
 
@@ -176,9 +223,9 @@ taxi_eth_mac_25g_us #(
     .stat_tx_err_underflow              (),
     .rx_start_packet                    (),
     .rx_error_count                     (),
-    .rx_block_lock                      (),
+    .rx_block_lock                      (rx_block_lock),
     .rx_high_ber                        (),
-    .rx_status                          (),
+    .rx_status                          (rx_status),
     .stat_rx_byte                       (),
     .stat_rx_pkt_len                    (),
     .stat_rx_pkt_fragment               (),
@@ -259,26 +306,26 @@ taxi_eth_mac_25g_us #(
 taxi_dma_desc_if #(.SRC_ADDR_W(16), .DST_ADDR_W(16), .ID_W(8), .DEST_W(8)) rd_desc();
 taxi_dma_desc_if #(.SRC_ADDR_W(16), .DST_ADDR_W(16), .ID_W(8), .DEST_W(8)) wr_desc();
 
-pcie_dma_regs_pkg::pcie_dma_regs__in_t hwif_in;
+pcie_dma_regs_pkg::pcie_dma_regs__in_t dma_hwif_in;
-pcie_dma_regs_pkg::pcie_dma_regs__out_t hwif_out;
+pcie_dma_regs_pkg::pcie_dma_regs__out_t dma_hwif_out;
 
 pcie_dma_regs u_pcie_dma_regs(
     .clk                            (clk_250),
     .rst                            (rst_250),
 
-    .s_apb_psel                     (s_apb.psel),
+    .s_apb_psel                     (eth_dma_apb.psel),
-    .s_apb_penable                  (s_apb.penable),
+    .s_apb_penable                  (eth_dma_apb.penable),
-    .s_apb_pwrite                   (s_apb.pwrite),
+    .s_apb_pwrite                   (eth_dma_apb.pwrite),
-    .s_apb_pprot                    (s_apb.pprot),
+    .s_apb_pprot                    (eth_dma_apb.pprot),
-    .s_apb_paddr                    (s_apb.paddr),
+    .s_apb_paddr                    (eth_dma_apb.paddr),
-    .s_apb_pwdata                   (s_apb.pwdata),
+    .s_apb_pwdata                   (eth_dma_apb.pwdata),
-    .s_apb_pstrb                    (s_apb.pstrb),
+    .s_apb_pstrb                    (eth_dma_apb.pstrb),
-    .s_apb_pready                   (s_apb.pready),
+    .s_apb_pready                   (eth_dma_apb.pready),
-    .s_apb_prdata                   (s_apb.prdata),
+    .s_apb_prdata                   (eth_dma_apb.prdata),
-    .s_apb_pslverr                  (s_apb.pslverr),
+    .s_apb_pslverr                  (eth_dma_apb.pslverr),
 
-    .hwif_in                        (hwif_in),
+    .hwif_in                        (dma_hwif_in),
-    .hwif_out                       (hwif_out)
+    .hwif_out                       (dma_hwif_out)
 );
 
 logic [7:0] read_tag;
@@ -300,35 +347,35 @@ end
 
 
 always_comb begin
-    rd_desc.req_src_addr = hwif_out.dma_rd.src_addr_low.addr.value[15:0];
+    rd_desc.req_src_addr = dma_hwif_out.dma_rd.src_addr_low.addr.value[15:0];
     rd_desc.req_src_sel = '0;
-    rd_desc.req_dst_addr = hwif_out.dma_rd.dst_addr.addr.value;
+    rd_desc.req_dst_addr = dma_hwif_out.dma_rd.dst_addr.addr.value;
     rd_desc.req_dst_sel = '0;
     rd_desc.req_imm = '0;
     rd_desc.req_imm_en = '0;
-    rd_desc.req_len = hwif_out.dma_rd.length.len.value;
+    rd_desc.req_len = dma_hwif_out.dma_rd.length.len.value;
     rd_desc.req_tag = read_tag;
     rd_desc.req_id = '0;
     rd_desc.req_dest = '0;
     rd_desc.req_user = '0;
-    rd_desc.req_valid = hwif_out.dma_rd.trigger.trigger.value;
+    rd_desc.req_valid = dma_hwif_out.dma_rd.trigger.trigger.value;
-    hwif_in.dma_rd.trigger.trigger.hwclr = (rd_desc.req_valid && rd_desc.req_ready);
+    dma_hwif_in.dma_rd.trigger.trigger.hwclr = (rd_desc.req_valid && rd_desc.req_ready);
-    hwif_in.dma_rd.done.done.hwset = rd_desc.sts_valid;
+    dma_hwif_in.dma_rd.done.done.hwset = rd_desc.sts_valid;
 
-    wr_desc.req_src_addr = hwif_out.dma_wr.src_addr.addr.value;
+    wr_desc.req_src_addr = dma_hwif_out.dma_wr.src_addr.addr.value;
     wr_desc.req_src_sel = '0;
-    wr_desc.req_dst_addr = hwif_out.dma_wr.dst_addr_low.addr.value[15:0];
+    wr_desc.req_dst_addr = dma_hwif_out.dma_wr.dst_addr_low.addr.value[15:0];
     wr_desc.req_dst_sel = '0;
     wr_desc.req_imm = '0;
     wr_desc.req_imm_en = '0;
-    wr_desc.req_len = hwif_out.dma_wr.length.len.value;
+    wr_desc.req_len = dma_hwif_out.dma_wr.length.len.value;
     wr_desc.req_tag = write_tag;
     wr_desc.req_id = '0;
     wr_desc.req_dest = '0;
     wr_desc.req_user = '0;
-    wr_desc.req_valid = hwif_out.dma_wr.trigger.trigger.value;
+    wr_desc.req_valid = dma_hwif_out.dma_wr.trigger.trigger.value;
-    hwif_in.dma_wr.trigger.trigger.hwclr = (wr_desc.req_valid && wr_desc.req_ready);
+    dma_hwif_in.dma_wr.trigger.trigger.hwclr = (wr_desc.req_valid && wr_desc.req_ready);
-    hwif_in.dma_wr.done.done.hwset = wr_desc.sts_valid;
+    dma_hwif_in.dma_wr.done.done.hwset = wr_desc.sts_valid;
 end
 
 // 250 is too slow to actually saturate 25Gbps, but

src/eth/regs/compile_regs.sh

@@ -0,0 +1,2 @@
+peakrdl regblock -t eth_mac_25g_us_regs eth_mac_25g_us_regs.rdl -o . --cpuif apb4-flat
+peakrdl busdecoder -t eth_dma_wrapper_regs eth_mac_25g_us_regs.rdl ../../pcie/regs/pcie_dma_regs.rdl eth_dma_wrapper_regs.rdl  -o . --cpuif taxi-apb

src/eth/regs/eth_dma_wrapper_regs.rdl

@@ -0,0 +1,5 @@
+addrmap eth_dma_wrapper_regs {
+
+    external eth_mac_25g_us_regs eth_mac_25g_us_regs @ 0x0;
+    external pcie_dma_regs pcie_dma_regs @ 0x80;
+};

src/eth/regs/eth_dma_wrapper_regs.sv

@@ -0,0 +1,169 @@
+//==========================================================
+//  Module: eth_dma_wrapper_regs
+//  Description: CPU Interface Bus Decoder
+//  Author: PeakRDL-BusDecoder
+//  License: LGPL-3.0
+//  Date: 2025-11-22
+//  Version: 0.5.0
+//  Links:
+//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
+//==========================================================
+
+
+module eth_dma_wrapper_regs (
+    taxi_apb_if.slv s_apb,
+    taxi_apb_if.mst m_apb_eth_mac_25g_us_regs,
+    taxi_apb_if.mst m_apb_pcie_dma_regs
+);
+    //--------------------------------------------------------------------------
+    // CPU Bus interface logic
+    //--------------------------------------------------------------------------
+    logic cpuif_req;
+    logic cpuif_wr_en;
+    logic cpuif_rd_en;
+    logic [7:0] cpuif_wr_addr;
+    logic [7:0] cpuif_rd_addr;
+
+    logic cpuif_wr_ack;
+    logic cpuif_wr_err;
+    logic [31:0] cpuif_wr_data;
+    logic [3:0] cpuif_wr_byte_en;
+
+    logic cpuif_rd_ack;
+    logic cpuif_rd_err;
+    logic [31:0] cpuif_rd_data;
+
+    //--------------------------------------------------------------------------
+    // Child instance signals
+    //--------------------------------------------------------------------------
+    typedef struct {
+        logic eth_mac_25g_us_regs;
+        logic pcie_dma_regs;
+        logic cpuif_err;
+    } cpuif_sel_t;
+    cpuif_sel_t cpuif_wr_sel;
+    cpuif_sel_t cpuif_rd_sel;
+
+    //--------------------------------------------------------------------------
+    // Slave <-> Internal CPUIF <-> Master
+    //--------------------------------------------------------------------------
+    
+    `ifndef SYNTHESIS
+        initial begin
+            assert_bad_addr_width: assert($bits(s_apb.paddr) >= eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH)
+                else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH);
+            assert_bad_data_width: assert($bits(s_apb.pwdata) == eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_DATA_WIDTH)
+                else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_DATA_WIDTH);
+        end
+        `ifdef PEAKRDL_ASSERTIONS
+        assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
+            else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+        `endif
+    `endif
+
+    assign cpuif_req   = s_apb.psel;
+    assign cpuif_wr_en = s_apb.pwrite;
+    assign cpuif_rd_en = !s_apb.pwrite;
+
+    assign cpuif_wr_addr = s_apb.paddr;
+    assign cpuif_rd_addr = s_apb.paddr;
+
+    assign cpuif_wr_data = s_apb.pwdata;
+    assign cpuif_wr_byte_en = s_apb.pstrb;
+
+    assign s_apb.prdata = cpuif_rd_data;
+    assign s_apb.pready = cpuif_rd_ack;
+    assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+
+    //--------------------------------------------------------------------------
+    // Fanout CPU Bus interface signals
+    //--------------------------------------------------------------------------
+    assign m_apb_eth_mac_25g_us_regs.psel = cpuif_wr_sel.eth_mac_25g_us_regs|cpuif_rd_sel.eth_mac_25g_us_regs;
+    assign m_apb_eth_mac_25g_us_regs.penable = s_apb.penable;
+    assign m_apb_eth_mac_25g_us_regs.pwrite = cpuif_wr_sel.eth_mac_25g_us_regs;
+    assign m_apb_eth_mac_25g_us_regs.paddr = s_apb.paddr;
+    assign m_apb_eth_mac_25g_us_regs.pprot = s_apb.pprot;
+    assign m_apb_eth_mac_25g_us_regs.pwdata = cpuif_wr_data;
+    assign m_apb_eth_mac_25g_us_regs.pstrb = cpuif_wr_byte_en;
+    assign m_apb_pcie_dma_regs.psel = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
+    assign m_apb_pcie_dma_regs.penable = s_apb.penable;
+    assign m_apb_pcie_dma_regs.pwrite = cpuif_wr_sel.pcie_dma_regs;
+    assign m_apb_pcie_dma_regs.paddr = s_apb.paddr;
+    assign m_apb_pcie_dma_regs.pprot = s_apb.pprot;
+    assign m_apb_pcie_dma_regs.pwdata = cpuif_wr_data;
+    assign m_apb_pcie_dma_regs.pstrb = cpuif_wr_byte_en;
+
+    //--------------------------------------------------------------------------
+    // Intermediate signals for interface array fanin
+    //--------------------------------------------------------------------------
+
+
+    //--------------------------------------------------------------------------
+    // Fanin CPU Bus interface signals
+    //--------------------------------------------------------------------------
+    always_comb begin
+        cpuif_rd_ack = '0;
+        cpuif_rd_err = '0;
+        cpuif_rd_data = '0;
+        if (cpuif_rd_sel.eth_mac_25g_us_regs || cpuif_wr_sel.eth_mac_25g_us_regs) begin
+            cpuif_rd_ack = m_apb_eth_mac_25g_us_regs.pready;
+            cpuif_rd_err = m_apb_eth_mac_25g_us_regs.pslverr;
+        end
+        if (cpuif_rd_sel.eth_mac_25g_us_regs) begin
+            cpuif_rd_data = m_apb_eth_mac_25g_us_regs.prdata;
+        end
+        if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin
+            cpuif_rd_ack = m_apb_pcie_dma_regs.pready;
+            cpuif_rd_err = m_apb_pcie_dma_regs.pslverr;
+        end
+        if (cpuif_rd_sel.pcie_dma_regs) begin
+            cpuif_rd_data = m_apb_pcie_dma_regs.prdata;
+        end
+    end
+
+    //--------------------------------------------------------------------------
+    // Write Address Decoder
+    //--------------------------------------------------------------------------
+    always_comb begin
+        // Default all write select signals to 0
+        cpuif_wr_sel = '{default: '0};
+
+        if (cpuif_req && cpuif_wr_en) begin
+            // A write request is pending
+            if ((cpuif_wr_addr < (8'h60))) begin
+                cpuif_wr_sel.eth_mac_25g_us_regs = 1'b1;
+            end
+            else if ((cpuif_wr_addr >= (8'h80)) && (cpuif_wr_addr < (8'hb8))) begin
+                cpuif_wr_sel.pcie_dma_regs = 1'b1;
+            end
+            else begin
+                cpuif_wr_sel.cpuif_err = 1'b1;
+            end
+        end else begin
+            // No write request, all select signals remain 0
+        end
+    end
+
+    //--------------------------------------------------------------------------
+    // Read Address Decoder
+    //--------------------------------------------------------------------------
+    always_comb begin
+        // Default all read select signals to 0
+        cpuif_rd_sel = '{default: '0};
+
+        if (cpuif_req && cpuif_rd_en) begin
+            // A read request is pending
+            if ((cpuif_rd_addr < (8'h60))) begin
+                cpuif_rd_sel.eth_mac_25g_us_regs = 1'b1;
+            end
+            else if ((cpuif_rd_addr >= (8'h80)) && (cpuif_rd_addr < (8'hb8))) begin
+                cpuif_rd_sel.pcie_dma_regs = 1'b1;
+            end
+            else begin
+                cpuif_rd_sel.cpuif_err = 1'b1;
+            end
+        end else begin
+            // No read request, all select signals remain 0
+        end
+    end
+endmodule

src/eth/regs/eth_dma_wrapper_regs_pkg.sv

@@ -0,0 +1,19 @@
+//==========================================================
+//  Package: eth_dma_wrapper_regs_pkg
+//  Description: CPU Interface Bus Decoder Package
+//  Author: PeakRDL-BusDecoder
+//  License: LGPL-3.0
+//  Date: 2025-11-22
+//  Version: 0.5.0
+//  Links:
+//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
+//==========================================================
+
+
+package eth_dma_wrapper_regs_pkg;
+    localparam ETH_DMA_WRAPPER_REGS_DATA_WIDTH = 32;
+    localparam ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH = 8;
+    localparam ETH_DMA_WRAPPER_REGS_SIZE = 'hb8;
+    localparam ETH_DMA_WRAPPER_REGS_ETH_MAC_25G_US_REGS_ADDR_WIDTH = 7;
+    localparam ETH_DMA_WRAPPER_REGS_PCIE_DMA_REGS_ADDR_WIDTH = 6;
+endpackage

src/eth/regs/eth_mac_25g_us_regs.rdl

@@ -0,0 +1,73 @@
+addrmap eth_mac_25g_us_regs {
+    name = "";
+    desc = "";
+    
+
+    regfile {
+        reg {
+            name = "xcvr_gtpowergood_out";
+            desc = "";
+
+            field {
+                name = "xcvr_gtpowergood_out";
+                desc = "";
+                hw   = w;
+                sw   = r;
+            } xcvr_gtpowergood_out[0:0] = 0x0;
+            
+        } xcvr_gtpowergood_out @ 0x0;
+
+        reg {
+            name = "xcvr_qpll0lock_out";
+            desc = "";
+            
+            field {
+                name = "xcvr_qpll0lock_out";
+                desc = "";
+                hw   = w;
+                sw   = r;
+            } xcvr_qpll0lock_out[0:0] = 0x0;
+        } xcvr_qpll0lock_out @ 0x4;
+        reg {
+            name = "xcvr_qpll1lock_out";
+            desc = "";
+            
+            field {
+                name = "xcvr_qpll1lock_out";
+                desc = "";
+                hw   = w;
+                sw   = r;
+            } xcvr_qpll1lock_out[0:0] = 0x0;
+        } xcvr_qpll1lock_out @ 0x8;
+    } common @0x0;
+
+    regfile lane {
+        reg {
+            name = "rx_block_lock";
+            desc = "";
+
+            field {
+                name = "rx_block_lock";
+                desc = "";
+                hw   = w;
+                sw   = r;
+            } rx_block_lock[0:0] = 0x0;
+            
+        } rx_block_lock @ 0x0;
+
+        reg {
+            name = "rx_status";
+            desc = "";
+
+            field {
+                name = "rx_status";
+                desc = "";
+                hw   = w;
+                sw   = r;
+            } rx_status[0:0] = 0x0;
+            
+        } rx_status @ 0x4;
+    };
+
+    lane lanes[2] @ 0x20 += 0x20;
+};

src/eth/regs/eth_mac_25g_us_regs.sv

@@ -0,0 +1,179 @@
+// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
+//  https://github.com/SystemRDL/PeakRDL-regblock
+
+module eth_mac_25g_us_regs (
+        input wire clk,
+        input wire rst,
+
+        input wire s_apb_psel,
+        input wire s_apb_penable,
+        input wire s_apb_pwrite,
+        input wire [2:0] s_apb_pprot,
+        input wire [6:0] s_apb_paddr,
+        input wire [31:0] s_apb_pwdata,
+        input wire [3:0] s_apb_pstrb,
+        output logic s_apb_pready,
+        output logic [31:0] s_apb_prdata,
+        output logic s_apb_pslverr,
+
+        input eth_mac_25g_us_regs_pkg::eth_mac_25g_us_regs__in_t hwif_in
+    );
+
+    //--------------------------------------------------------------------------
+    // CPU Bus interface logic
+    //--------------------------------------------------------------------------
+    logic cpuif_req;
+    logic cpuif_req_is_wr;
+    logic [6:0] cpuif_addr;
+    logic [31:0] cpuif_wr_data;
+    logic [31:0] cpuif_wr_biten;
+    logic cpuif_req_stall_wr;
+    logic cpuif_req_stall_rd;
+
+    logic cpuif_rd_ack;
+    logic cpuif_rd_err;
+    logic [31:0] cpuif_rd_data;
+
+    logic cpuif_wr_ack;
+    logic cpuif_wr_err;
+
+    // Request
+    logic is_active;
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            is_active <= '0;
+            cpuif_req <= '0;
+            cpuif_req_is_wr <= '0;
+            cpuif_addr <= '0;
+            cpuif_wr_data <= '0;
+            cpuif_wr_biten <= '0;
+        end else begin
+            if(~is_active) begin
+                if(s_apb_psel) begin
+                    is_active <= '1;
+                    cpuif_req <= '1;
+                    cpuif_req_is_wr <= s_apb_pwrite;
+                    cpuif_addr <= {s_apb_paddr[6:2], 2'b0};
+                    cpuif_wr_data <= s_apb_pwdata;
+                    for(int i=0; i<4; i++) begin
+                        cpuif_wr_biten[i*8 +: 8] <= {8{s_apb_pstrb[i]}};
+                    end
+                end
+            end else begin
+                cpuif_req <= '0;
+                if(cpuif_rd_ack || cpuif_wr_ack) begin
+                    is_active <= '0;
+                end
+            end
+        end
+    end
+
+    // Response
+    assign s_apb_pready = cpuif_rd_ack | cpuif_wr_ack;
+    assign s_apb_prdata = cpuif_rd_data;
+    assign s_apb_pslverr = cpuif_rd_err | cpuif_wr_err;
+
+    logic cpuif_req_masked;
+
+    // Read & write latencies are balanced. Stalls not required
+    assign cpuif_req_stall_rd = '0;
+    assign cpuif_req_stall_wr = '0;
+    assign cpuif_req_masked = cpuif_req
+                            & !(!cpuif_req_is_wr & cpuif_req_stall_rd)
+                            & !(cpuif_req_is_wr & cpuif_req_stall_wr);
+
+    //--------------------------------------------------------------------------
+    // Address Decode
+    //--------------------------------------------------------------------------
+    typedef struct {
+        struct {
+            logic xcvr_gtpowergood_out;
+            logic xcvr_qpll0lock_out;
+            logic xcvr_qpll1lock_out;
+        } common;
+        struct {
+            logic rx_block_lock;
+            logic rx_status;
+        } lanes[2];
+    } decoded_reg_strb_t;
+    decoded_reg_strb_t decoded_reg_strb;
+    logic decoded_err;
+    logic decoded_req;
+    logic decoded_req_is_wr;
+    logic [31:0] decoded_wr_data;
+    logic [31:0] decoded_wr_biten;
+
+    always_comb begin
+        automatic logic is_valid_addr;
+        automatic logic is_invalid_rw;
+        is_valid_addr = '1; // No error checking on valid address access
+        is_invalid_rw = '0;
+        decoded_reg_strb.common.xcvr_gtpowergood_out = cpuif_req_masked & (cpuif_addr == 7'h0) & !cpuif_req_is_wr;
+        decoded_reg_strb.common.xcvr_qpll0lock_out = cpuif_req_masked & (cpuif_addr == 7'h4) & !cpuif_req_is_wr;
+        decoded_reg_strb.common.xcvr_qpll1lock_out = cpuif_req_masked & (cpuif_addr == 7'h8) & !cpuif_req_is_wr;
+        for(int i0=0; i0<2; i0++) begin
+            decoded_reg_strb.lanes[i0].rx_block_lock = cpuif_req_masked & (cpuif_addr == 7'h20 + (7)'(i0) * 7'h20) & !cpuif_req_is_wr;
+            decoded_reg_strb.lanes[i0].rx_status = cpuif_req_masked & (cpuif_addr == 7'h24 + (7)'(i0) * 7'h20) & !cpuif_req_is_wr;
+        end
+        decoded_err = (~is_valid_addr | is_invalid_rw) & decoded_req;
+    end
+
+    // Pass down signals to next stage
+    assign decoded_req = cpuif_req_masked;
+    assign decoded_req_is_wr = cpuif_req_is_wr;
+    assign decoded_wr_data = cpuif_wr_data;
+    assign decoded_wr_biten = cpuif_wr_biten;
+
+    //--------------------------------------------------------------------------
+    // Field logic
+    //--------------------------------------------------------------------------
+    
+
+    
+
+    
+
+    //--------------------------------------------------------------------------
+    // Write response
+    //--------------------------------------------------------------------------
+    assign cpuif_wr_ack = decoded_req & decoded_req_is_wr;
+    // Writes are always granted with no error response
+    assign cpuif_wr_err = '0;
+
+    //--------------------------------------------------------------------------
+    // Readback
+    //--------------------------------------------------------------------------
+
+    logic readback_err;
+    logic readback_done;
+    logic [31:0] readback_data;
+
+    // Assign readback values to a flattened array
+    logic [31:0] readback_array[7];
+    assign readback_array[0][0:0] = (decoded_reg_strb.common.xcvr_gtpowergood_out && !decoded_req_is_wr) ? hwif_in.common.xcvr_gtpowergood_out.xcvr_gtpowergood_out.next : '0;
+    assign readback_array[0][31:1] = '0;
+    assign readback_array[1][0:0] = (decoded_reg_strb.common.xcvr_qpll0lock_out && !decoded_req_is_wr) ? hwif_in.common.xcvr_qpll0lock_out.xcvr_qpll0lock_out.next : '0;
+    assign readback_array[1][31:1] = '0;
+    assign readback_array[2][0:0] = (decoded_reg_strb.common.xcvr_qpll1lock_out && !decoded_req_is_wr) ? hwif_in.common.xcvr_qpll1lock_out.xcvr_qpll1lock_out.next : '0;
+    assign readback_array[2][31:1] = '0;
+    for(genvar i0=0; i0<2; i0++) begin
+        assign readback_array[i0 * 2 + 3][0:0] = (decoded_reg_strb.lanes[i0].rx_block_lock && !decoded_req_is_wr) ? hwif_in.lanes[i0].rx_block_lock.rx_block_lock.next : '0;
+        assign readback_array[i0 * 2 + 3][31:1] = '0;
+        assign readback_array[i0 * 2 + 4][0:0] = (decoded_reg_strb.lanes[i0].rx_status && !decoded_req_is_wr) ? hwif_in.lanes[i0].rx_status.rx_status.next : '0;
+        assign readback_array[i0 * 2 + 4][31:1] = '0;
+    end
+
+    // Reduce the array
+    always_comb begin
+        automatic logic [31:0] readback_data_var;
+        readback_done = decoded_req & ~decoded_req_is_wr;
+        readback_err = '0;
+        readback_data_var = '0;
+        for(int i=0; i<7; i++) readback_data_var |= readback_array[i];
+        readback_data = readback_data_var;
+    end
+
+    assign cpuif_rd_ack = readback_done;
+    assign cpuif_rd_data = readback_data;
+    assign cpuif_rd_err = readback_err;
+endmodule

src/eth/regs/eth_mac_25g_us_regs_pkg.sv

@@ -0,0 +1,65 @@
+// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
+//  https://github.com/SystemRDL/PeakRDL-regblock
+
+package eth_mac_25g_us_regs_pkg;
+
+    localparam ETH_MAC_25G_US_REGS_DATA_WIDTH = 32;
+    localparam ETH_MAC_25G_US_REGS_MIN_ADDR_WIDTH = 7;
+    localparam ETH_MAC_25G_US_REGS_SIZE = 'h60;
+
+    typedef struct {
+        logic next;
+    } eth_mac_25g_us_regs__common__xcvr_gtpowergood_out__xcvr_gtpowergood_out__in_t;
+
+    typedef struct {
+        eth_mac_25g_us_regs__common__xcvr_gtpowergood_out__xcvr_gtpowergood_out__in_t xcvr_gtpowergood_out;
+    } eth_mac_25g_us_regs__common__xcvr_gtpowergood_out__in_t;
+
+    typedef struct {
+        logic next;
+    } eth_mac_25g_us_regs__common__xcvr_qpll0lock_out__xcvr_qpll0lock_out__in_t;
+
+    typedef struct {
+        eth_mac_25g_us_regs__common__xcvr_qpll0lock_out__xcvr_qpll0lock_out__in_t xcvr_qpll0lock_out;
+    } eth_mac_25g_us_regs__common__xcvr_qpll0lock_out__in_t;
+
+    typedef struct {
+        logic next;
+    } eth_mac_25g_us_regs__common__xcvr_qpll1lock_out__xcvr_qpll1lock_out__in_t;
+
+    typedef struct {
+        eth_mac_25g_us_regs__common__xcvr_qpll1lock_out__xcvr_qpll1lock_out__in_t xcvr_qpll1lock_out;
+    } eth_mac_25g_us_regs__common__xcvr_qpll1lock_out__in_t;
+
+    typedef struct {
+        eth_mac_25g_us_regs__common__xcvr_gtpowergood_out__in_t xcvr_gtpowergood_out;
+        eth_mac_25g_us_regs__common__xcvr_qpll0lock_out__in_t xcvr_qpll0lock_out;
+        eth_mac_25g_us_regs__common__xcvr_qpll1lock_out__in_t xcvr_qpll1lock_out;
+    } eth_mac_25g_us_regs__common__in_t;
+
+    typedef struct {
+        logic next;
+    } eth_mac_25g_us_regs__lane__rx_block_lock__rx_block_lock__in_t;
+
+    typedef struct {
+        eth_mac_25g_us_regs__lane__rx_block_lock__rx_block_lock__in_t rx_block_lock;
+    } eth_mac_25g_us_regs__lane__rx_block_lock__in_t;
+
+    typedef struct {
+        logic next;
+    } eth_mac_25g_us_regs__lane__rx_status__rx_status__in_t;
+
+    typedef struct {
+        eth_mac_25g_us_regs__lane__rx_status__rx_status__in_t rx_status;
+    } eth_mac_25g_us_regs__lane__rx_status__in_t;
+
+    typedef struct {
+        eth_mac_25g_us_regs__lane__rx_block_lock__in_t rx_block_lock;
+        eth_mac_25g_us_regs__lane__rx_status__in_t rx_status;
+    } eth_mac_25g_us_regs__lane__in_t;
+
+    typedef struct {
+        eth_mac_25g_us_regs__common__in_t common;
+        eth_mac_25g_us_regs__lane__in_t lanes[2];
+    } eth_mac_25g_us_regs__in_t;
+endpackage

src/eth/sources.list

@@ -0,0 +1,6 @@
+regs/eth_dma_wrapper_regs_pkg.sv
+regs/eth_dma_wrapper_regs.sv
+regs/eth_mac_25g_us_regs_pkg.sv
+regs/eth_mac_25g_us_regs.sv
+
+eth_dma_wrapper.sv

src/pcie/pcie_top.sv

@@ -0,0 +1,181 @@
+module pcie_top(
+    input  wire [7:0]               pci_exp_rxp,
+    input  wire [7:0]               pci_exp_rxn,
+    output wire [7:0]               pci_exp_txp,
+    output wire [7:0]               pci_exp_txn,
+
+    input  wire                     pcie_mgt_refclk_p,
+    input  wire                     pcie_mgt_refclk_n,
+
+    input  wire                     pcie_reset_n,
+
+    output wire                     user_lnk_up,
+    output wire                     phy_rdy_out,
+
+    output wire                     o_clk_250,
+    output wire                     o_rst_250,
+
+    taxi_dma_ram_if.wr_slv          dma_ram_eth_wr_if,
+    taxi_dma_ram_if.rd_slv          dma_ram_eth_rd_if,
+
+    taxi_axil_if.rd_mst             m_axil_rd,
+    taxi_axil_if.wr_mst             m_axil_wr,
+
+    taxi_apb_if.slv                 s_apb
+
+);
+
+logic clk_pcie_gt;
+logic clk_pcie;
+logic rst_pcie;
+
+logic clk_250;
+logic rst_250;
+
+assign o_clk_250 = clk_250;
+assign o_rst_250 = rst_250;
+
+taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(33), .KEEP_W(8)) s_axis_cc();
+taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(88), .KEEP_W(8)) m_axis_cq();
+
+taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(62), .KEEP_W(8)) s_axis_rq();
+taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
+
+taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_rd_if();
+taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_wr_if();
+
+taxi_apb_if #(.ADDR_W(pcie_dma_regs_pkg::PCIE_DMA_REGS_MIN_ADDR_WIDTH)) pcie_dma_apb();
+
+
+`ifndef SIM
+IBUFDS_GTE4 m_ibufds (
+    .CEB('0),
+    .I(pcie_mgt_refclk_p),
+    .IB(pcie_mgt_refclk_n),
+    .O(clk_pcie_gt),
+    .ODIV2(clk_pcie)
+);
+`endif
+
+pcie_top_regs u_pcie_top_regs (
+    .s_apb              (s_apb),
+    .m_apb_pcie_dma_regs(pcie_dma_apb)
+);
+
+taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
+    .clk                (clk_250),
+    .rst                (rst_250),
+
+    .s_axis_cq          (m_axis_cq),
+    .m_axis_cc          (s_axis_cc),
+
+    .m_axil_wr          (m_axil_wr),
+    .m_axil_rd          (m_axil_rd),
+
+    .completer_id       ('0),
+    .completer_id_en    ('0),
+
+    .stat_err_cor       (),
+    .stat_err_uncor     ()
+);
+
+taxi_dma_psdpram #(
+    .SIZE(16384)
+) u_taxi_dma_tx_psdpram (
+    .clk                            (clk_250),
+    .rst                            (rst_250),
+
+    .dma_ram_wr                     (dma_ram_pcie_wr_if),
+    .dma_ram_rd                     (dma_ram_eth_rd_if)
+);
+
+taxi_dma_psdpram #(
+    .SIZE(16384)
+) u_taxi_dma_rx_psdpram(
+    .clk                            (clk_250),
+    .rst                            (rst_250),
+
+    .dma_ram_wr                     (dma_ram_eth_wr_if),
+    .dma_ram_rd                     (dma_ram_pcie_rd_if)
+);
+
+pcie_dma_wrapper u_pcie_dma_wrapper (
+    .clk                (clk_250),
+    .rst                (rst_250),
+
+    .m_axis_rq          (s_axis_rq),
+    .s_axis_rc          (m_axis_rc),
+
+    .wr_dma_mst         (dma_ram_pcie_wr_if),
+    .rd_dma_mst         (dma_ram_pcie_rd_if),
+
+    .s_apb              (pcie_dma_apb)
+);
+
+`ifndef SIM
+pcie4_uscale_plus_0 u_pcie4_uscale_plus_0 (
+    .pci_exp_txn(pci_exp_txn),
+    .pci_exp_txp(pci_exp_txp),
+    .pci_exp_rxn(pci_exp_rxn),
+    .pci_exp_rxp(pci_exp_rxp),
+
+    .user_clk(clk_250),
+    .user_reset(rst_250),
+    .user_lnk_up(user_lnk_up),
+
+    .s_axis_rq_tdata(s_axis_rq.tdata),
+    .s_axis_rq_tkeep(s_axis_rq.tkeep),
+    .s_axis_rq_tlast(s_axis_rq.tlast),
+    .s_axis_rq_tready(s_axis_rq.tready),
+    .s_axis_rq_tuser(s_axis_rq.tuser),
+    .s_axis_rq_tvalid(s_axis_rq.tvalid),
+
+    .m_axis_rc_tdata(m_axis_rc.tdata),
+    .m_axis_rc_tkeep(m_axis_rc.tkeep),
+    .m_axis_rc_tlast(m_axis_rc.tlast),
+    .m_axis_rc_tready(m_axis_rc.tready),
+    .m_axis_rc_tuser(m_axis_rc.tuser),
+    .m_axis_rc_tvalid(m_axis_rc.tvalid),
+
+    .m_axis_cq_tdata(m_axis_cq.tdata),
+    .m_axis_cq_tkeep(m_axis_cq.tkeep),
+    .m_axis_cq_tlast(m_axis_cq.tlast),
+    .m_axis_cq_tready(m_axis_cq.tready),
+    .m_axis_cq_tuser(m_axis_cq.tuser),
+    .m_axis_cq_tvalid(m_axis_cq.tvalid),
+
+    .s_axis_cc_tdata(s_axis_cc.tdata),
+    .s_axis_cc_tkeep(s_axis_cc.tkeep),
+    .s_axis_cc_tlast(s_axis_cc.tlast),
+    .s_axis_cc_tready(s_axis_cc.tready),
+    .s_axis_cc_tuser(s_axis_cc.tuser),
+    .s_axis_cc_tvalid(s_axis_cc.tvalid),
+
+    .cfg_interrupt_int('0),
+    .cfg_interrupt_pending(),
+    .cfg_interrupt_sent('0),
+    .cfg_interrupt_msi_enable(),
+    .cfg_interrupt_msi_mmenable(),
+    .cfg_interrupt_msi_mask_update(),
+    .cfg_interrupt_msi_data(),
+    .cfg_interrupt_msi_select('0),
+    .cfg_interrupt_msi_int('0),
+    .cfg_interrupt_msi_pending_status('0),
+    .cfg_interrupt_msi_pending_status_data_enable('0),
+    .cfg_interrupt_msi_pending_status_function_num('0),
+    .cfg_interrupt_msi_sent(),
+    .cfg_interrupt_msi_fail(),
+    .cfg_interrupt_msi_attr('0),
+    .cfg_interrupt_msi_tph_present('0),
+    .cfg_interrupt_msi_tph_type('0),
+    .cfg_interrupt_msi_tph_st_tag('0),
+    .cfg_interrupt_msi_function_number('0),
+
+    .sys_clk(clk_pcie),
+    .sys_clk_gt(clk_pcie_gt),
+    .sys_reset(pcie_reset_n),
+    .phy_rdy_out(phy_rdy_out)
+);
+`endif
+
+endmodule

src/pcie/regs/compile_regs.sh

@@ -0,0 +1,2 @@
+peakrdl regblock -t pcie_dma_regs pcie_dma_regs.rdl -o . --cpuif apb4-flat
+peakrdl busdecoder -t pcie_top_regs pcie_dma_regs.rdl pcie_top_regs.rdl -o . --cpuif taxi-apb

src/pcie/regs/pcie_top_regs.rdl

@@ -0,0 +1,6 @@
+addrmap pcie_top_regs {
+    name = "";
+    desc = "";
+    
+    external pcie_dma_regs pcie_dma_regs;
+};

src/pcie/regs/pcie_top_regs.sv

@@ -0,0 +1,147 @@
+//==========================================================
+//  Module: pcie_top_regs
+//  Description: CPU Interface Bus Decoder
+//  Author: PeakRDL-BusDecoder
+//  License: LGPL-3.0
+//  Date: 2025-11-22
+//  Version: 0.5.0
+//  Links:
+//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
+//==========================================================
+
+
+module pcie_top_regs (
+    taxi_apb_if.slv s_apb,
+    taxi_apb_if.mst m_apb_pcie_dma_regs
+);
+    //--------------------------------------------------------------------------
+    // CPU Bus interface logic
+    //--------------------------------------------------------------------------
+    logic cpuif_req;
+    logic cpuif_wr_en;
+    logic cpuif_rd_en;
+    logic [5:0] cpuif_wr_addr;
+    logic [5:0] cpuif_rd_addr;
+
+    logic cpuif_wr_ack;
+    logic cpuif_wr_err;
+    logic [31:0] cpuif_wr_data;
+    logic [3:0] cpuif_wr_byte_en;
+
+    logic cpuif_rd_ack;
+    logic cpuif_rd_err;
+    logic [31:0] cpuif_rd_data;
+
+    //--------------------------------------------------------------------------
+    // Child instance signals
+    //--------------------------------------------------------------------------
+    typedef struct {
+        logic pcie_dma_regs;
+        logic cpuif_err;
+    } cpuif_sel_t;
+    cpuif_sel_t cpuif_wr_sel;
+    cpuif_sel_t cpuif_rd_sel;
+
+    //--------------------------------------------------------------------------
+    // Slave <-> Internal CPUIF <-> Master
+    //--------------------------------------------------------------------------
+    
+    `ifndef SYNTHESIS
+        initial begin
+            assert_bad_addr_width: assert($bits(s_apb.paddr) >= pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH)
+                else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH);
+            assert_bad_data_width: assert($bits(s_apb.pwdata) == pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH)
+                else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH);
+        end
+        `ifdef PEAKRDL_ASSERTIONS
+        assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
+            else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+        `endif
+    `endif
+
+    assign cpuif_req   = s_apb.psel;
+    assign cpuif_wr_en = s_apb.pwrite;
+    assign cpuif_rd_en = !s_apb.pwrite;
+
+    assign cpuif_wr_addr = s_apb.paddr;
+    assign cpuif_rd_addr = s_apb.paddr;
+
+    assign cpuif_wr_data = s_apb.pwdata;
+    assign cpuif_wr_byte_en = s_apb.pstrb;
+
+    assign s_apb.prdata = cpuif_rd_data;
+    assign s_apb.pready = cpuif_rd_ack;
+    assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+
+    //--------------------------------------------------------------------------
+    // Fanout CPU Bus interface signals
+    //--------------------------------------------------------------------------
+    assign m_apb_pcie_dma_regs.psel = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
+    assign m_apb_pcie_dma_regs.penable = s_apb.penable;
+    assign m_apb_pcie_dma_regs.pwrite = cpuif_wr_sel.pcie_dma_regs;
+    assign m_apb_pcie_dma_regs.paddr = s_apb.paddr;
+    assign m_apb_pcie_dma_regs.pprot = s_apb.pprot;
+    assign m_apb_pcie_dma_regs.pwdata = cpuif_wr_data;
+    assign m_apb_pcie_dma_regs.pstrb = cpuif_wr_byte_en;
+
+    //--------------------------------------------------------------------------
+    // Intermediate signals for interface array fanin
+    //--------------------------------------------------------------------------
+
+
+    //--------------------------------------------------------------------------
+    // Fanin CPU Bus interface signals
+    //--------------------------------------------------------------------------
+    always_comb begin
+        cpuif_rd_ack = '0;
+        cpuif_rd_err = '0;
+        cpuif_rd_data = '0;
+        if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin
+            cpuif_rd_ack = m_apb_pcie_dma_regs.pready;
+            cpuif_rd_err = m_apb_pcie_dma_regs.pslverr;
+        end
+        if (cpuif_rd_sel.pcie_dma_regs) begin
+            cpuif_rd_data = m_apb_pcie_dma_regs.prdata;
+        end
+    end
+
+    //--------------------------------------------------------------------------
+    // Write Address Decoder
+    //--------------------------------------------------------------------------
+    always_comb begin
+        // Default all write select signals to 0
+        cpuif_wr_sel = '{default: '0};
+
+        if (cpuif_req && cpuif_wr_en) begin
+            // A write request is pending
+            if ((cpuif_wr_addr < (6'h38))) begin
+                cpuif_wr_sel.pcie_dma_regs = 1'b1;
+            end
+            else begin
+                cpuif_wr_sel.cpuif_err = 1'b1;
+            end
+        end else begin
+            // No write request, all select signals remain 0
+        end
+    end
+
+    //--------------------------------------------------------------------------
+    // Read Address Decoder
+    //--------------------------------------------------------------------------
+    always_comb begin
+        // Default all read select signals to 0
+        cpuif_rd_sel = '{default: '0};
+
+        if (cpuif_req && cpuif_rd_en) begin
+            // A read request is pending
+            if ((cpuif_rd_addr < (6'h38))) begin
+                cpuif_rd_sel.pcie_dma_regs = 1'b1;
+            end
+            else begin
+                cpuif_rd_sel.cpuif_err = 1'b1;
+            end
+        end else begin
+            // No read request, all select signals remain 0
+        end
+    end
+endmodule

src/pcie/regs/pcie_top_regs_pkg.sv

@@ -0,0 +1,18 @@
+//==========================================================
+//  Package: pcie_top_regs_pkg
+//  Description: CPU Interface Bus Decoder Package
+//  Author: PeakRDL-BusDecoder
+//  License: LGPL-3.0
+//  Date: 2025-11-22
+//  Version: 0.5.0
+//  Links:
+//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
+//==========================================================
+
+
+package pcie_top_regs_pkg;
+    localparam PCIE_TOP_REGS_DATA_WIDTH = 32;
+    localparam PCIE_TOP_REGS_MIN_ADDR_WIDTH = 6;
+    localparam PCIE_TOP_REGS_SIZE = 'h38;
+    localparam PCIE_TOP_REGS_PCIE_DMA_REGS_ADDR_WIDTH = 6;
+endpackage

src/pcie/regs/verilator.vlt

@@ -0,0 +1,4 @@
+`verilator_config
+
+lint_off -rule MULTIDRIVEN -file "**/regs/*"
+lint_off -file "**/regs/*"

src/pcie/sources.list

@@ -0,0 +1,9 @@
+regs/verilator.vlt
+
+regs/pcie_dma_regs_pkg.sv
+regs/pcie_dma_regs.sv
+regs/pcie_top_regs_pkg.sv
+regs/pcie_top_regs.sv
+
+pcie_dma_wrapper.sv
+pcie_top.sv

src/regs/alibaba_pcie_top.rdl

@@ -0,0 +1,6 @@
+addrmap alibaba_pcie_top_regs {
+    name = "Alibaba PCIe Top";
+
+    external pcie_top_regs pcie_top_regs;
+    external eth_dma_wrapper_regs eth_dma_wrapper_regs;
+};

src/regs/alibaba_pcie_top_regs.h

@@ -0,0 +1,190 @@
+// Generated by PeakRDL-cheader - A free and open-source header generator
+//  https://github.com/SystemRDL/PeakRDL-cheader
+
+#ifndef ALIBABA_PCIE_TOP_REGS_H
+#define ALIBABA_PCIE_TOP_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <assert.h>
+
+// Reg - pcie_dma_regs::dma_rd::src_addr_low
+#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bm 0xffffffff
+#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bp 0
+#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bw 32
+#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_reset 0x0
+
+// Reg - pcie_dma_regs::dma_rd::src_addr_high
+#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bm 0xffffffff
+#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bp 0
+#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bw 32
+#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_reset 0x0
+
+// Reg - pcie_dma_regs::dma_rd::dst_addr
+#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bm 0xffff
+#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bp 0
+#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bw 16
+#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_reset 0x0
+
+// Reg - pcie_dma_regs::dma_rd::length
+#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bm 0xffff
+#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bp 0
+#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bw 16
+#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_reset 0x0
+
+// Reg - pcie_dma_regs::dma_rd::trigger
+#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bm 0x1
+#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bp 0
+#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bw 1
+#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_reset 0x0
+
+// Reg - pcie_dma_regs::dma_rd::done
+#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bm 0x1
+#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bp 0
+#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bw 1
+#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_reset 0x0
+
+// Regfile - pcie_dma_regs::dma_rd
+typedef struct __attribute__ ((__packed__)) {
+    uint32_t src_addr_low;
+    uint32_t src_addr_high;
+    uint32_t dst_addr;
+    uint32_t length;
+    uint32_t trigger;
+    uint32_t done;
+} pcie_dma_regs__dma_rd_t;
+
+// Reg - pcie_dma_regs::dma_wr::dst_addr_low
+#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bm 0xffffffff
+#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bp 0
+#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bw 32
+#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_reset 0x0
+
+// Reg - pcie_dma_regs::dma_wr::dst_addr_high
+#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bm 0xffffffff
+#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bp 0
+#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bw 32
+#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_reset 0x0
+
+// Reg - pcie_dma_regs::dma_wr::src_addr
+#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bm 0xffff
+#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bp 0
+#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bw 16
+#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_reset 0x0
+
+// Reg - pcie_dma_regs::dma_wr::length
+#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bm 0xffff
+#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bp 0
+#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bw 16
+#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_reset 0x0
+
+// Reg - pcie_dma_regs::dma_wr::trigger
+#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bm 0x1
+#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bp 0
+#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bw 1
+#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_reset 0x0
+
+// Reg - pcie_dma_regs::dma_wr::done
+#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bm 0x1
+#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bp 0
+#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bw 1
+#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_reset 0x0
+
+// Regfile - pcie_dma_regs::dma_wr
+typedef struct __attribute__ ((__packed__)) {
+    uint32_t dst_addr_low;
+    uint32_t dst_addr_high;
+    uint32_t src_addr;
+    uint32_t length;
+    uint32_t trigger;
+    uint32_t done;
+} pcie_dma_regs__dma_wr_t;
+
+// Addrmap - pcie_dma_regs
+typedef struct __attribute__ ((__packed__)) {
+    pcie_dma_regs__dma_rd_t dma_rd;
+    uint8_t RESERVED_18_1f[0x8];
+    pcie_dma_regs__dma_wr_t dma_wr;
+} pcie_dma_regs_t;
+
+// Addrmap - pcie_top_regs
+typedef struct __attribute__ ((__packed__)) {
+    pcie_dma_regs_t pcie_dma_regs;
+} pcie_top_regs_t;
+
+// Reg - eth_mac_25g_us_regs::common::xcvr_gtpowergood_out
+#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bm 0x1
+#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bp 0
+#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bw 1
+#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_reset 0x0
+
+// Reg - eth_mac_25g_us_regs::common::xcvr_qpll0lock_out
+#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bm 0x1
+#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bp 0
+#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bw 1
+#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_reset 0x0
+
+// Reg - eth_mac_25g_us_regs::common::xcvr_qpll1lock_out
+#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bm 0x1
+#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bp 0
+#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bw 1
+#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_reset 0x0
+
+// Regfile - eth_mac_25g_us_regs::common
+typedef struct __attribute__ ((__packed__)) {
+    uint32_t xcvr_gtpowergood_out;
+    uint32_t xcvr_qpll0lock_out;
+    uint32_t xcvr_qpll1lock_out;
+} eth_mac_25g_us_regs__common_t;
+
+// Reg - eth_mac_25g_us_regs::lane::rx_block_lock
+#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bm 0x1
+#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bp 0
+#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bw 1
+#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_reset 0x0
+
+// Reg - eth_mac_25g_us_regs::lane::rx_status
+#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bm 0x1
+#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bp 0
+#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bw 1
+#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_reset 0x0
+
+// Regfile - eth_mac_25g_us_regs::lane
+typedef struct __attribute__ ((__packed__)) {
+    uint32_t rx_block_lock;
+    uint32_t rx_status;
+    uint8_t RESERVED_8_1f[0x18];
+} eth_mac_25g_us_regs__lane__stride20_t;
+
+// Addrmap - eth_mac_25g_us_regs
+typedef struct __attribute__ ((__packed__)) {
+    eth_mac_25g_us_regs__common_t common;
+    uint8_t RESERVED_c_1f[0x14];
+    eth_mac_25g_us_regs__lane__stride20_t lanes[2];
+} eth_mac_25g_us_regs_t;
+
+// Addrmap - eth_dma_wrapper_regs
+typedef struct __attribute__ ((__packed__)) {
+    eth_mac_25g_us_regs_t eth_mac_25g_us_regs;
+    uint8_t RESERVED_60_7f[0x20];
+    pcie_dma_regs_t pcie_dma_regs;
+} eth_dma_wrapper_regs_t;
+
+// Addrmap - alibaba_pcie_top_regs
+typedef struct __attribute__ ((__packed__)) {
+    pcie_top_regs_t pcie_top_regs;
+    uint8_t RESERVED_38_ff[0xc8];
+    eth_dma_wrapper_regs_t eth_dma_wrapper_regs;
+} alibaba_pcie_top_regs_t;
+
+
+static_assert(sizeof(alibaba_pcie_top_regs_t) == 0x1b8, "Packing error");
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ALIBABA_PCIE_TOP_REGS_H */

src/regs/alibaba_pcie_top_regs.py

@@ -0,0 +1,165 @@
+class AddrNode():
+    addr: int
+class alibaba_pcie_top_regsClass(AddrNode):
+    class pcie_top_regsClass(AddrNode):
+        class pcie_dma_regsClass(AddrNode):
+            class dma_rdClass(AddrNode):
+                class src_addr_lowClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class src_addr_highClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class dst_addrClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class lengthClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class triggerClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class doneClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.src_addr_low = self.src_addr_lowClass(self.addr + 0)
+                    self.src_addr_high = self.src_addr_highClass(self.addr + 4)
+                    self.dst_addr = self.dst_addrClass(self.addr + 8)
+                    self.length = self.lengthClass(self.addr + 12)
+                    self.trigger = self.triggerClass(self.addr + 16)
+                    self.done = self.doneClass(self.addr + 20)
+            class dma_wrClass(AddrNode):
+                class dst_addr_lowClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class dst_addr_highClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class src_addrClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class lengthClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class triggerClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class doneClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.dst_addr_low = self.dst_addr_lowClass(self.addr + 0)
+                    self.dst_addr_high = self.dst_addr_highClass(self.addr + 4)
+                    self.src_addr = self.src_addrClass(self.addr + 8)
+                    self.length = self.lengthClass(self.addr + 12)
+                    self.trigger = self.triggerClass(self.addr + 16)
+                    self.done = self.doneClass(self.addr + 20)
+            def __init__(self, addr: int = 0):
+                self.addr = addr
+                self.dma_rd = self.dma_rdClass(self.addr + 0)
+                self.dma_wr = self.dma_wrClass(self.addr + 32)
+        def __init__(self, addr: int = 0):
+            self.addr = addr
+            self.pcie_dma_regs = self.pcie_dma_regsClass(self.addr + 0)
+    class eth_dma_wrapper_regsClass(AddrNode):
+        class eth_mac_25g_us_regsClass(AddrNode):
+            class commonClass(AddrNode):
+                class xcvr_gtpowergood_outClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class xcvr_qpll0lock_outClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class xcvr_qpll1lock_outClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.xcvr_gtpowergood_out = self.xcvr_gtpowergood_outClass(self.addr + 0)
+                    self.xcvr_qpll0lock_out = self.xcvr_qpll0lock_outClass(self.addr + 4)
+                    self.xcvr_qpll1lock_out = self.xcvr_qpll1lock_outClass(self.addr + 8)
+            class lanesClass(AddrNode):
+                class rx_block_lockClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class rx_statusClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.rx_block_lock = self.rx_block_lockClass(self.addr + 0)
+                    self.rx_status = self.rx_statusClass(self.addr + 4)
+            def __init__(self, addr: int = 0):
+                self.addr = addr
+                self.common = self.commonClass(self.addr + 0)
+                self.lanes = [self.lanesClass(self.addr + 32 + 8*i) for i in range(2)]
+        class pcie_dma_regsClass(AddrNode):
+            class dma_rdClass(AddrNode):
+                class src_addr_lowClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class src_addr_highClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class dst_addrClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class lengthClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class triggerClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class doneClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.src_addr_low = self.src_addr_lowClass(self.addr + 0)
+                    self.src_addr_high = self.src_addr_highClass(self.addr + 4)
+                    self.dst_addr = self.dst_addrClass(self.addr + 8)
+                    self.length = self.lengthClass(self.addr + 12)
+                    self.trigger = self.triggerClass(self.addr + 16)
+                    self.done = self.doneClass(self.addr + 20)
+            class dma_wrClass(AddrNode):
+                class dst_addr_lowClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class dst_addr_highClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class src_addrClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class lengthClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class triggerClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class doneClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.dst_addr_low = self.dst_addr_lowClass(self.addr + 0)
+                    self.dst_addr_high = self.dst_addr_highClass(self.addr + 4)
+                    self.src_addr = self.src_addrClass(self.addr + 8)
+                    self.length = self.lengthClass(self.addr + 12)
+                    self.trigger = self.triggerClass(self.addr + 16)
+                    self.done = self.doneClass(self.addr + 20)
+            def __init__(self, addr: int = 0):
+                self.addr = addr
+                self.dma_rd = self.dma_rdClass(self.addr + 0)
+                self.dma_wr = self.dma_wrClass(self.addr + 32)
+        def __init__(self, addr: int = 0):
+            self.addr = addr
+            self.eth_mac_25g_us_regs = self.eth_mac_25g_us_regsClass(self.addr + 0)
+            self.pcie_dma_regs = self.pcie_dma_regsClass(self.addr + 128)
+    def __init__(self, addr: int = 0):
+        self.addr = addr
+        self.pcie_top_regs = self.pcie_top_regsClass(self.addr + 0)
+        self.eth_dma_wrapper_regs = self.eth_dma_wrapper_regsClass(self.addr + 256)

src/regs/alibaba_pcie_top_regs.sv

@@ -0,0 +1,169 @@
+//==========================================================
+//  Module: alibaba_pcie_top_regs
+//  Description: CPU Interface Bus Decoder
+//  Author: PeakRDL-BusDecoder
+//  License: LGPL-3.0
+//  Date: 2025-11-23
+//  Version: 0.6.0
+//  Links:
+//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
+//==========================================================
+
+
+module alibaba_pcie_top_regs (
+    taxi_apb_if.slv s_apb,
+    taxi_apb_if.mst m_apb_pcie_top_regs,
+    taxi_apb_if.mst m_apb_eth_dma_wrapper_regs
+);
+    //--------------------------------------------------------------------------
+    // CPU Bus interface logic
+    //--------------------------------------------------------------------------
+    logic cpuif_req;
+    logic cpuif_wr_en;
+    logic cpuif_rd_en;
+    logic [8:0] cpuif_wr_addr;
+    logic [8:0] cpuif_rd_addr;
+
+    logic cpuif_wr_ack;
+    logic cpuif_wr_err;
+    logic [31:0] cpuif_wr_data;
+    logic [3:0] cpuif_wr_byte_en;
+
+    logic cpuif_rd_ack;
+    logic cpuif_rd_err;
+    logic [31:0] cpuif_rd_data;
+
+    //--------------------------------------------------------------------------
+    // Child instance signals
+    //--------------------------------------------------------------------------
+    typedef struct {
+        logic pcie_top_regs;
+        logic eth_dma_wrapper_regs;
+        logic cpuif_err;
+    } cpuif_sel_t;
+    cpuif_sel_t cpuif_wr_sel;
+    cpuif_sel_t cpuif_rd_sel;
+
+    //--------------------------------------------------------------------------
+    // Slave <-> Internal CPUIF <-> Master
+    //--------------------------------------------------------------------------
+    
+    `ifndef SYNTHESIS
+        initial begin
+            assert_bad_addr_width: assert($bits(s_apb.paddr) >= alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH)
+                else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH);
+            assert_bad_data_width: assert($bits(s_apb.pwdata) == alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH)
+                else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH);
+        end
+        `ifdef PEAKRDL_ASSERTIONS
+        assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
+            else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+        `endif
+    `endif
+
+    assign cpuif_req   = s_apb.psel;
+    assign cpuif_wr_en = s_apb.pwrite;
+    assign cpuif_rd_en = !s_apb.pwrite;
+
+    assign cpuif_wr_addr = s_apb.paddr;
+    assign cpuif_rd_addr = s_apb.paddr;
+
+    assign cpuif_wr_data = s_apb.pwdata;
+    assign cpuif_wr_byte_en = s_apb.pstrb;
+
+    assign s_apb.prdata = cpuif_rd_data;
+    assign s_apb.pready = cpuif_rd_ack;
+    assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+
+    //--------------------------------------------------------------------------
+    // Fanout CPU Bus interface signals
+    //--------------------------------------------------------------------------
+    assign m_apb_pcie_top_regs.psel = cpuif_wr_sel.pcie_top_regs|cpuif_rd_sel.pcie_top_regs;
+    assign m_apb_pcie_top_regs.penable = s_apb.penable;
+    assign m_apb_pcie_top_regs.pwrite = cpuif_wr_sel.pcie_top_regs;
+    assign m_apb_pcie_top_regs.paddr = s_apb.paddr;
+    assign m_apb_pcie_top_regs.pprot = s_apb.pprot;
+    assign m_apb_pcie_top_regs.pwdata = cpuif_wr_data;
+    assign m_apb_pcie_top_regs.pstrb = cpuif_wr_byte_en;
+    assign m_apb_eth_dma_wrapper_regs.psel = cpuif_wr_sel.eth_dma_wrapper_regs|cpuif_rd_sel.eth_dma_wrapper_regs;
+    assign m_apb_eth_dma_wrapper_regs.penable = s_apb.penable;
+    assign m_apb_eth_dma_wrapper_regs.pwrite = cpuif_wr_sel.eth_dma_wrapper_regs;
+    assign m_apb_eth_dma_wrapper_regs.paddr = s_apb.paddr;
+    assign m_apb_eth_dma_wrapper_regs.pprot = s_apb.pprot;
+    assign m_apb_eth_dma_wrapper_regs.pwdata = cpuif_wr_data;
+    assign m_apb_eth_dma_wrapper_regs.pstrb = cpuif_wr_byte_en;
+
+    //--------------------------------------------------------------------------
+    // Intermediate signals for interface array fanin
+    //--------------------------------------------------------------------------
+
+
+    //--------------------------------------------------------------------------
+    // Fanin CPU Bus interface signals
+    //--------------------------------------------------------------------------
+    always_comb begin
+        cpuif_rd_ack = '0;
+        cpuif_rd_err = '0;
+        cpuif_rd_data = '0;
+        if (cpuif_rd_sel.pcie_top_regs || cpuif_wr_sel.pcie_top_regs) begin
+            cpuif_rd_ack = m_apb_pcie_top_regs.pready;
+            cpuif_rd_err = m_apb_pcie_top_regs.pslverr;
+        end
+        if (cpuif_rd_sel.pcie_top_regs) begin
+            cpuif_rd_data = m_apb_pcie_top_regs.prdata;
+        end
+        if (cpuif_rd_sel.eth_dma_wrapper_regs || cpuif_wr_sel.eth_dma_wrapper_regs) begin
+            cpuif_rd_ack = m_apb_eth_dma_wrapper_regs.pready;
+            cpuif_rd_err = m_apb_eth_dma_wrapper_regs.pslverr;
+        end
+        if (cpuif_rd_sel.eth_dma_wrapper_regs) begin
+            cpuif_rd_data = m_apb_eth_dma_wrapper_regs.prdata;
+        end
+    end
+
+    //--------------------------------------------------------------------------
+    // Write Address Decoder
+    //--------------------------------------------------------------------------
+    always_comb begin
+        // Default all write select signals to 0
+        cpuif_wr_sel = '{default: '0};
+
+        if (cpuif_req && cpuif_wr_en) begin
+            // A write request is pending
+            if ((cpuif_wr_addr < (9'h38))) begin
+                cpuif_wr_sel.pcie_top_regs = 1'b1;
+            end
+            else if ((cpuif_wr_addr >= (9'h100)) && (cpuif_wr_addr < (9'h1b8))) begin
+                cpuif_wr_sel.eth_dma_wrapper_regs = 1'b1;
+            end
+            else begin
+                cpuif_wr_sel.cpuif_err = 1'b1;
+            end
+        end else begin
+            // No write request, all select signals remain 0
+        end
+    end
+
+    //--------------------------------------------------------------------------
+    // Read Address Decoder
+    //--------------------------------------------------------------------------
+    always_comb begin
+        // Default all read select signals to 0
+        cpuif_rd_sel = '{default: '0};
+
+        if (cpuif_req && cpuif_rd_en) begin
+            // A read request is pending
+            if ((cpuif_rd_addr < (9'h38))) begin
+                cpuif_rd_sel.pcie_top_regs = 1'b1;
+            end
+            else if ((cpuif_rd_addr >= (9'h100)) && (cpuif_rd_addr < (9'h1b8))) begin
+                cpuif_rd_sel.eth_dma_wrapper_regs = 1'b1;
+            end
+            else begin
+                cpuif_rd_sel.cpuif_err = 1'b1;
+            end
+        end else begin
+            // No read request, all select signals remain 0
+        end
+    end
+endmodule

src/regs/alibaba_pcie_top_regs_pkg.sv

@@ -0,0 +1,19 @@
+//==========================================================
+//  Package: alibaba_pcie_top_regs_pkg
+//  Description: CPU Interface Bus Decoder Package
+//  Author: PeakRDL-BusDecoder
+//  License: LGPL-3.0
+//  Date: 2025-11-23
+//  Version: 0.6.0
+//  Links:
+//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
+//==========================================================
+
+
+package alibaba_pcie_top_regs_pkg;
+    localparam ALIBABA_PCIE_TOP_REGS_DATA_WIDTH = 32;
+    localparam ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH = 9;
+    localparam ALIBABA_PCIE_TOP_REGS_SIZE = 'h1b8;
+    localparam ALIBABA_PCIE_TOP_REGS_PCIE_TOP_REGS_ADDR_WIDTH = 6;
+    localparam ALIBABA_PCIE_TOP_REGS_ETH_DMA_WRAPPER_REGS_ADDR_WIDTH = 8;
+endpackage

src/regs/compile_regs.sh

@@ -1 +1,6 @@
-peakrdl regblock -t pcie_dma_regs pcie_dma_regs.rdl -o . --cpuif apb4-flat
+SRCS="../pcie/regs/pcie_dma_regs.rdl ../pcie/regs/pcie_top_regs.rdl ../eth/regs/eth_mac_25g_us_regs.rdl ../eth/regs/eth_dma_wrapper_regs.rdl alibaba_pcie_top.rdl"
+
+peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif taxi-apb
+peakrdl python-regmap -t alibaba_pcie_top_regs $SRCS -o alibaba_pcie_top_regs.py
+peakrdl html -t alibaba_pcie_top_regs $SRCS -o html
+peakrdl c-header -t alibaba_pcie_top_regs $SRCS -o alibaba_pcie_top_regs.h

sw/test/alibaba_pcie_top_regs.h

@@ -0,0 +1 @@
+../../src/regs/alibaba_pcie_top_regs.h

sw/test/pcie_dma_test.c

@@ -7,6 +7,8 @@
 #include <sys/mman.h>
 #include <string.h>
 
+#include "alibaba_pcie_top_regs.h"
+
 typedef struct {
     uint64_t pfn : 55;
     unsigned int soft_dirty : 1;
@@ -105,8 +107,8 @@ int main(void)
     // this is hardcoded, seems to be deterministic.
     uint32_t pcie_physical_base_offset = 0xfe800000;
     int fd = open("/dev/mem", O_RDWR|O_SYNC);
-    uint32_t* pcie_base = (uint32_t*)mmap(0, 64, PROT_READ|PROT_WRITE, MAP_SHARED, fd, pcie_physical_base_offset);
+    alibaba_pcie_top_regs_t* top_regs = (alibaba_pcie_top_regs_t*)mmap(0, 64, PROT_READ|PROT_WRITE, MAP_SHARED, fd, pcie_physical_base_offset);
-    printf("Virtual PCIe Base: %p\n", pcie_base);
+    printf("Virtual PCIe Base: %p\n", top_regs);
 
 
     for (int i = 0; i < 2; i++) { 
@@ -119,34 +121,60 @@ int main(void)
         memset((void*)dst, 0, 1024);
 
         printf("Sending read DMA\n");
-        pcie_base[0] = (uint32_t)src_phys;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.src_addr_low = (uint32_t)src_phys;
-        pcie_base[1] = (uint32_t)(src_phys >> 32);
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.src_addr_high = (uint32_t)(src_phys >> 32);
-        pcie_base[2] = dma_mem_addr;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.dst_addr = dma_mem_addr;
-        pcie_base[3] = strlen(src);
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.length = strlen(src);
 
         for (int i = 0; i < 4; i++) {
-            printf("pcie_base[%d] = %x\n", i, pcie_base[i]);
+            printf("pcie_rd_dma[%d] = %x\n", i, (&top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.src_addr_low)[i]);
         }
 
-        pcie_base[4] = 1;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.trigger = 1;
-        printf("%d\n", pcie_base[4]);
+        printf("%d\n", top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.trigger);
         printf("\n\n");
 
         printf("Sending write DMA\n");
 
+        // we use dma_mem_addr twice, but these are actually 2 separate memories.
 
-        printf("Sending read DMA\n");
+        // Set up stream to memory DMA to store ethernet frame
-        pcie_base[8] = (uint32_t)dst_phys;
+        printf("Setting up stream to memory DMA\n");
-        pcie_base[9] = (uint32_t)(dst_phys >> 32);
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.src_addr = 0;
-        pcie_base[10] = dma_mem_addr;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.dst_addr_low = dma_mem_addr;
-        pcie_base[11] = strlen(src);
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.dst_addr_high =  0;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.length = strlen(src);
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.trigger = 1;
 
-        for (int i = 8; i < 12; i++) {
+        for (int i = 0; i < 4; i++) {
-            printf("pcie_base[%d] = %x\n", i, pcie_base[i]);
+            printf("eth_wr_dma[%d] = %x\n", i, (&top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.dst_addr_low )[i]);
         }
 
-        pcie_base[12] = 1;
+        // Trigger memory to stream dma to send ethernet frame
-        printf("%d\n", pcie_base[12]);
+        printf("Sending memory to stream DMA\n");
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.src_addr_low = dma_mem_addr;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.src_addr_high = 0;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.dst_addr = 0;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.length = strlen(src);
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.trigger = 1;
+
+        for (int i = 0; i < 4; i++) {
+            printf("eth_rd_dma[%d] = %x\n", i, (&top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.src_addr_low)[i]);
+        }
+
+
+        printf("Sending read DMA\n");
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.dst_addr_low = (uint32_t)dst_phys;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.dst_addr_high = (uint32_t)(dst_phys >> 32);
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.src_addr = dma_mem_addr;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.length = strlen(src);
+
+        for (int i = 8; i < 12; i++) {
+            printf("pcie_wr_dma[%d] = %x\n", i, (&top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.dst_addr_low)[i]);
+        }
+
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.trigger = 1;
+        printf("%d\n", top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.trigger);
         printf("\n\n");
 
         printf("strlen(dst)=%d\n", strlen(dst));