Filter out only verilog sources (and verilator lint files)

pyproject.toml

@@ -35,7 +35,7 @@ name = "fpga-sim"  # REQUIRED, is the only field that cannot be marked as dynami
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.3.0"  # REQUIRED, although can be dynamic
+version = "0.3.1"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:

src/fpga_sim/fpga_sim.py

@@ -95,8 +95,11 @@ def fpga_sim_main():
 
         sources, incdirs = rtl_manifest.parse(f"{test['base_path']}/{test['sources']}")
 
+        verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv") or s.endswith(".vlt")), sources))
+
+
         runner.build(
-            verilog_sources=sources,
+            verilog_sources=verilog_sources,
             includes=incdirs,
             hdl_toplevel=test["toplevel"],
             build_dir=f"{test['base_path']}/sim_build",