bslathi19/fpga-sim
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Byron Lathi 443a99e477 Filter out only verilog sources (and verilator lint files)
2025-03-29 19:39:35 -07:00
src/fpga_sim
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.gitignore
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2024-11-29 22:31:03 -08:00
.gitlab-ci.yml
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init_env.sh
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LICENSE.txt
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pyproject.toml
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README.md
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requirements.txt
Experimental/incdirs
2025-03-21 05:45:28 +00:00

README.md

FPGA Sim

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Description
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Readme 107 KiB
Languages
Python 98%
Shell 2%