Filter out only verilog sources (and verilator lint files)

Fix quotes for old python compatibility

See merge request bslathi19/fpga-sim!2

pyproject.toml

@@ -35,7 +35,7 @@ name = "fpga-sim"  # REQUIRED, is the only field that cannot be marked as dynami
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.2.1"  # REQUIRED, although can be dynamic
+version = "0.3.1"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:
@@ -123,7 +123,7 @@ classifiers = [
 dependencies = [
   "pyyaml",
   "cocotb",
-  "rtl-manifest"
+  "rtl-manifest>=0.3.1"
 ]
 
 # List additional groups of dependencies here (e.g. development

requirements.txt

@@ -1,4 +1,8 @@
+-i https://git.byronlathi.com/api/v4/projects/95/packages/pypi/simple
 setuptools
 wheel
 build
 twine
+cocotb
+rtl-manifest
+pyyaml

src/fpga_sim/fpga_sim.py

@@ -1,5 +1,3 @@
-from ast import parse
-from email.mime import base
 import os
 import sys
 
@@ -22,6 +20,7 @@ def fpga_sim_main():
 
     parser.add_argument("yaml")
     parser.add_argument("test_name", nargs="?")
+    parser.add_argument("-j", "--jobs", default=1)
 
     args = parser.parse_args()
 
@@ -78,7 +77,9 @@ def fpga_sim_main():
     sim = os.getenv("SIM", "verilator")
     runner = get_runner(sim)
 
-    os.environ["MAKEFLAGS"] = "-j"
+    jobs = args.jobs
+    print(jobs)
+    os.environ["MAKEFLAGS"] = f"-j{jobs}"
 
     tests_to_run = []
 
@@ -92,10 +93,14 @@ def fpga_sim_main():
     # Turn this into a multiprocessing pool
     for test in tests_to_run:
 
-        sources = rtl_manifest.read_sources(f"{test['base_path']}/{test['sources']}")
+        sources, incdirs = rtl_manifest.parse(f"{test['base_path']}/{test['sources']}")
+
+        verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv") or s.endswith(".vlt")), sources))
+
 
         runner.build(
-            verilog_sources=sources,
+            verilog_sources=verilog_sources,
+            includes=incdirs,
             hdl_toplevel=test["toplevel"],
             build_dir=f"{test['base_path']}/sim_build",
             waves=test["waves"],
@@ -107,3 +112,4 @@ def fpga_sim_main():
         sys.path.append(test["base_path"])
 
         runner.test(hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)
+