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fpga-sim
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Byron Lathi
bc49915ba0
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Add back FST (use verilator 5.036 or greater)
2026-02-11 21:25:30 -08:00
.gitea
/workflows
Add actions
2025-11-08 14:33:28 -08:00
src
/fpga_sim
Add back FST (use verilator 5.036 or greater)
2026-02-11 21:25:30 -08:00
.gitignore
Initial commit
2024-11-29 22:31:03 -08:00
.gitlab-ci.yml
Initial commit
2024-11-29 22:31:03 -08:00
init_env.sh
Initial commit
2024-11-29 22:31:03 -08:00
LICENSE.txt
Initial commit
2024-11-29 22:31:03 -08:00
pyproject.toml
Add back FST (use verilator 5.036 or greater)
2026-02-11 21:25:30 -08:00
README.md
Initial commit
2024-11-29 22:31:03 -08:00
requirements.txt
Experimental/incdirs
2025-03-21 05:45:28 +00:00
README.md
FPGA Sim
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Python
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Shell
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