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Add back FST (use verilator 5.036 or greater)
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.gitea/workflows
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src/fpga_sim
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.gitignore
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.gitlab-ci.yml
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init_env.sh
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LICENSE.txt
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pyproject.toml
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README.md
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requirements.txt
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README.md

FPGA Sim

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Description
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Readme 116 KiB
Languages
Python 98%
Shell 2%