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Grand refactor

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This commit is contained in:
Byron Lathi
2026-04-18 19:19:55 -07:00
parent ef6b5f0669
commit 470bbc39ec
162 changed files with 483 additions and 335580 deletions
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fpga/ip/EfxSapphireHpSoc_slb/.gitignore vendored Normal file
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*
!.gitignore
!settings.json

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fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v
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fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh
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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.272
// IP Version: 1.22.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam PERI_FREQ = 200;

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fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v
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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.272
// IP Version: 1.22.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
EfxSapphireHpSoc_slb u_EfxSapphireHpSoc_slb
(
.io_peripheralClk ( io_peripheralClk ),
.io_peripheralReset ( io_peripheralReset ),
.io_asyncReset ( io_asyncReset ),
.io_gpio_sw_n ( io_gpio_sw_n ),
.pll_peripheral_locked ( pll_peripheral_locked ),
.pll_system_locked ( pll_system_locked ),
.jtagCtrl_capture ( jtagCtrl_capture ),
.jtagCtrl_enable ( jtagCtrl_enable ),
.jtagCtrl_reset ( jtagCtrl_reset ),
.jtagCtrl_shift ( jtagCtrl_shift ),
.jtagCtrl_tdi ( jtagCtrl_tdi ),
.jtagCtrl_tdo ( jtagCtrl_tdo ),
.jtagCtrl_update ( jtagCtrl_update ),
.ut_jtagCtrl_capture ( ut_jtagCtrl_capture ),
.ut_jtagCtrl_enable ( ut_jtagCtrl_enable ),
.ut_jtagCtrl_reset ( ut_jtagCtrl_reset ),
.ut_jtagCtrl_shift ( ut_jtagCtrl_shift ),
.ut_jtagCtrl_tdi ( ut_jtagCtrl_tdi ),
.ut_jtagCtrl_tdo ( ut_jtagCtrl_tdo ),
.ut_jtagCtrl_update ( ut_jtagCtrl_update ),
.system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ),
.system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ),
.system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ),
.system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ),
.system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ),
.system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ),
.system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ),
.system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ),
.system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ),
.system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ),
.system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ),
.system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ),
.system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ),
.system_spi_0_io_ss ( system_spi_0_io_ss ),
.system_uart_0_io_rxd ( system_uart_0_io_rxd ),
.system_uart_0_io_txd ( system_uart_0_io_txd ),
.system_i2c_0_io_scl_read ( system_i2c_0_io_scl_read ),
.system_i2c_0_io_scl_write ( system_i2c_0_io_scl_write ),
.system_i2c_0_io_sda_read ( system_i2c_0_io_sda_read ),
.system_gpio_0_io_read ( system_gpio_0_io_read ),
.system_gpio_0_io_write ( system_gpio_0_io_write ),
.system_gpio_0_io_writeEnable ( system_gpio_0_io_writeEnable ),
.cfg_done ( cfg_done ),
.cfg_start ( cfg_start ),
.cfg_sel ( cfg_sel ),
.cfg_reset ( cfg_reset ),
.axiAInterrupt ( axiAInterrupt ),
.axiA_awaddr ( axiA_awaddr ),
.axiA_awlen ( axiA_awlen ),
.axiA_awsize ( axiA_awsize ),
.axiA_awburst ( axiA_awburst ),
.axiA_awlock ( axiA_awlock ),
.axiA_awcache ( axiA_awcache ),
.axiA_awprot ( axiA_awprot ),
.axiA_awqos ( axiA_awqos ),
.axiA_awregion ( axiA_awregion ),
.axiA_awvalid ( axiA_awvalid ),
.axiA_awready ( axiA_awready ),
.axiA_wdata ( axiA_wdata ),
.axiA_wstrb ( axiA_wstrb ),
.axiA_wvalid ( axiA_wvalid ),
.axiA_wlast ( axiA_wlast ),
.axiA_wready ( axiA_wready ),
.axiA_bresp ( axiA_bresp ),
.axiA_bvalid ( axiA_bvalid ),
.axiA_bready ( axiA_bready ),
.axiA_araddr ( axiA_araddr ),
.axiA_arlen ( axiA_arlen ),
.axiA_arsize ( axiA_arsize ),
.axiA_arburst ( axiA_arburst ),
.axiA_arlock ( axiA_arlock ),
.axiA_arcache ( axiA_arcache ),
.axiA_arprot ( axiA_arprot ),
.axiA_arqos ( axiA_arqos ),
.axiA_arregion ( axiA_arregion ),
.axiA_arvalid ( axiA_arvalid ),
.axiA_arready ( axiA_arready ),
.axiA_rdata ( axiA_rdata ),
.axiA_rresp ( axiA_rresp ),
.axiA_rlast ( axiA_rlast ),
.axiA_rvalid ( axiA_rvalid ),
.axiA_rready ( axiA_rready ),
.userInterruptA ( userInterruptA ),
.userInterruptB ( userInterruptB ),
.userInterruptC ( userInterruptC ),
.userInterruptD ( userInterruptD ),
.userInterruptE ( userInterruptE ),
.userInterruptF ( userInterruptF ),
.io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ),
.io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ),
.io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ),
.io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ),
.io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ),
.io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ),
.io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ),
.io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ),
.system_i2c_0_io_sda_write ( system_i2c_0_io_sda_write ),
.system_i2c_0_io_sda_writeEnable ( system_i2c_0_io_sda_writeEnable ),
.system_i2c_0_io_scl_writeEnable ( system_i2c_0_io_scl_writeEnable ),
.system_watchdog_hardPanic_reset ( system_watchdog_hardPanic_reset )
);

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fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd
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--------------------------------------------------------------------------------
-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
component EfxSapphireHpSoc_slb is
port (
io_peripheralClk : in std_logic;
io_peripheralReset : in std_logic;
io_asyncReset : out std_logic;
io_gpio_sw_n : in std_logic;
pll_peripheral_locked : in std_logic;
pll_system_locked : in std_logic;
jtagCtrl_capture : out std_logic;
jtagCtrl_enable : out std_logic;
jtagCtrl_reset : out std_logic;
jtagCtrl_shift : out std_logic;
jtagCtrl_tdi : out std_logic;
jtagCtrl_tdo : in std_logic;
jtagCtrl_update : out std_logic;
ut_jtagCtrl_capture : in std_logic;
ut_jtagCtrl_enable : in std_logic;
ut_jtagCtrl_reset : in std_logic;
ut_jtagCtrl_shift : in std_logic;
ut_jtagCtrl_tdi : in std_logic;
ut_jtagCtrl_tdo : out std_logic;
ut_jtagCtrl_update : in std_logic;
system_spi_0_io_data_0_read : in std_logic;
system_spi_0_io_data_0_write : out std_logic;
system_spi_0_io_data_0_writeEnable : out std_logic;
system_spi_0_io_data_1_read : in std_logic;
system_spi_0_io_data_1_write : out std_logic;
system_spi_0_io_data_1_writeEnable : out std_logic;
system_spi_0_io_data_2_read : in std_logic;
system_spi_0_io_data_2_write : out std_logic;
system_spi_0_io_data_2_writeEnable : out std_logic;
system_spi_0_io_data_3_read : in std_logic;
system_spi_0_io_data_3_write : out std_logic;
system_spi_0_io_data_3_writeEnable : out std_logic;
system_spi_0_io_sclk_write : out std_logic;
system_spi_0_io_ss : out std_logic_vector(3 downto 0);
system_uart_0_io_rxd : in std_logic;
system_uart_0_io_txd : out std_logic;
system_i2c_0_io_scl_read : in std_logic;
system_i2c_0_io_scl_write : out std_logic;
system_i2c_0_io_sda_read : in std_logic;
system_gpio_0_io_read : in std_logic_vector(3 downto 0);
system_gpio_0_io_write : out std_logic_vector(3 downto 0);
system_gpio_0_io_writeEnable : out std_logic_vector(3 downto 0);
cfg_done : in std_logic;
cfg_start : out std_logic;
cfg_sel : out std_logic;
cfg_reset : out std_logic;
axiAInterrupt : out std_logic;
axiA_awaddr : in std_logic_vector(31 downto 0);
axiA_awlen : in std_logic_vector(7 downto 0);
axiA_awsize : in std_logic_vector(2 downto 0);
axiA_awburst : in std_logic_vector(1 downto 0);
axiA_awlock : in std_logic;
axiA_awcache : in std_logic_vector(3 downto 0);
axiA_awprot : in std_logic_vector(2 downto 0);
axiA_awqos : in std_logic_vector(3 downto 0);
axiA_awregion : in std_logic_vector(3 downto 0);
axiA_awvalid : in std_logic;
axiA_awready : out std_logic;
axiA_wdata : in std_logic_vector(31 downto 0);
axiA_wstrb : in std_logic_vector(3 downto 0);
axiA_wvalid : in std_logic;
axiA_wlast : in std_logic;
axiA_wready : out std_logic;
axiA_bresp : out std_logic_vector(1 downto 0);
axiA_bvalid : out std_logic;
axiA_bready : in std_logic;
axiA_araddr : in std_logic_vector(31 downto 0);
axiA_arlen : in std_logic_vector(7 downto 0);
axiA_arsize : in std_logic_vector(2 downto 0);
axiA_arburst : in std_logic_vector(1 downto 0);
axiA_arlock : in std_logic;
axiA_arcache : in std_logic_vector(3 downto 0);
axiA_arprot : in std_logic_vector(2 downto 0);
axiA_arqos : in std_logic_vector(3 downto 0);
axiA_arregion : in std_logic_vector(3 downto 0);
axiA_arvalid : in std_logic;
axiA_arready : out std_logic;
axiA_rdata : out std_logic_vector(31 downto 0);
axiA_rresp : out std_logic_vector(1 downto 0);
axiA_rlast : out std_logic;
axiA_rvalid : out std_logic;
axiA_rready : in std_logic;
userInterruptA : out std_logic;
userInterruptB : out std_logic;
userInterruptC : out std_logic;
userInterruptD : out std_logic;
userInterruptE : out std_logic;
userInterruptF : out std_logic;
io_apbSlave_0_PADDR : out std_logic_vector(31 downto 0);
io_apbSlave_0_PENABLE : out std_logic;
io_apbSlave_0_PRDATA : in std_logic_vector(31 downto 0);
io_apbSlave_0_PREADY : in std_logic;
io_apbSlave_0_PSEL : out std_logic;
io_apbSlave_0_PSLVERROR : in std_logic;
io_apbSlave_0_PWDATA : out std_logic_vector(31 downto 0);
io_apbSlave_0_PWRITE : out std_logic;
system_i2c_0_io_sda_write : out std_logic;
system_i2c_0_io_sda_writeEnable : out std_logic;
system_i2c_0_io_scl_writeEnable : out std_logic;
system_watchdog_hardPanic_reset : out std_logic
);
end component EfxSapphireHpSoc_slb;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_EfxSapphireHpSoc_slb : EfxSapphireHpSoc_slb
port map (
io_peripheralClk => io_peripheralClk,
io_peripheralReset => io_peripheralReset,
io_asyncReset => io_asyncReset,
io_gpio_sw_n => io_gpio_sw_n,
pll_peripheral_locked => pll_peripheral_locked,
pll_system_locked => pll_system_locked,
jtagCtrl_capture => jtagCtrl_capture,
jtagCtrl_enable => jtagCtrl_enable,
jtagCtrl_reset => jtagCtrl_reset,
jtagCtrl_shift => jtagCtrl_shift,
jtagCtrl_tdi => jtagCtrl_tdi,
jtagCtrl_tdo => jtagCtrl_tdo,
jtagCtrl_update => jtagCtrl_update,
ut_jtagCtrl_capture => ut_jtagCtrl_capture,
ut_jtagCtrl_enable => ut_jtagCtrl_enable,
ut_jtagCtrl_reset => ut_jtagCtrl_reset,
ut_jtagCtrl_shift => ut_jtagCtrl_shift,
ut_jtagCtrl_tdi => ut_jtagCtrl_tdi,
ut_jtagCtrl_tdo => ut_jtagCtrl_tdo,
ut_jtagCtrl_update => ut_jtagCtrl_update,
system_spi_0_io_data_0_read => system_spi_0_io_data_0_read,
system_spi_0_io_data_0_write => system_spi_0_io_data_0_write,
system_spi_0_io_data_0_writeEnable => system_spi_0_io_data_0_writeEnable,
system_spi_0_io_data_1_read => system_spi_0_io_data_1_read,
system_spi_0_io_data_1_write => system_spi_0_io_data_1_write,
system_spi_0_io_data_1_writeEnable => system_spi_0_io_data_1_writeEnable,
system_spi_0_io_data_2_read => system_spi_0_io_data_2_read,
system_spi_0_io_data_2_write => system_spi_0_io_data_2_write,
system_spi_0_io_data_2_writeEnable => system_spi_0_io_data_2_writeEnable,
system_spi_0_io_data_3_read => system_spi_0_io_data_3_read,
system_spi_0_io_data_3_write => system_spi_0_io_data_3_write,
system_spi_0_io_data_3_writeEnable => system_spi_0_io_data_3_writeEnable,
system_spi_0_io_sclk_write => system_spi_0_io_sclk_write,
system_spi_0_io_ss => system_spi_0_io_ss,
system_uart_0_io_rxd => system_uart_0_io_rxd,
system_uart_0_io_txd => system_uart_0_io_txd,
system_i2c_0_io_scl_read => system_i2c_0_io_scl_read,
system_i2c_0_io_scl_write => system_i2c_0_io_scl_write,
system_i2c_0_io_sda_read => system_i2c_0_io_sda_read,
system_gpio_0_io_read => system_gpio_0_io_read,
system_gpio_0_io_write => system_gpio_0_io_write,
system_gpio_0_io_writeEnable => system_gpio_0_io_writeEnable,
cfg_done => cfg_done,
cfg_start => cfg_start,
cfg_sel => cfg_sel,
cfg_reset => cfg_reset,
axiAInterrupt => axiAInterrupt,
axiA_awaddr => axiA_awaddr,
axiA_awlen => axiA_awlen,
axiA_awsize => axiA_awsize,
axiA_awburst => axiA_awburst,
axiA_awlock => axiA_awlock,
axiA_awcache => axiA_awcache,
axiA_awprot => axiA_awprot,
axiA_awqos => axiA_awqos,
axiA_awregion => axiA_awregion,
axiA_awvalid => axiA_awvalid,
axiA_awready => axiA_awready,
axiA_wdata => axiA_wdata,
axiA_wstrb => axiA_wstrb,
axiA_wvalid => axiA_wvalid,
axiA_wlast => axiA_wlast,
axiA_wready => axiA_wready,
axiA_bresp => axiA_bresp,
axiA_bvalid => axiA_bvalid,
axiA_bready => axiA_bready,
axiA_araddr => axiA_araddr,
axiA_arlen => axiA_arlen,
axiA_arsize => axiA_arsize,
axiA_arburst => axiA_arburst,
axiA_arlock => axiA_arlock,
axiA_arcache => axiA_arcache,
axiA_arprot => axiA_arprot,
axiA_arqos => axiA_arqos,
axiA_arregion => axiA_arregion,
axiA_arvalid => axiA_arvalid,
axiA_arready => axiA_arready,
axiA_rdata => axiA_rdata,
axiA_rresp => axiA_rresp,
axiA_rlast => axiA_rlast,
axiA_rvalid => axiA_rvalid,
axiA_rready => axiA_rready,
userInterruptA => userInterruptA,
userInterruptB => userInterruptB,
userInterruptC => userInterruptC,
userInterruptD => userInterruptD,
userInterruptE => userInterruptE,
userInterruptF => userInterruptF,
io_apbSlave_0_PADDR => io_apbSlave_0_PADDR,
io_apbSlave_0_PENABLE => io_apbSlave_0_PENABLE,
io_apbSlave_0_PRDATA => io_apbSlave_0_PRDATA,
io_apbSlave_0_PREADY => io_apbSlave_0_PREADY,
io_apbSlave_0_PSEL => io_apbSlave_0_PSEL,
io_apbSlave_0_PSLVERROR => io_apbSlave_0_PSLVERROR,
io_apbSlave_0_PWDATA => io_apbSlave_0_PWDATA,
io_apbSlave_0_PWRITE => io_apbSlave_0_PWRITE,
system_i2c_0_io_sda_write => system_i2c_0_io_sda_write,
system_i2c_0_io_sda_writeEnable => system_i2c_0_io_sda_writeEnable,
system_i2c_0_io_scl_writeEnable => system_i2c_0_io_scl_writeEnable,
system_watchdog_hardPanic_reset => system_watchdog_hardPanic_reset
);
------------------------ End INSTANTIATION Template ---------

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fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_wrapper.v
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module EfxSapphireHpSoc_wrapper (
input cpu0_customInstruction_cmd_valid,
output cpu0_customInstruction_cmd_ready,
input [9:0] cpu0_customInstruction_function_id,
input [31:0] cpu0_customInstruction_inputs_0,
input [31:0] cpu0_customInstruction_inputs_1,
output cpu0_customInstruction_rsp_valid,
input cpu0_customInstruction_rsp_ready,
output [31:0] cpu0_customInstruction_outputs_0,
output userInterruptB,
output userInterruptE,
input cpu2_customInstruction_cmd_valid,
output cpu2_customInstruction_cmd_ready,
input [9:0] cpu2_customInstruction_function_id,
input [31:0] cpu2_customInstruction_inputs_0,
input [31:0] cpu2_customInstruction_inputs_1,
output cpu2_customInstruction_rsp_valid,
input cpu2_customInstruction_rsp_ready,
output [31:0] cpu2_customInstruction_outputs_0,
input io_cfuClk,
input io_cfuReset,
output system_spi_0_io_sclk_write,
output system_spi_0_io_data_0_writeEnable,
input system_spi_0_io_data_0_read,
output system_spi_0_io_data_0_write,
output system_spi_0_io_data_1_writeEnable,
input system_spi_0_io_data_1_read,
output system_spi_0_io_data_1_write,
output system_spi_0_io_data_2_writeEnable,
input system_spi_0_io_data_2_read,
output system_spi_0_io_data_2_write,
output system_spi_0_io_data_3_writeEnable,
input system_spi_0_io_data_3_read,
output system_spi_0_io_data_3_write,
output [3:0] system_spi_0_io_ss,
output userInterruptC,
output userInterruptH,
input cpu1_customInstruction_cmd_valid,
output cpu1_customInstruction_cmd_ready,
input [9:0] cpu1_customInstruction_function_id,
input [31:0] cpu1_customInstruction_inputs_0,
input [31:0] cpu1_customInstruction_inputs_1,
output cpu1_customInstruction_rsp_valid,
input cpu1_customInstruction_rsp_ready,
output [31:0] cpu1_customInstruction_outputs_0,
output jtagCtrl_tdi,
input jtagCtrl_tdo,
output jtagCtrl_enable,
output jtagCtrl_capture,
output jtagCtrl_shift,
output jtagCtrl_update,
output jtagCtrl_reset,
input ut_jtagCtrl_tdi,
output ut_jtagCtrl_tdo,
input ut_jtagCtrl_enable,
input ut_jtagCtrl_capture,
input ut_jtagCtrl_shift,
input ut_jtagCtrl_update,
input ut_jtagCtrl_reset,
output system_uart_0_io_txd,
input system_uart_0_io_rxd,
output io_ddrMasters_0_aw_valid,
input io_ddrMasters_0_aw_ready,
output [31:0] io_ddrMasters_0_aw_payload_addr,
output [3:0] io_ddrMasters_0_aw_payload_id,
output [3:0] io_ddrMasters_0_aw_payload_region,
output [7:0] io_ddrMasters_0_aw_payload_len,
output [2:0] io_ddrMasters_0_aw_payload_size,
output [1:0] io_ddrMasters_0_aw_payload_burst,
output io_ddrMasters_0_aw_payload_lock,
output [3:0] io_ddrMasters_0_aw_payload_cache,
output [3:0] io_ddrMasters_0_aw_payload_qos,
output [2:0] io_ddrMasters_0_aw_payload_prot,
output io_ddrMasters_0_aw_payload_allStrb,
output io_ddrMasters_0_w_valid,
input io_ddrMasters_0_w_ready,
output [127:0] io_ddrMasters_0_w_payload_data,
output [15:0] io_ddrMasters_0_w_payload_strb,
output io_ddrMasters_0_w_payload_last,
input io_ddrMasters_0_b_valid,
output io_ddrMasters_0_b_ready,
input [3:0] io_ddrMasters_0_b_payload_id,
input [1:0] io_ddrMasters_0_b_payload_resp,
output io_ddrMasters_0_ar_valid,
input io_ddrMasters_0_ar_ready,
output [31:0] io_ddrMasters_0_ar_payload_addr,
output [3:0] io_ddrMasters_0_ar_payload_id,
output [3:0] io_ddrMasters_0_ar_payload_region,
output [7:0] io_ddrMasters_0_ar_payload_len,
output [2:0] io_ddrMasters_0_ar_payload_size,
output [1:0] io_ddrMasters_0_ar_payload_burst,
output io_ddrMasters_0_ar_payload_lock,
output [3:0] io_ddrMasters_0_ar_payload_cache,
output [3:0] io_ddrMasters_0_ar_payload_qos,
output [2:0] io_ddrMasters_0_ar_payload_prot,
input io_ddrMasters_0_r_valid,
output io_ddrMasters_0_r_ready,
input [127:0] io_ddrMasters_0_r_payload_data,
input [3:0] io_ddrMasters_0_r_payload_id,
input [1:0] io_ddrMasters_0_r_payload_resp,
input io_ddrMasters_0_r_payload_last,
input io_ddrMasters_0_clk,
input io_ddrMasters_0_reset,
output userInterruptF,
output userInterruptG,
output userInterruptA,
output system_i2c_0_io_sda_writeEnable,
output system_i2c_0_io_sda_write,
input system_i2c_0_io_sda_read,
output system_i2c_0_io_scl_writeEnable,
output system_i2c_0_io_scl_write,
input system_i2c_0_io_scl_read,
input [3:0] system_gpio_0_io_read,
output [3:0] system_gpio_0_io_write,
output [3:0] system_gpio_0_io_writeEnable,
output system_watchdog_hardPanic_reset,
output userInterruptI,
input cpu3_customInstruction_cmd_valid,
output cpu3_customInstruction_cmd_ready,
input [9:0] cpu3_customInstruction_function_id,
input [31:0] cpu3_customInstruction_inputs_0,
input [31:0] cpu3_customInstruction_inputs_1,
output cpu3_customInstruction_rsp_valid,
input cpu3_customInstruction_rsp_ready,
output [31:0] cpu3_customInstruction_outputs_0,
output userInterruptD,
input [31:0] axiA_awaddr,
input [7:0] axiA_awlen,
input [2:0] axiA_awsize,
input [1:0] axiA_awburst,
input axiA_awlock,
input [3:0] axiA_awcache,
input [2:0] axiA_awprot,
input [3:0] axiA_awqos,
input [3:0] axiA_awregion,
input axiA_awvalid,
output axiA_awready,
input [31:0] axiA_wdata,
input [3:0] axiA_wstrb,
input axiA_wvalid,
input axiA_wlast,
output axiA_wready,
output [1:0] axiA_bresp,
output axiA_bvalid,
input axiA_bready,
input [31:0] axiA_araddr,
input [7:0] axiA_arlen,
input [2:0] axiA_arsize,
input [1:0] axiA_arburst,
input axiA_arlock,
input [3:0] axiA_arcache,
input [2:0] axiA_arprot,
input [3:0] axiA_arqos,
input [3:0] axiA_arregion,
input axiA_arvalid,
output axiA_arready,
output [31:0] axiA_rdata,
output [1:0] axiA_rresp,
output axiA_rlast,
output axiA_rvalid,
input axiA_rready,
output axiAInterrupt,
input cfg_done,
output cfg_start,
output cfg_sel,
output cfg_reset,
input io_peripheralClk,
input io_peripheralReset,
output io_asyncReset,
input io_gpio_sw_n,
input pll_peripheral_locked,
input pll_system_locked
);
wire [15:0] io_apbSlave_0_PADDR;
wire io_apbSlave_0_PSEL;
wire io_apbSlave_0_PENABLE;
wire io_apbSlave_0_PREADY;
wire io_apbSlave_0_PWRITE;
wire [31:0] io_apbSlave_0_PWDATA;
wire [31:0] io_apbSlave_0_PRDATA;
wire io_apbSlave_0_PSLVERROR;
assign userInterruptG = 1'b0; //USER TO MODIFY
assign userInterruptH = 1'b0; //USER TO MODIFY
assign userInterruptI = 1'b0; //USER TO MODIFY
/**/
/* INFO: USER TO MODIFY CODES BELOW */
/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
/**/
assign cpu3_customInstruction_cmd_ready = 1'b1;
assign cpu3_customInstruction_rsp_valid = 1'b0;
assign cpu3_customInstruction_outputs_0 = 32'd0;
//io_cfuClk
//io_cfyReset
//cpu3_customInstruction_rsp_ready
//cpu3_customInstruction_cmd_valid
//cpu3_customInstruction_function_id
//cpu3_customInstruction_inputs_0
//cpu3_customInstruction_inputs_1
/**/
/* INFO: USER TO MODIFY CODES BELOW */
/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
/**/
assign cpu0_customInstruction_cmd_ready = 1'b1;
assign cpu0_customInstruction_rsp_valid = 1'b0;
assign cpu0_customInstruction_outputs_0 = 32'd0;
//io_cfuClk
//io_cfyReset
//cpu0_customInstruction_rsp_ready
//cpu0_customInstruction_cmd_valid
//cpu0_customInstruction_function_id
//cpu0_customInstruction_inputs_0
//cpu0_customInstruction_inputs_1
/**/
/* INFO: USER TO MODIFY CODES BELOW */
/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
/**/
assign cpu1_customInstruction_cmd_ready = 1'b1;
assign cpu1_customInstruction_rsp_valid = 1'b0;
assign cpu1_customInstruction_outputs_0 = 32'd0;
//io_cfuClk
//io_cfyReset
//cpu1_customInstruction_rsp_ready
//cpu1_customInstruction_cmd_valid
//cpu1_customInstruction_function_id
//cpu1_customInstruction_inputs_0
//cpu1_customInstruction_inputs_1
/**/
/* INFO: USER TO MODIFY CODES BELOW */
/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
/**/
assign io_apbSlave_0_PREADY = 1'b1;
assign io_apbSlave_0_PRDATA = 32'd0;
//io_apbSlave_0_PADDR;
//io_apbSlave_0_PSEL;
//io_apbSlave_0_PENABLE;
//io_apbSlave_0_PWRITE;
//io_apbSlave_0_PWDATA;
//io_apbSlave_0_PSLVERROR;
/**/
/* INFO: USER TO MODIFY CODES BELOW */
/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
/**/
assign cpu2_customInstruction_cmd_ready = 1'b1;
assign cpu2_customInstruction_rsp_valid = 1'b0;
assign cpu2_customInstruction_outputs_0 = 32'd0;
//io_cfuClk
//io_cfyReset
//cpu2_customInstruction_rsp_ready
//cpu2_customInstruction_cmd_valid
//cpu2_customInstruction_function_id
//cpu2_customInstruction_inputs_0
//cpu2_customInstruction_inputs_1
/**/
/* INFO: USER TO MODIFY CODES BELOW */
/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
/**/
assign io_ddrMasters_0_aw_payload_addr = 32'd0;
assign io_ddrMasters_0_aw_payload_id = 4'd0;
assign io_ddrMasters_0_aw_payload_region = 4'd0;
assign io_ddrMasters_0_aw_payload_len = 8'd0;
assign io_ddrMasters_0_aw_payload_size = 3'd0;
assign io_ddrMasters_0_aw_payload_burst = 2'd0;
assign io_ddrMasters_0_aw_payload_lock = 1'b0;
assign io_ddrMasters_0_aw_payload_cache = 4'd0;
assign io_ddrMasters_0_aw_payload_qos = 4'd0;
assign io_ddrMasters_0_aw_payload_prot = 3'd0;
assign io_ddrMasters_0_aw_payload_allStrb = 1'b0;
assign io_ddrMasters_0_w_valid = 1'b0;
//io_ddrMasters_0_w_ready
assign io_ddrMasters_0_w_payload_data = 128'd0;
assign io_ddrMasters_0_w_payload_strb = 16'd0;
assign io_ddrMasters_0_w_payload_last = 1'b0;
//io_ddrMasters_0_b_valid
assign io_ddrMasters_0_b_ready = 1'b1;
//io_ddrMasters_0_b_payload_id
//io_ddrMasters_0_b_payload_resp
assign io_ddrMasters_0_ar_valid = 1'b0;
//io_ddrMasters_0_ar_ready
assign io_ddrMasters_0_ar_payload_addr = 32'd0;
assign io_ddrMasters_0_ar_payload_id = 4'd0;
assign io_ddrMasters_0_ar_payload_region = 4'd0;
assign io_ddrMasters_0_ar_payload_len = 8'd0;
assign io_ddrMasters_0_ar_payload_size = 3'd0;
assign io_ddrMasters_0_ar_payload_burst = 2'd0;
assign io_ddrMasters_0_ar_payload_lock = 1'b0;
assign io_ddrMasters_0_ar_payload_cache = 4'd0;
assign io_ddrMasters_0_ar_payload_qos = 4'd0;
assign io_ddrMasters_0_ar_payload_pro = 3'd0;
//io_ddrMasters_0_r_valid
assign io_ddrMasters_0_r_ready = 1'b1;
//io_ddrMasters_0_r_payload_data
//io_ddrMasters_0_r_payload_id
//io_ddrMasters_0_r_payload_resp
//io_ddrMasters_0_r_payload_last
//axi4 bridge to various I/O
EfxSapphireHpSoc_slb u_top_peripherals(
.userInterruptD(userInterruptD),
.userInterruptA(userInterruptA),
.system_watchdog_hardPanic_reset(system_watchdog_hardPanic_reset),
.system_uart_0_io_txd(system_uart_0_io_txd),
.system_uart_0_io_rxd(system_uart_0_io_rxd),
.system_spi_0_io_sclk_write(system_spi_0_io_sclk_write),
.system_spi_0_io_data_0_writeEnable(system_spi_0_io_data_0_writeEnable),
.system_spi_0_io_data_0_read(system_spi_0_io_data_0_read),
.system_spi_0_io_data_0_write(system_spi_0_io_data_0_write),
.system_spi_0_io_data_1_writeEnable(system_spi_0_io_data_1_writeEnable),
.system_spi_0_io_data_1_read(system_spi_0_io_data_1_read),
.system_spi_0_io_data_1_write(system_spi_0_io_data_1_write),
.system_spi_0_io_data_2_writeEnable(system_spi_0_io_data_2_writeEnable),
.system_spi_0_io_data_2_read(system_spi_0_io_data_2_read),
.system_spi_0_io_data_2_write(system_spi_0_io_data_2_write),
.system_spi_0_io_data_3_writeEnable(system_spi_0_io_data_3_writeEnable),
.system_spi_0_io_data_3_read(system_spi_0_io_data_3_read),
.system_spi_0_io_data_3_write(system_spi_0_io_data_3_write),
.system_spi_0_io_ss(system_spi_0_io_ss),
.system_gpio_0_io_read(system_gpio_0_io_read),
.system_gpio_0_io_write(system_gpio_0_io_write),
.system_gpio_0_io_writeEnable(system_gpio_0_io_writeEnable),
.userInterruptB(userInterruptB),
.userInterruptE(userInterruptE),
.io_apbSlave_0_PADDR(io_apbSlave_0_PADDR),
.io_apbSlave_0_PSEL(io_apbSlave_0_PSEL),
.io_apbSlave_0_PENABLE(io_apbSlave_0_PENABLE),
.io_apbSlave_0_PREADY(io_apbSlave_0_PREADY),
.io_apbSlave_0_PWRITE(io_apbSlave_0_PWRITE),
.io_apbSlave_0_PWDATA(io_apbSlave_0_PWDATA),
.io_apbSlave_0_PRDATA(io_apbSlave_0_PRDATA),
.io_apbSlave_0_PSLVERROR(io_apbSlave_0_PSLVERROR),
.system_i2c_0_io_sda_writeEnable(system_i2c_0_io_sda_writeEnable),
.system_i2c_0_io_sda_write(system_i2c_0_io_sda_write),
.system_i2c_0_io_sda_read(system_i2c_0_io_sda_read),
.system_i2c_0_io_scl_writeEnable(system_i2c_0_io_scl_writeEnable),
.system_i2c_0_io_scl_write(system_i2c_0_io_scl_write),
.system_i2c_0_io_scl_read(system_i2c_0_io_scl_read),
.userInterruptF(userInterruptF),
.jtagCtrl_tdi(jtagCtrl_tdi),
.jtagCtrl_tdo(jtagCtrl_tdo),
.jtagCtrl_enable(jtagCtrl_enable),
.jtagCtrl_capture(jtagCtrl_capture),
.jtagCtrl_shift(jtagCtrl_shift),
.jtagCtrl_update(jtagCtrl_update),
.jtagCtrl_reset(jtagCtrl_reset),
.ut_jtagCtrl_tdi(ut_jtagCtrl_tdi),
.ut_jtagCtrl_tdo(ut_jtagCtrl_tdo),
.ut_jtagCtrl_enable(ut_jtagCtrl_enable),
.ut_jtagCtrl_capture(ut_jtagCtrl_capture),
.ut_jtagCtrl_shift(ut_jtagCtrl_shift),
.ut_jtagCtrl_update(ut_jtagCtrl_update),
.ut_jtagCtrl_reset(ut_jtagCtrl_reset),
.userInterruptC(userInterruptC),
.axiA_awvalid(axiA_awvalid),
.axiA_awready(axiA_awready),
.axiA_awaddr(axiA_awaddr),
.axiA_awlen(axiA_awlen),
.axiA_awsize(axiA_awsize),
.axiA_awcache(axiA_awcache),
.axiA_awprot(axiA_awprot),
.axiA_wvalid(axiA_wvalid),
.axiA_wready(axiA_wready),
.axiA_wdata(axiA_wdata),
.axiA_wstrb(axiA_wstrb),
.axiA_wlast(axiA_wlast),
.axiA_bvalid(axiA_bvalid),
.axiA_bready(axiA_bready),
.axiA_bresp(axiA_bresp),
.axiA_arvalid(axiA_arvalid),
.axiA_arready(axiA_arready),
.axiA_araddr(axiA_araddr),
.axiA_arlen(axiA_arlen),
.axiA_arsize(axiA_arsize),
.axiA_arcache(axiA_arcache),
.axiA_arprot(axiA_arprot),
.axiA_rvalid(axiA_rvalid),
.axiA_rready(axiA_rready),
.axiA_rdata(axiA_rdata),
.axiA_rresp(axiA_rresp),
.axiA_rlast(axiA_rlast),
.axiAInterrupt(axiAInterrupt),
.cfg_done(cfg_done),
.cfg_start(cfg_start),
.cfg_sel(cfg_sel),
.cfg_reset(cfg_reset),
.io_peripheralClk(io_peripheralClk),
.io_peripheralReset(io_peripheralReset),
.io_asyncReset(io_asyncReset),
.io_gpio_sw_n(io_gpio_sw_n),
.pll_peripheral_locked(pll_peripheral_locked),
.pll_system_locked(pll_system_locked)
);
endmodule

224
fpga/ip/EfxSapphireHpSoc_slb/hard_ip_args.ini
View File

@@ -1,224 +0,0 @@
[parameters]
pll_soc_sys_clk_name = soc_pll_sys_clk
hidden_min_freq = 0
pll_soc_sys_clk_ref_freq_hidden = 100
pll_soc_sys_clk_ref_freq = 100
pll_soc_sys_clkout1_freq = 1000
pll_soc_sys_clkout1_phase = 0
pll_soc_sys_clkout2_freq = 250
pll_soc_sys_clkout2_phase = 0
pll_soc_mem_clk_name = soc_pll_peri_clk
pll_soc_mem_clk_ref_freq = 25
pll_soc_mem_clkout1_freq = 250
pll_soc_mem_clkout1_phase = 0
pll_soc_mem_clkout2_freq = 250
pll_soc_mem_clkout2_phase = 0
pll_lpddr4_name = soc_ddr_pll
pll_lpddr4_ref_freq = 25
pll_lpddr4_clkout0_freq = 100
pll_lpddr4_clkout0_phase = 0
pll_lpddr4_clkout3_freq = 533
pll_lpddr4_clkout3_phase = 0
ddr_data_width = 32
ddr_memory_density = 8G
ddr_memory_type = LPDDR4x
ddr_physical_rank = 1
ddr_pin_name = soc_ddr_inst1
gpio_bus_name = system_gpio_0
hard_jtag_inst_name = soc_jtag_inst1
uart0_gpio_inst_name = system_uart_0
spi0_gpio_inst_name = system_spi_0
i2c0_gpio_inst_name = system_i2c_0
jtag_gpio_inst_name = io_jtag
soc_pin_name = qcrv32_inst1
intf_axim = 1
intf_ci_0 = 1
intf_ci_1 = 1
intf_ci_2 = 1
intf_ci_3 = 1
co_debug = 0
intf_jtag_type = 0
intf_uintr = 9
peri_spi_0 = 1
peri_spi_1 = 0
peri_spi_2 = 0
peri_i2c_0 = 1
peri_i2c_1 = 0
peri_i2c_2 = 0
peri_gpio_0 = 1
peri_gpio_1 = 0
peri_wdt_0 = 1
peri_apb_0 = 1
peri_apb_1 = 0
peri_apb_2 = 0
peri_apb_3 = 0
peri_apb_4 = 0
peri_gen = 1
peri_uart_0 = 1
peri_uart_1 = 0
peri_uart_2 = 0
peri_gpio_0_width = 4
peri_gpio_1_width = 4
peri_apb_0_size = 65536
peri_apb_1_size = 4096
peri_apb_2_size = 4096
peri_apb_3_size = 4096
peri_apb_4_size = 4096
peri_freq = 200
app_overwrite = 0
app_overwrite_path =
peri_count = 6
peri_tcount = 6
intf_jtag_tap_sel = 8
intf_axis = 1
peri_pin_assign = 1
pll_soc_mem_resource = PLL_TR0
sys_freq = 1000
sys_freq_hidden = 1000
pll_soc_sys_clkout3_freq = 250
pll_soc_sys_clkout3_phase = 0
pll_soc_mem_clkout3_freq = 250
pll_soc_mem_clkout3_phase = 0
pll_soc_mem_clkout4_freq = 200
pll_soc_mem_clkout4_phase = 0
pll_soc_sys_resource = PLL_BL0
pll_lpddr4_resource = PLL_BL2
pll_res_assign = 0
pll_soc_sys_clkout0_freq = 100
pll_soc_sys_clkout0_phase = 0
pll_soc_mem_clkout0_freq = 100
pll_soc_mem_clkout0_phase = 0
pll_lpddr4_clkout1_freq = 33
pll_lpddr4_clkout1_phase = 0
mem_freq = 250
axim_freq = 250
cfu_freq = 125
ddr_freq = 800
pll_res_assign_2 = 0
ddr_res_assign = 0
peri_res_assign = 0
pll_soc_sys_ext_clk_src = 1
pll_soc_mem_ext_clk_src = 0
peri_sdhc = 0
peri_tsemac = 0
sw_ftdi_ch_num = 6011
sw_app_size = 2044
sw_app_size_custom = 0
sw_stack_size = 8
sw_stack_size_custom = 0
sw_board = Ti375C529 Development Kit
sw_board_custom =
sw_ftdi_target_ch = 1
sw_ftdi_ch_num_soft = 6011
sw_ftdi_target_ch_soft = 0
sw_frtos_app_size = 16380
sw_frtos_app_size_custom = 0
sw_frtos_stack_size = 4
sw_frtos_stack_size_custom = 0
package_type = 529
family_type = TITANIUM
axi_pipeline = 0
axi_write_buffer = 0
[ports]
io_peripheralclk = io_peripheralClk
io_peripheralreset = io_peripheralReset
io_asyncreset = io_asyncReset
io_gpio_sw_n = io_gpio_sw_n
pll_peripheral_locked = pll_peripheral_locked
pll_system_locked = pll_system_locked
jtagctrl_capture = jtagCtrl_capture
jtagctrl_enable = jtagCtrl_enable
jtagctrl_reset = jtagCtrl_reset
jtagctrl_shift = jtagCtrl_shift
jtagctrl_tdi = jtagCtrl_tdi
jtagctrl_tdo = jtagCtrl_tdo
jtagctrl_update = jtagCtrl_update
ut_jtagctrl_capture = ut_jtagCtrl_capture
ut_jtagctrl_enable = ut_jtagCtrl_enable
ut_jtagctrl_reset = ut_jtagCtrl_reset
ut_jtagctrl_shift = ut_jtagCtrl_shift
ut_jtagctrl_tdi = ut_jtagCtrl_tdi
ut_jtagctrl_tdo = ut_jtagCtrl_tdo
ut_jtagctrl_update = ut_jtagCtrl_update
system_spi_0_io_data_0_read = system_spi_0_io_data_0_read
system_spi_0_io_data_0_write = system_spi_0_io_data_0_write
system_spi_0_io_data_0_writeenable = system_spi_0_io_data_0_writeEnable
system_spi_0_io_data_1_read = system_spi_0_io_data_1_read
system_spi_0_io_data_1_write = system_spi_0_io_data_1_write
system_spi_0_io_data_1_writeenable = system_spi_0_io_data_1_writeEnable
system_spi_0_io_data_2_read = system_spi_0_io_data_2_read
system_spi_0_io_data_2_write = system_spi_0_io_data_2_write
system_spi_0_io_data_2_writeenable = system_spi_0_io_data_2_writeEnable
system_spi_0_io_data_3_read = system_spi_0_io_data_3_read
system_spi_0_io_data_3_write = system_spi_0_io_data_3_write
system_spi_0_io_data_3_writeenable = system_spi_0_io_data_3_writeEnable
system_spi_0_io_sclk_write = system_spi_0_io_sclk_write
system_spi_0_io_ss = system_spi_0_io_ss
system_uart_0_io_rxd = system_uart_0_io_rxd
system_uart_0_io_txd = system_uart_0_io_txd
system_i2c_0_io_scl_read = system_i2c_0_io_scl_read
system_i2c_0_io_scl_write = system_i2c_0_io_scl_write
system_i2c_0_io_sda_read = system_i2c_0_io_sda_read
system_gpio_0_io_read = system_gpio_0_io_read
system_gpio_0_io_write = system_gpio_0_io_write
system_gpio_0_io_writeenable = system_gpio_0_io_writeEnable
cfg_done = cfg_done
cfg_start = cfg_start
cfg_sel = cfg_sel
cfg_reset = cfg_reset
axiainterrupt = axiAInterrupt
axia_awaddr = axiA_awaddr
axia_awlen = axiA_awlen
axia_awsize = axiA_awsize
axia_awburst = axiA_awburst
axia_awlock = axiA_awlock
axia_awcache = axiA_awcache
axia_awprot = axiA_awprot
axia_awqos = axiA_awqos
axia_awregion = axiA_awregion
axia_awvalid = axiA_awvalid
axia_awready = axiA_awready
axia_wdata = axiA_wdata
axia_wstrb = axiA_wstrb
axia_wvalid = axiA_wvalid
axia_wlast = axiA_wlast
axia_wready = axiA_wready
axia_bresp = axiA_bresp
axia_bvalid = axiA_bvalid
axia_bready = axiA_bready
axia_araddr = axiA_araddr
axia_arlen = axiA_arlen
axia_arsize = axiA_arsize
axia_arburst = axiA_arburst
axia_arlock = axiA_arlock
axia_arcache = axiA_arcache
axia_arprot = axiA_arprot
axia_arqos = axiA_arqos
axia_arregion = axiA_arregion
axia_arvalid = axiA_arvalid
axia_arready = axiA_arready
axia_rdata = axiA_rdata
axia_rresp = axiA_rresp
axia_rlast = axiA_rlast
axia_rvalid = axiA_rvalid
axia_rready = axiA_rready
userinterrupta = userInterruptA
userinterruptb = userInterruptB
userinterruptc = userInterruptC
userinterruptd = userInterruptD
userinterrupte = userInterruptE
userinterruptf = userInterruptF
io_apbslave_0_paddr = io_apbSlave_0_PADDR
io_apbslave_0_penable = io_apbSlave_0_PENABLE
io_apbslave_0_prdata = io_apbSlave_0_PRDATA
io_apbslave_0_pready = io_apbSlave_0_PREADY
io_apbslave_0_psel = io_apbSlave_0_PSEL
io_apbslave_0_pslverror = io_apbSlave_0_PSLVERROR
io_apbslave_0_pwdata = io_apbSlave_0_PWDATA
io_apbslave_0_pwrite = io_apbSlave_0_PWRITE
system_i2c_0_io_sda_write = system_i2c_0_io_sda_write
system_i2c_0_io_sda_writeenable = system_i2c_0_io_sda_writeEnable
system_i2c_0_io_scl_writeenable = system_i2c_0_io_scl_writeEnable
system_watchdog_hardpanic_reset = system_watchdog_hardPanic_reset

BIN
fpga/ip/EfxSapphireHpSoc_slb/ipm/component.pickle
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Binary file not shown.

BIN
fpga/ip/EfxSapphireHpSoc_slb/ipm/graph.pickle
View File

Binary file not shown.

20
fpga/ip/EfxSapphireHpSoc_slb/ipm_pt_map.json
View File

@@ -1,20 +0,0 @@
{
"PLL": {},
"GPIO": {
"UART": [],
"SPI": [],
"I2C": [],
"JTAG": [],
"GPIO": []
},
"SOC": {
"SOC_PIN_NAME": {
"SOC_PIN_NAME": "qcrv32_inst1"
}
},
"JTAG": {
"HARD_JTAG_INST_NAME": {
"HARD_JTAG_INST_NAME": "soc_jtag_inst1"
}
}
}

10
fpga/ip/EfxSapphireHpSoc_slb/settings.json
View File

@@ -35,11 +35,11 @@
"DDR_MEMORY_TYPE": "\"LPDDR4x\"",
"DDR_PHYSICAL_RANK": "1",
"DDR_PIN_NAME": "\"soc_ddr_inst1\"",
"INTF_AXIM": "1'b1",
"INTF_CI_0": "1'b1",
"INTF_CI_1": "1'b1",
"INTF_CI_2": "1'b1",
"INTF_CI_3": "1'b1",
"INTF_AXIM": "1'b0",
"INTF_CI_0": "1'b0",
"INTF_CI_1": "1'b0",
"INTF_CI_2": "1'b0",
"INTF_CI_3": "1'b0",
"CO_DEBUG": "1'b0",
"INTF_JTAG_TYPE": "0",
"INTF_UINTR": "9",

8070
fpga/ip/EfxSapphireHpSoc_slb/source/Axi4PeripheralTop.v
View File

File diff suppressed because it is too large Load Diff

8
fpga/ip/EfxSapphireHpSoc_slb/source/peri_config
View File

@@ -1,8 +0,0 @@
--peripheralFrequency 200000000
--PeripheralClock true
--uart name=system_uart_0_io,address=0x10000,interruptId=0
--apbSlave name=io_apbSlave_0,address=0x100000,size=65536
--watchdog name=system_watchdog,address=0x50000,interruptId=13,prescalerWidth=24,counters=2,countersWidth=16
--gpio name=system_gpio_0_io,address=0x40000,width=4,interrupts="0->9;1->10"
--i2c name=system_i2c_0_io,address=0x20000,interruptId=6
--spi name=system_spi_0_io,address=0x30000,interruptId=3,width=8,ssCount=4