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Grand refactor

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This commit is contained in:
Byron Lathi
2026-04-18 19:19:55 -07:00
parent ef6b5f0669
commit 470bbc39ec
162 changed files with 483 additions and 335580 deletions
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10
fpga/ip/EfxSapphireHpSoc_slb/settings.json
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@@ -35,11 +35,11 @@
"DDR_MEMORY_TYPE": "\"LPDDR4x\"",
"DDR_PHYSICAL_RANK": "1",
"DDR_PIN_NAME": "\"soc_ddr_inst1\"",
"INTF_AXIM": "1'b1",
"INTF_CI_0": "1'b1",
"INTF_CI_1": "1'b1",
"INTF_CI_2": "1'b1",
"INTF_CI_3": "1'b1",
"INTF_AXIM": "1'b0",
"INTF_CI_0": "1'b0",
"INTF_CI_1": "1'b0",
"INTF_CI_2": "1'b0",
"INTF_CI_3": "1'b0",
"CO_DEBUG": "1'b0",
"INTF_JTAG_TYPE": "0",
"INTF_UINTR": "9",