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fpga/constraints.sdc
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fpga/constraints.sdc
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# Auto-generated by Interface Designer
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#
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# WARNING: Any manual changes made to this file will be lost when generating constraints.
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# Efinity Interface Designer SDC
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# Version: 2024.M.98
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# Date: 2024-04-13 10:16
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# Copyright (C) 2013 - 2024 Efinix Inc. All rights reserved.
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# Device: Ti375C529
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# Project: Ti375C529_devkit
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# Timing Model: C4 (preliminary)
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# NOTE: The timing data is not final
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# PLL Constraints
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#################
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create_clock -period 10.0000 io_sysFbClk
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create_clock -period 5.0000 io_peripheralClk
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create_clock -period 4.0000 io_ddrMasters_0_clk
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create_clock -period 8.0000 io_cfuClk
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create_clock -period 10.0000 sd_base_clk
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create_clock -period 8.0000 rgmii_rxc
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create_clock -waveform {2.0000 6.0000} -period 8.0000 io_tseClk_90
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create_clock -period 8.0000 io_tseClk
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set_clock_groups -exclusive -group {rgmii_rxc io_tseClk_90 io_tseClk} -group {sd_base_clk} -group {io_cfuClk} -group {io_peripheralClk} -group {io_ddrMasters_0_clk}
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# GPIO Constraints
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####################
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set_output_delay -clock sd_base_clk -reference_pin [get_ports {sd_base_clk~CLKOUT~347~2}] -max 0.079 [get_ports {sd_clk_hi}]
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set_output_delay -clock sd_base_clk -reference_pin [get_ports {sd_base_clk~CLKOUT~347~2}] -min -0.045 [get_ports {sd_clk_hi}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {io_gpio_sw_n}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {io_gpio_sw_n}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_uart_0_io_rxd}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_uart_0_io_rxd}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_uart_0_io_txd}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_uart_0_io_txd}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_read[1]}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_read[1]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_write[1]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_write[1]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_writeEnable[1]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_writeEnable[1]}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_read[2]}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_read[2]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_write[2]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_write[2]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_writeEnable[2]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_writeEnable[2]}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_i2c_0_io_scl_read}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_i2c_0_io_scl_read}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_i2c_0_io_scl_write}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_i2c_0_io_scl_write}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_i2c_0_io_scl_writeEnable}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_i2c_0_io_scl_writeEnable}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_i2c_0_io_sda_read}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_i2c_0_io_sda_read}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_i2c_0_io_sda_write}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_i2c_0_io_sda_write}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_i2c_0_io_sda_writeEnable}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_i2c_0_io_sda_writeEnable}]
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# JTAG Constraints
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####################
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create_clock -period 100 [get_ports {jtagCtrl_tck}]
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set_output_delay -clock jtagCtrl_tck -max 0.117 [get_ports {ut_jtagCtrl_tdo}]
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set_output_delay -clock jtagCtrl_tck -min -0.075 [get_ports {ut_jtagCtrl_tdo}]
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set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.280 [get_ports {ut_jtagCtrl_capture}]
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set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.187 [get_ports {ut_jtagCtrl_capture}]
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set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.280 [get_ports {ut_jtagCtrl_reset}]
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set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.187 [get_ports {ut_jtagCtrl_reset}]
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set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.243 [get_ports {ut_jtagCtrl_enable}]
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set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.162 [get_ports {ut_jtagCtrl_enable}]
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set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.280 [get_ports {ut_jtagCtrl_update}]
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set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.187 [get_ports {ut_jtagCtrl_update}]
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set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.337 [get_ports {ut_jtagCtrl_shift}]
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set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.225 [get_ports {ut_jtagCtrl_shift}]
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# JTAG Constraints (extra... not used by current Efinity debug tools)
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# Create separate clock groups for JTAG clocks. Remove DRCK clock from the list below if it is not defined.
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# set_clock_groups -asynchronous -group {jtagCtrl_tck}
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# HSIO GPIO Constraints
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#########################
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set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~391~964}] -max 0.414 [get_ports {rgmii_rx_ctl_LO rgmii_rx_ctl_HI}]
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set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~391~964}] -min 0.276 [get_ports {rgmii_rx_ctl_LO rgmii_rx_ctl_HI}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {rgmii_rxc_phy}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {rgmii_rxc_phy}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {rgmii_rxc_slow}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {rgmii_rxc_slow}]
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set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~395~964}] -max 0.414 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}]
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set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~395~964}] -min 0.276 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}]
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set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~397~964}] -max 0.414 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}]
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set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~397~964}] -min 0.276 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}]
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set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~408~964}] -max 0.414 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}]
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set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~408~964}] -min 0.276 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}]
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set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~412~963}] -max 0.414 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}]
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set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~412~963}] -min 0.276 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {sd_cd_n}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {sd_cd_n}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {io_ddrMasters_memCheck_pass}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {io_ddrMasters_memCheck_pass}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {phy_mdc}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {phy_mdc}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~352~963}] -max 0.263 [get_ports {rgmii_tx_ctl_LO rgmii_tx_ctl_HI}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~352~963}] -min -0.140 [get_ports {rgmii_tx_ctl_LO rgmii_tx_ctl_HI}]
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set_output_delay -clock io_tseClk_90 -reference_pin [get_ports {io_tseClk_90~CLKOUT~359~964}] -max 0.263 [get_ports {rgmii_txc_LO rgmii_txc_HI}]
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set_output_delay -clock io_tseClk_90 -reference_pin [get_ports {io_tseClk_90~CLKOUT~359~964}] -min -0.140 [get_ports {rgmii_txc_LO rgmii_txc_HI}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~358~963}] -max 0.263 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~358~963}] -min -0.140 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~364~963}] -max 0.263 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~364~963}] -min -0.140 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~365~964}] -max 0.263 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~365~964}] -min -0.140 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~376~964}] -max 0.263 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~376~964}] -min -0.140 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}]
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set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~2}] -max 0.263 [get_ports {system_spi_0_io_sclk_write}]
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set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~2}] -min -0.140 [get_ports {system_spi_0_io_sclk_write}]
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set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~407~2}] -max 0.263 [get_ports {system_spi_0_io_ss[0]}]
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set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~407~2}] -min -0.140 [get_ports {system_spi_0_io_ss[0]}]
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set_input_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~381~964}] -max 0.414 [get_ports {phy_mdi}]
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set_input_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~381~964}] -min 0.276 [get_ports {phy_mdi}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -max 0.263 [get_ports {phy_mdo}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -min -0.140 [get_ports {phy_mdo}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -max 0.263 [get_ports {phy_mdo_en}]
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set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -min -0.140 [get_ports {phy_mdo_en}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_read[0]}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_read[0]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_write[0]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_write[0]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_writeEnable[0]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_writeEnable[0]}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_read[3]}]
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# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_read[3]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_write[3]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_write[3]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_writeEnable[3]}]
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# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_writeEnable[3]}]
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set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~1}] -max 0.414 [get_ports {system_spi_0_io_data_0_read}]
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set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~1}] -min 0.276 [get_ports {system_spi_0_io_data_0_read}]
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set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -max 0.263 [get_ports {system_spi_0_io_data_0_write}]
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set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -min -0.140 [get_ports {system_spi_0_io_data_0_write}]
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set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -max 0.263 [get_ports {system_spi_0_io_data_0_writeEnable}]
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set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -min -0.140 [get_ports {system_spi_0_io_data_0_writeEnable}]
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set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~425~1}] -max 0.414 [get_ports {system_spi_0_io_data_1_read}]
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set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~425~1}] -min 0.276 [get_ports {system_spi_0_io_data_1_read}]
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set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -max 0.263 [get_ports {system_spi_0_io_data_1_write}]
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set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -min -0.140 [get_ports {system_spi_0_io_data_1_write}]
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set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -max 0.263 [get_ports {system_spi_0_io_data_1_writeEnable}]
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set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -min -0.140 [get_ports {system_spi_0_io_data_1_writeEnable}]
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# QCRV32 Constraints
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#######################
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set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.701 [get_ports {io_ddrMasters_0_reset}]
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set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.340 [get_ports {io_ddrMasters_0_reset}]
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set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.196 [get_ports {io_ddrMasters_0_ar_payload_addr[*]}]
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set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.071 [get_ports {io_ddrMasters_0_ar_payload_addr[*]}]
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set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.217 [get_ports {io_ddrMasters_0_ar_payload_burst[*]}]
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set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.034 [get_ports {io_ddrMasters_0_ar_payload_burst[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.222 [get_ports {io_ddrMasters_0_ar_payload_cache[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.020 [get_ports {io_ddrMasters_0_ar_payload_cache[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.247 [get_ports {io_ddrMasters_0_ar_payload_id[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.038 [get_ports {io_ddrMasters_0_ar_payload_id[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.251 [get_ports {io_ddrMasters_0_ar_payload_len[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.008 [get_ports {io_ddrMasters_0_ar_payload_len[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.226 [get_ports {io_ddrMasters_0_ar_payload_lock}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.054 [get_ports {io_ddrMasters_0_ar_payload_lock}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.265 [get_ports {io_ddrMasters_0_ar_payload_prot[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.006 [get_ports {io_ddrMasters_0_ar_payload_prot[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.191 [get_ports {io_ddrMasters_0_ar_payload_qos[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.013 [get_ports {io_ddrMasters_0_ar_payload_qos[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.259 [get_ports {io_ddrMasters_0_ar_payload_region[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.018 [get_ports {io_ddrMasters_0_ar_payload_region[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.219 [get_ports {io_ddrMasters_0_ar_payload_size[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.007 [get_ports {io_ddrMasters_0_ar_payload_size[*]}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.064 [get_ports {io_ddrMasters_0_ar_ready}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.544 [get_ports {io_ddrMasters_0_ar_ready}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.025 [get_ports {io_ddrMasters_0_ar_valid}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.051 [get_ports {io_ddrMasters_0_ar_valid}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.031 [get_ports {io_ddrMasters_0_r_payload_data[*]}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.347 [get_ports {io_ddrMasters_0_r_payload_data[*]}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.844 [get_ports {io_ddrMasters_0_r_payload_last}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.387 [get_ports {io_ddrMasters_0_r_payload_last}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.426 [get_ports {io_ddrMasters_0_r_ready}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.095 [get_ports {io_ddrMasters_0_r_ready}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.965 [get_ports {io_ddrMasters_0_r_valid}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.508 [get_ports {io_ddrMasters_0_r_valid}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.372 [get_ports {io_ddrMasters_0_aw_payload_addr[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.005 [get_ports {io_ddrMasters_0_aw_payload_addr[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.296 [get_ports {io_ddrMasters_0_aw_payload_allStrb}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.016 [get_ports {io_ddrMasters_0_aw_payload_allStrb}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.217 [get_ports {io_ddrMasters_0_aw_payload_burst[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.002 [get_ports {io_ddrMasters_0_aw_payload_burst[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.217 [get_ports {io_ddrMasters_0_aw_payload_cache[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.027 [get_ports {io_ddrMasters_0_aw_payload_cache[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.238 [get_ports {io_ddrMasters_0_aw_payload_id[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.001 [get_ports {io_ddrMasters_0_aw_payload_id[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.280 [get_ports {io_ddrMasters_0_aw_payload_len[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.003 [get_ports {io_ddrMasters_0_aw_payload_len[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.205 [get_ports {io_ddrMasters_0_aw_payload_lock}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.022 [get_ports {io_ddrMasters_0_aw_payload_lock}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.178 [get_ports {io_ddrMasters_0_aw_payload_prot[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.039 [get_ports {io_ddrMasters_0_aw_payload_prot[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.243 [get_ports {io_ddrMasters_0_aw_payload_qos[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.053 [get_ports {io_ddrMasters_0_aw_payload_qos[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.253 [get_ports {io_ddrMasters_0_aw_payload_region[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.008 [get_ports {io_ddrMasters_0_aw_payload_region[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.263 [get_ports {io_ddrMasters_0_aw_payload_size[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.007 [get_ports {io_ddrMasters_0_aw_payload_size[*]}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.213 [get_ports {io_ddrMasters_0_aw_ready}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.610 [get_ports {io_ddrMasters_0_aw_ready}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.294 [get_ports {io_ddrMasters_0_aw_valid}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.058 [get_ports {io_ddrMasters_0_aw_valid}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.289 [get_ports {io_ddrMasters_0_w_payload_data[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.105 [get_ports {io_ddrMasters_0_w_payload_data[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.042 [get_ports {io_ddrMasters_0_w_payload_last}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.053 [get_ports {io_ddrMasters_0_w_payload_last}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.130 [get_ports {io_ddrMasters_0_w_payload_strb[*]}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.070 [get_ports {io_ddrMasters_0_w_payload_strb[*]}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.193 [get_ports {io_ddrMasters_0_w_ready}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.616 [get_ports {io_ddrMasters_0_w_ready}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.118 [get_ports {io_ddrMasters_0_w_valid}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.038 [get_ports {io_ddrMasters_0_w_valid}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.196 [get_ports {io_ddrMasters_0_b_ready}]
|
||||
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.012 [get_ports {io_ddrMasters_0_b_ready}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.991 [get_ports {io_ddrMasters_0_b_valid}]
|
||||
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.514 [get_ports {io_ddrMasters_0_b_valid}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.766 [get_ports {axiAInterrupt}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.322 [get_ports {axiAInterrupt}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.089 [get_ports {axiA_araddr[*]}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.425 [get_ports {axiA_araddr[*]}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.134 [get_ports {axiA_arlen[*]}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.484 [get_ports {axiA_arlen[*]}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.285 [get_ports {axiA_arready}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.074 [get_ports {axiA_arready}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.824 [get_ports {axiA_arvalid}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.444 [get_ports {axiA_arvalid}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.660 [get_ports {axiA_rdata[*]}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.018 [get_ports {axiA_rdata[*]}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.384 [get_ports {axiA_rlast}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.068 [get_ports {axiA_rlast}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.305 [get_ports {axiA_rready}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.647 [get_ports {axiA_rready}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.460 [get_ports {axiA_rresp[*]}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.113 [get_ports {axiA_rresp[*]}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.344 [get_ports {axiA_rvalid}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.071 [get_ports {axiA_rvalid}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.710 [get_ports {axiA_awaddr[*]}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.344 [get_ports {axiA_awaddr[*]}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.753 [get_ports {axiA_awlen[*]}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.363 [get_ports {axiA_awlen[*]}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.156 [get_ports {axiA_awready}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min -0.017 [get_ports {axiA_awready}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.674 [get_ports {axiA_awvalid}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.354 [get_ports {axiA_awvalid}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.000 [get_ports {axiA_wdata[*]}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.373 [get_ports {axiA_wdata[*]}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.933 [get_ports {axiA_wlast}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.494 [get_ports {axiA_wlast}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.155 [get_ports {axiA_wready}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min -0.018 [get_ports {axiA_wready}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.021 [get_ports {axiA_wstrb[*]}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.491 [get_ports {axiA_wstrb[*]}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.799 [get_ports {axiA_wvalid}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.414 [get_ports {axiA_wvalid}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.944 [get_ports {axiA_bready}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.494 [get_ports {axiA_bready}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.315 [get_ports {axiA_bresp[*]}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.064 [get_ports {axiA_bresp[*]}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.251 [get_ports {axiA_bvalid}]
|
||||
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.052 [get_ports {axiA_bvalid}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.730 [get_ports {io_peripheralReset}]
|
||||
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.386 [get_ports {io_peripheralReset}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.777 [get_ports {cpu0_customInstruction_cmd_ready}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.246 [get_ports {cpu0_customInstruction_cmd_ready}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.488 [get_ports {cpu0_customInstruction_cmd_valid}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.776 [get_ports {cpu0_customInstruction_cmd_valid}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.500 [get_ports {cpu0_customInstruction_function_id[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.637 [get_ports {cpu0_customInstruction_function_id[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.545 [get_ports {cpu0_customInstruction_inputs_0[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.612 [get_ports {cpu0_customInstruction_inputs_0[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.428 [get_ports {cpu0_customInstruction_inputs_1[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.625 [get_ports {cpu0_customInstruction_inputs_1[*]}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.844 [get_ports {cpu0_customInstruction_outputs_0[*]}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.147 [get_ports {cpu0_customInstruction_outputs_0[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.401 [get_ports {cpu0_customInstruction_rsp_ready}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.746 [get_ports {cpu0_customInstruction_rsp_ready}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.864 [get_ports {cpu0_customInstruction_rsp_valid}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.251 [get_ports {cpu0_customInstruction_rsp_valid}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.947 [get_ports {cpu1_customInstruction_cmd_ready}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.300 [get_ports {cpu1_customInstruction_cmd_ready}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.580 [get_ports {cpu1_customInstruction_cmd_valid}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.804 [get_ports {cpu1_customInstruction_cmd_valid}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.849 [get_ports {cpu1_customInstruction_function_id[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.720 [get_ports {cpu1_customInstruction_function_id[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.956 [get_ports {cpu1_customInstruction_inputs_0[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.752 [get_ports {cpu1_customInstruction_inputs_0[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.810 [get_ports {cpu1_customInstruction_inputs_1[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.748 [get_ports {cpu1_customInstruction_inputs_1[*]}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.052 [get_ports {cpu1_customInstruction_outputs_0[*]}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.169 [get_ports {cpu1_customInstruction_outputs_0[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.643 [get_ports {cpu1_customInstruction_rsp_ready}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.869 [get_ports {cpu1_customInstruction_rsp_ready}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.800 [get_ports {cpu1_customInstruction_rsp_valid}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.278 [get_ports {cpu1_customInstruction_rsp_valid}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.863 [get_ports {cpu2_customInstruction_cmd_ready}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.325 [get_ports {cpu2_customInstruction_cmd_ready}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.757 [get_ports {cpu2_customInstruction_cmd_valid}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.841 [get_ports {cpu2_customInstruction_cmd_valid}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.667 [get_ports {cpu2_customInstruction_function_id[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.801 [get_ports {cpu2_customInstruction_function_id[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.848 [get_ports {cpu2_customInstruction_inputs_0[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.750 [get_ports {cpu2_customInstruction_inputs_0[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.750 [get_ports {cpu2_customInstruction_inputs_1[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.762 [get_ports {cpu2_customInstruction_inputs_1[*]}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.950 [get_ports {cpu2_customInstruction_outputs_0[*]}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.234 [get_ports {cpu2_customInstruction_outputs_0[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.745 [get_ports {cpu2_customInstruction_rsp_ready}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.931 [get_ports {cpu2_customInstruction_rsp_ready}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.726 [get_ports {cpu2_customInstruction_rsp_valid}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.277 [get_ports {cpu2_customInstruction_rsp_valid}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.730 [get_ports {cpu3_customInstruction_cmd_ready}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.297 [get_ports {cpu3_customInstruction_cmd_ready}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.529 [get_ports {cpu3_customInstruction_cmd_valid}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.830 [get_ports {cpu3_customInstruction_cmd_valid}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.677 [get_ports {cpu3_customInstruction_function_id[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.788 [get_ports {cpu3_customInstruction_function_id[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.677 [get_ports {cpu3_customInstruction_inputs_0[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.770 [get_ports {cpu3_customInstruction_inputs_0[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.741 [get_ports {cpu3_customInstruction_inputs_1[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.769 [get_ports {cpu3_customInstruction_inputs_1[*]}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.074 [get_ports {cpu3_customInstruction_outputs_0[*]}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.200 [get_ports {cpu3_customInstruction_outputs_0[*]}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.685 [get_ports {cpu3_customInstruction_rsp_ready}]
|
||||
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.913 [get_ports {cpu3_customInstruction_rsp_ready}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.756 [get_ports {cpu3_customInstruction_rsp_valid}]
|
||||
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.319 [get_ports {cpu3_customInstruction_rsp_valid}]
|
||||
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.058 [get_ports {jtagCtrl_capture}]
|
||||
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.420 [get_ports {jtagCtrl_capture}]
|
||||
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.423 [get_ports {jtagCtrl_enable}]
|
||||
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.374 [get_ports {jtagCtrl_enable}]
|
||||
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.313 [get_ports {jtagCtrl_reset}]
|
||||
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.436 [get_ports {jtagCtrl_reset}]
|
||||
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.379 [get_ports {jtagCtrl_shift}]
|
||||
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.399 [get_ports {jtagCtrl_shift}]
|
||||
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 0.687 [get_ports {jtagCtrl_tdi}]
|
||||
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.304 [get_ports {jtagCtrl_tdi}]
|
||||
set_input_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 2.055 [get_ports {jtagCtrl_tdo}]
|
||||
set_input_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.906 [get_ports {jtagCtrl_tdo}]
|
||||
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.351 [get_ports {jtagCtrl_update}]
|
||||
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.425 [get_ports {jtagCtrl_update}]
|
||||
|
||||
# Clock Latency Constraints
|
||||
############################
|
||||
# set_clock_latency -source -setup <board_max + 1.177> [get_ports {io_sysFbClk}]
|
||||
# set_clock_latency -source -hold <board_min + 0.785> [get_ports {io_sysFbClk}]
|
||||
# set_clock_latency -source -setup <board_max + 1.177> [get_ports {io_systemClk}]
|
||||
# set_clock_latency -source -hold <board_min + 0.785> [get_ports {io_systemClk}]
|
||||
# set_clock_latency -source -setup <board_max + 1.177> [get_ports {io_memoryClk}]
|
||||
# set_clock_latency -source -hold <board_min + 0.785> [get_ports {io_memoryClk}]
|
||||
# set_clock_latency -source -setup <board_max + 0.828> [get_ports {io_memFbClk}]
|
||||
# set_clock_latency -source -hold <board_min + 0.552> [get_ports {io_memFbClk}]
|
||||
# set_clock_latency -source -setup <board_max + 0.828> [get_ports {io_peripheralClk}]
|
||||
# set_clock_latency -source -hold <board_min + 0.552> [get_ports {io_peripheralClk}]
|
||||
# set_clock_latency -source -setup <board_max + 0.828> [get_ports {io_ddrMasters_0_clk}]
|
||||
# set_clock_latency -source -hold <board_min + 0.552> [get_ports {io_ddrMasters_0_clk}]
|
||||
# set_clock_latency -source -setup <board_max + 0.828> [get_ports {io_cfuClk}]
|
||||
# set_clock_latency -source -hold <board_min + 0.552> [get_ports {io_cfuClk}]
|
||||
Reference in New Issue
Block a user