initial commit
This commit is contained in:
402
fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_wrapper.v
Normal file
402
fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_wrapper.v
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@@ -0,0 +1,402 @@
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module EfxSapphireHpSoc_wrapper (
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input cpu0_customInstruction_cmd_valid,
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output cpu0_customInstruction_cmd_ready,
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input [9:0] cpu0_customInstruction_function_id,
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input [31:0] cpu0_customInstruction_inputs_0,
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input [31:0] cpu0_customInstruction_inputs_1,
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output cpu0_customInstruction_rsp_valid,
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input cpu0_customInstruction_rsp_ready,
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output [31:0] cpu0_customInstruction_outputs_0,
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output userInterruptB,
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output userInterruptE,
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input cpu2_customInstruction_cmd_valid,
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output cpu2_customInstruction_cmd_ready,
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input [9:0] cpu2_customInstruction_function_id,
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input [31:0] cpu2_customInstruction_inputs_0,
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input [31:0] cpu2_customInstruction_inputs_1,
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output cpu2_customInstruction_rsp_valid,
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input cpu2_customInstruction_rsp_ready,
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output [31:0] cpu2_customInstruction_outputs_0,
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input io_cfuClk,
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input io_cfuReset,
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output system_spi_0_io_sclk_write,
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output system_spi_0_io_data_0_writeEnable,
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input system_spi_0_io_data_0_read,
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output system_spi_0_io_data_0_write,
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output system_spi_0_io_data_1_writeEnable,
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input system_spi_0_io_data_1_read,
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output system_spi_0_io_data_1_write,
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output system_spi_0_io_data_2_writeEnable,
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input system_spi_0_io_data_2_read,
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output system_spi_0_io_data_2_write,
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output system_spi_0_io_data_3_writeEnable,
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input system_spi_0_io_data_3_read,
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output system_spi_0_io_data_3_write,
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output [3:0] system_spi_0_io_ss,
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output userInterruptC,
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output userInterruptH,
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input cpu1_customInstruction_cmd_valid,
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output cpu1_customInstruction_cmd_ready,
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input [9:0] cpu1_customInstruction_function_id,
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input [31:0] cpu1_customInstruction_inputs_0,
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input [31:0] cpu1_customInstruction_inputs_1,
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output cpu1_customInstruction_rsp_valid,
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input cpu1_customInstruction_rsp_ready,
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output [31:0] cpu1_customInstruction_outputs_0,
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output jtagCtrl_tdi,
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input jtagCtrl_tdo,
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output jtagCtrl_enable,
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output jtagCtrl_capture,
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output jtagCtrl_shift,
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output jtagCtrl_update,
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output jtagCtrl_reset,
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input ut_jtagCtrl_tdi,
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output ut_jtagCtrl_tdo,
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input ut_jtagCtrl_enable,
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input ut_jtagCtrl_capture,
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input ut_jtagCtrl_shift,
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input ut_jtagCtrl_update,
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input ut_jtagCtrl_reset,
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output system_uart_0_io_txd,
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input system_uart_0_io_rxd,
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output io_ddrMasters_0_aw_valid,
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input io_ddrMasters_0_aw_ready,
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output [31:0] io_ddrMasters_0_aw_payload_addr,
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output [3:0] io_ddrMasters_0_aw_payload_id,
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output [3:0] io_ddrMasters_0_aw_payload_region,
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output [7:0] io_ddrMasters_0_aw_payload_len,
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output [2:0] io_ddrMasters_0_aw_payload_size,
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output [1:0] io_ddrMasters_0_aw_payload_burst,
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output io_ddrMasters_0_aw_payload_lock,
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output [3:0] io_ddrMasters_0_aw_payload_cache,
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output [3:0] io_ddrMasters_0_aw_payload_qos,
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output [2:0] io_ddrMasters_0_aw_payload_prot,
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output io_ddrMasters_0_aw_payload_allStrb,
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output io_ddrMasters_0_w_valid,
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input io_ddrMasters_0_w_ready,
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output [127:0] io_ddrMasters_0_w_payload_data,
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output [15:0] io_ddrMasters_0_w_payload_strb,
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output io_ddrMasters_0_w_payload_last,
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input io_ddrMasters_0_b_valid,
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output io_ddrMasters_0_b_ready,
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input [3:0] io_ddrMasters_0_b_payload_id,
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input [1:0] io_ddrMasters_0_b_payload_resp,
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output io_ddrMasters_0_ar_valid,
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input io_ddrMasters_0_ar_ready,
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output [31:0] io_ddrMasters_0_ar_payload_addr,
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output [3:0] io_ddrMasters_0_ar_payload_id,
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output [3:0] io_ddrMasters_0_ar_payload_region,
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output [7:0] io_ddrMasters_0_ar_payload_len,
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output [2:0] io_ddrMasters_0_ar_payload_size,
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output [1:0] io_ddrMasters_0_ar_payload_burst,
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output io_ddrMasters_0_ar_payload_lock,
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output [3:0] io_ddrMasters_0_ar_payload_cache,
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output [3:0] io_ddrMasters_0_ar_payload_qos,
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output [2:0] io_ddrMasters_0_ar_payload_prot,
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input io_ddrMasters_0_r_valid,
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output io_ddrMasters_0_r_ready,
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input [127:0] io_ddrMasters_0_r_payload_data,
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input [3:0] io_ddrMasters_0_r_payload_id,
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input [1:0] io_ddrMasters_0_r_payload_resp,
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input io_ddrMasters_0_r_payload_last,
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input io_ddrMasters_0_clk,
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input io_ddrMasters_0_reset,
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output userInterruptF,
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output userInterruptG,
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output userInterruptA,
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output system_i2c_0_io_sda_writeEnable,
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output system_i2c_0_io_sda_write,
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input system_i2c_0_io_sda_read,
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output system_i2c_0_io_scl_writeEnable,
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output system_i2c_0_io_scl_write,
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input system_i2c_0_io_scl_read,
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input [3:0] system_gpio_0_io_read,
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output [3:0] system_gpio_0_io_write,
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output [3:0] system_gpio_0_io_writeEnable,
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output system_watchdog_hardPanic_reset,
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output userInterruptI,
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input cpu3_customInstruction_cmd_valid,
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output cpu3_customInstruction_cmd_ready,
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input [9:0] cpu3_customInstruction_function_id,
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input [31:0] cpu3_customInstruction_inputs_0,
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input [31:0] cpu3_customInstruction_inputs_1,
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output cpu3_customInstruction_rsp_valid,
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input cpu3_customInstruction_rsp_ready,
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output [31:0] cpu3_customInstruction_outputs_0,
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output userInterruptD,
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input [31:0] axiA_awaddr,
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input [7:0] axiA_awlen,
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input [2:0] axiA_awsize,
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input [1:0] axiA_awburst,
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input axiA_awlock,
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input [3:0] axiA_awcache,
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input [2:0] axiA_awprot,
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input [3:0] axiA_awqos,
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input [3:0] axiA_awregion,
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input axiA_awvalid,
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output axiA_awready,
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input [31:0] axiA_wdata,
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input [3:0] axiA_wstrb,
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input axiA_wvalid,
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input axiA_wlast,
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output axiA_wready,
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output [1:0] axiA_bresp,
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output axiA_bvalid,
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input axiA_bready,
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input [31:0] axiA_araddr,
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input [7:0] axiA_arlen,
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input [2:0] axiA_arsize,
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input [1:0] axiA_arburst,
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input axiA_arlock,
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input [3:0] axiA_arcache,
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input [2:0] axiA_arprot,
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input [3:0] axiA_arqos,
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input [3:0] axiA_arregion,
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input axiA_arvalid,
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output axiA_arready,
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output [31:0] axiA_rdata,
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output [1:0] axiA_rresp,
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output axiA_rlast,
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output axiA_rvalid,
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input axiA_rready,
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output axiAInterrupt,
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input cfg_done,
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output cfg_start,
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output cfg_sel,
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output cfg_reset,
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input io_peripheralClk,
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input io_peripheralReset,
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output io_asyncReset,
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input io_gpio_sw_n,
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input pll_peripheral_locked,
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input pll_system_locked
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);
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wire [15:0] io_apbSlave_0_PADDR;
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wire io_apbSlave_0_PSEL;
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wire io_apbSlave_0_PENABLE;
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wire io_apbSlave_0_PREADY;
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wire io_apbSlave_0_PWRITE;
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wire [31:0] io_apbSlave_0_PWDATA;
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wire [31:0] io_apbSlave_0_PRDATA;
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wire io_apbSlave_0_PSLVERROR;
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assign userInterruptG = 1'b0; //USER TO MODIFY
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assign userInterruptH = 1'b0; //USER TO MODIFY
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assign userInterruptI = 1'b0; //USER TO MODIFY
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/**/
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/* INFO: USER TO MODIFY CODES BELOW */
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/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
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/**/
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assign cpu3_customInstruction_cmd_ready = 1'b1;
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assign cpu3_customInstruction_rsp_valid = 1'b0;
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assign cpu3_customInstruction_outputs_0 = 32'd0;
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//io_cfuClk
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//io_cfyReset
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//cpu3_customInstruction_rsp_ready
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//cpu3_customInstruction_cmd_valid
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//cpu3_customInstruction_function_id
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//cpu3_customInstruction_inputs_0
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//cpu3_customInstruction_inputs_1
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/**/
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/* INFO: USER TO MODIFY CODES BELOW */
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/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
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/**/
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assign cpu0_customInstruction_cmd_ready = 1'b1;
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assign cpu0_customInstruction_rsp_valid = 1'b0;
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assign cpu0_customInstruction_outputs_0 = 32'd0;
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//io_cfuClk
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//io_cfyReset
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//cpu0_customInstruction_rsp_ready
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//cpu0_customInstruction_cmd_valid
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//cpu0_customInstruction_function_id
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//cpu0_customInstruction_inputs_0
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//cpu0_customInstruction_inputs_1
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/**/
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/* INFO: USER TO MODIFY CODES BELOW */
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/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
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/**/
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assign cpu1_customInstruction_cmd_ready = 1'b1;
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assign cpu1_customInstruction_rsp_valid = 1'b0;
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assign cpu1_customInstruction_outputs_0 = 32'd0;
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//io_cfuClk
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//io_cfyReset
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//cpu1_customInstruction_rsp_ready
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//cpu1_customInstruction_cmd_valid
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//cpu1_customInstruction_function_id
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//cpu1_customInstruction_inputs_0
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//cpu1_customInstruction_inputs_1
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/**/
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/* INFO: USER TO MODIFY CODES BELOW */
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/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
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/**/
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assign io_apbSlave_0_PREADY = 1'b1;
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assign io_apbSlave_0_PRDATA = 32'd0;
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//io_apbSlave_0_PADDR;
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//io_apbSlave_0_PSEL;
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//io_apbSlave_0_PENABLE;
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//io_apbSlave_0_PWRITE;
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//io_apbSlave_0_PWDATA;
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//io_apbSlave_0_PSLVERROR;
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/**/
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/* INFO: USER TO MODIFY CODES BELOW */
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/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
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/**/
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assign cpu2_customInstruction_cmd_ready = 1'b1;
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assign cpu2_customInstruction_rsp_valid = 1'b0;
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assign cpu2_customInstruction_outputs_0 = 32'd0;
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//io_cfuClk
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//io_cfyReset
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//cpu2_customInstruction_rsp_ready
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//cpu2_customInstruction_cmd_valid
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//cpu2_customInstruction_function_id
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//cpu2_customInstruction_inputs_0
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//cpu2_customInstruction_inputs_1
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/**/
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/* INFO: USER TO MODIFY CODES BELOW */
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/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
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/**/
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assign io_ddrMasters_0_aw_payload_addr = 32'd0;
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assign io_ddrMasters_0_aw_payload_id = 4'd0;
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assign io_ddrMasters_0_aw_payload_region = 4'd0;
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assign io_ddrMasters_0_aw_payload_len = 8'd0;
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assign io_ddrMasters_0_aw_payload_size = 3'd0;
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assign io_ddrMasters_0_aw_payload_burst = 2'd0;
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assign io_ddrMasters_0_aw_payload_lock = 1'b0;
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assign io_ddrMasters_0_aw_payload_cache = 4'd0;
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assign io_ddrMasters_0_aw_payload_qos = 4'd0;
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assign io_ddrMasters_0_aw_payload_prot = 3'd0;
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assign io_ddrMasters_0_aw_payload_allStrb = 1'b0;
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assign io_ddrMasters_0_w_valid = 1'b0;
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//io_ddrMasters_0_w_ready
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assign io_ddrMasters_0_w_payload_data = 128'd0;
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assign io_ddrMasters_0_w_payload_strb = 16'd0;
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assign io_ddrMasters_0_w_payload_last = 1'b0;
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//io_ddrMasters_0_b_valid
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assign io_ddrMasters_0_b_ready = 1'b1;
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//io_ddrMasters_0_b_payload_id
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//io_ddrMasters_0_b_payload_resp
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assign io_ddrMasters_0_ar_valid = 1'b0;
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//io_ddrMasters_0_ar_ready
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assign io_ddrMasters_0_ar_payload_addr = 32'd0;
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assign io_ddrMasters_0_ar_payload_id = 4'd0;
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assign io_ddrMasters_0_ar_payload_region = 4'd0;
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assign io_ddrMasters_0_ar_payload_len = 8'd0;
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assign io_ddrMasters_0_ar_payload_size = 3'd0;
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assign io_ddrMasters_0_ar_payload_burst = 2'd0;
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assign io_ddrMasters_0_ar_payload_lock = 1'b0;
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assign io_ddrMasters_0_ar_payload_cache = 4'd0;
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assign io_ddrMasters_0_ar_payload_qos = 4'd0;
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assign io_ddrMasters_0_ar_payload_pro = 3'd0;
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//io_ddrMasters_0_r_valid
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assign io_ddrMasters_0_r_ready = 1'b1;
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//io_ddrMasters_0_r_payload_data
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//io_ddrMasters_0_r_payload_id
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//io_ddrMasters_0_r_payload_resp
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//io_ddrMasters_0_r_payload_last
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//axi4 bridge to various I/O
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EfxSapphireHpSoc_slb u_top_peripherals(
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.userInterruptD(userInterruptD),
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.userInterruptA(userInterruptA),
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.system_watchdog_hardPanic_reset(system_watchdog_hardPanic_reset),
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.system_uart_0_io_txd(system_uart_0_io_txd),
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.system_uart_0_io_rxd(system_uart_0_io_rxd),
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.system_spi_0_io_sclk_write(system_spi_0_io_sclk_write),
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.system_spi_0_io_data_0_writeEnable(system_spi_0_io_data_0_writeEnable),
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.system_spi_0_io_data_0_read(system_spi_0_io_data_0_read),
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.system_spi_0_io_data_0_write(system_spi_0_io_data_0_write),
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.system_spi_0_io_data_1_writeEnable(system_spi_0_io_data_1_writeEnable),
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.system_spi_0_io_data_1_read(system_spi_0_io_data_1_read),
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.system_spi_0_io_data_1_write(system_spi_0_io_data_1_write),
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.system_spi_0_io_data_2_writeEnable(system_spi_0_io_data_2_writeEnable),
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.system_spi_0_io_data_2_read(system_spi_0_io_data_2_read),
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.system_spi_0_io_data_2_write(system_spi_0_io_data_2_write),
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.system_spi_0_io_data_3_writeEnable(system_spi_0_io_data_3_writeEnable),
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.system_spi_0_io_data_3_read(system_spi_0_io_data_3_read),
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.system_spi_0_io_data_3_write(system_spi_0_io_data_3_write),
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.system_spi_0_io_ss(system_spi_0_io_ss),
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.system_gpio_0_io_read(system_gpio_0_io_read),
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.system_gpio_0_io_write(system_gpio_0_io_write),
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.system_gpio_0_io_writeEnable(system_gpio_0_io_writeEnable),
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.userInterruptB(userInterruptB),
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.userInterruptE(userInterruptE),
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.io_apbSlave_0_PADDR(io_apbSlave_0_PADDR),
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.io_apbSlave_0_PSEL(io_apbSlave_0_PSEL),
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.io_apbSlave_0_PENABLE(io_apbSlave_0_PENABLE),
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.io_apbSlave_0_PREADY(io_apbSlave_0_PREADY),
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.io_apbSlave_0_PWRITE(io_apbSlave_0_PWRITE),
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.io_apbSlave_0_PWDATA(io_apbSlave_0_PWDATA),
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.io_apbSlave_0_PRDATA(io_apbSlave_0_PRDATA),
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.io_apbSlave_0_PSLVERROR(io_apbSlave_0_PSLVERROR),
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.system_i2c_0_io_sda_writeEnable(system_i2c_0_io_sda_writeEnable),
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.system_i2c_0_io_sda_write(system_i2c_0_io_sda_write),
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.system_i2c_0_io_sda_read(system_i2c_0_io_sda_read),
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.system_i2c_0_io_scl_writeEnable(system_i2c_0_io_scl_writeEnable),
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.system_i2c_0_io_scl_write(system_i2c_0_io_scl_write),
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.system_i2c_0_io_scl_read(system_i2c_0_io_scl_read),
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.userInterruptF(userInterruptF),
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||||
.jtagCtrl_tdi(jtagCtrl_tdi),
|
||||
.jtagCtrl_tdo(jtagCtrl_tdo),
|
||||
.jtagCtrl_enable(jtagCtrl_enable),
|
||||
.jtagCtrl_capture(jtagCtrl_capture),
|
||||
.jtagCtrl_shift(jtagCtrl_shift),
|
||||
.jtagCtrl_update(jtagCtrl_update),
|
||||
.jtagCtrl_reset(jtagCtrl_reset),
|
||||
.ut_jtagCtrl_tdi(ut_jtagCtrl_tdi),
|
||||
.ut_jtagCtrl_tdo(ut_jtagCtrl_tdo),
|
||||
.ut_jtagCtrl_enable(ut_jtagCtrl_enable),
|
||||
.ut_jtagCtrl_capture(ut_jtagCtrl_capture),
|
||||
.ut_jtagCtrl_shift(ut_jtagCtrl_shift),
|
||||
.ut_jtagCtrl_update(ut_jtagCtrl_update),
|
||||
.ut_jtagCtrl_reset(ut_jtagCtrl_reset),
|
||||
.userInterruptC(userInterruptC),
|
||||
.axiA_awvalid(axiA_awvalid),
|
||||
.axiA_awready(axiA_awready),
|
||||
.axiA_awaddr(axiA_awaddr),
|
||||
.axiA_awlen(axiA_awlen),
|
||||
.axiA_awsize(axiA_awsize),
|
||||
.axiA_awcache(axiA_awcache),
|
||||
.axiA_awprot(axiA_awprot),
|
||||
.axiA_wvalid(axiA_wvalid),
|
||||
.axiA_wready(axiA_wready),
|
||||
.axiA_wdata(axiA_wdata),
|
||||
.axiA_wstrb(axiA_wstrb),
|
||||
.axiA_wlast(axiA_wlast),
|
||||
.axiA_bvalid(axiA_bvalid),
|
||||
.axiA_bready(axiA_bready),
|
||||
.axiA_bresp(axiA_bresp),
|
||||
.axiA_arvalid(axiA_arvalid),
|
||||
.axiA_arready(axiA_arready),
|
||||
.axiA_araddr(axiA_araddr),
|
||||
.axiA_arlen(axiA_arlen),
|
||||
.axiA_arsize(axiA_arsize),
|
||||
.axiA_arcache(axiA_arcache),
|
||||
.axiA_arprot(axiA_arprot),
|
||||
.axiA_rvalid(axiA_rvalid),
|
||||
.axiA_rready(axiA_rready),
|
||||
.axiA_rdata(axiA_rdata),
|
||||
.axiA_rresp(axiA_rresp),
|
||||
.axiA_rlast(axiA_rlast),
|
||||
.axiAInterrupt(axiAInterrupt),
|
||||
.cfg_done(cfg_done),
|
||||
.cfg_start(cfg_start),
|
||||
.cfg_sel(cfg_sel),
|
||||
.cfg_reset(cfg_reset),
|
||||
.io_peripheralClk(io_peripheralClk),
|
||||
.io_peripheralReset(io_peripheralReset),
|
||||
.io_asyncReset(io_asyncReset),
|
||||
.io_gpio_sw_n(io_gpio_sw_n),
|
||||
.pll_peripheral_locked(pll_peripheral_locked),
|
||||
.pll_system_locked(pll_system_locked)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user