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Byron Lathi
2026-04-14 21:34:37 -07:00
commit 50f8791588
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fpga/ip/gAXIS_1to3_switch/axi_interconnect.vh Normal file
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localparam M_BASE_ADDR = {32'h41000000,32'h40000000,32'h30000000,32'h20000000,32'h11100000,32'h1100000,32'h1000000,32'h0};
localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd16,32'd16,32'd24};