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Byron Lathi
2026-04-14 21:34:37 -07:00
commit 50f8791588
181 changed files with 344781 additions and 0 deletions
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71
fpga/ip/gDMA/source/dma_config.json Normal file
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{
"name": "EfxDMA",
"efinix_ddr": false,
"with_sg_bus": false,
"with_ddr_write_queue": false,
"with_ddr_read_queue": false,
"ctrl": {
"asynchronous": true
},
"buffer": {
"bank_count": 2,
"bank_width": 64,
"bank_words": 512
},
"read": {
"address_width": 32,
"data_width_external": 128,
"data_width_internal": 128
},
"write": {
"address_width": 32,
"data_width_external": 128,
"data_width_internal": 128
},
"channels": {
"c0": {
"progress_probe": true,
"direct_ctrl_capable": true,
"linked_list_capable": true,
"memory_to_memory": false,
"inputs": [
"dat0_i"
],
"half_completion_interrupt": false,
"self_restart_capable": false,
"bytes_per_burst": 1024,
"buffer_address": 0,
"buffer_size": 4096
},
"c1": {
"progress_probe": true,
"direct_ctrl_capable": true,
"linked_list_capable": true,
"memory_to_memory": false,
"outputs": [
"dat1_o"
],
"half_completion_interrupt": false,
"self_restart_capable": false,
"bytes_per_burst": 1024,
"buffer_address": 4096,
"buffer_size": 4096
}
},
"inputs": {
"dat0_i": {
"data_width": 8,
"tid_width": 0,
"tdest_width": 4,
"asynchronous": true
}
},
"outputs": {
"dat1_o": {
"data_width": 8,
"tid_width": 0,
"tdest_width": 4,
"asynchronous": true
}
}
}