bslathi19/fpga6502
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

initial commit

Browse Source
This commit is contained in:
Byron Lathi
2026-04-14 21:34:37 -07:00
commit 50f8791588
181 changed files with 344781 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

498
fpga/ip/gTSE/T120F324_devkit/DaulClkFifo.v Normal file
View File

@@ -0,0 +1,498 @@
`timescale 1ns/100ps
module DC_FIFO
# (
parameter FIFO_MODE = "Normal" , //"Normal"; //"ShowAhead"
parameter DATA_WIDTH = 8 ,
parameter FIFO_DEPTH = 512 ,
parameter AW_C = $clog2(FIFO_DEPTH),
parameter DW_C = DATA_WIDTH ,
parameter DD_C = 2**AW_C
)
(
//System Signal
input Reset , //System Reset
//Write Signal
input WrClk , //(I)Wirte Clock
input WrEn , //(I)Write Enable
output [AW_C-1:0] WrDNum , //(O)Write Data Number In Fifo
output WrFull , //(I)Write Full
input [DW_C -1:0] WrData , //(I)Write Data
//Read Signal
input RdClk , //(I)Read Clock
input RdEn , //(I)Read Enable
output [AW_C-1:0] RdDNum , //(O)Radd Data Number In Fifo
output RdEmpty , //(O)Read FifoEmpty
output [DW_C-1 :0] RdData //(O)Read Data
);
//Define Parameter
///////////////////////////////////////////////////////////////
localparam TCo_C = 0 ;
reg [1:0] WrClkRstGen = 2'h3;
reg [1:0] RdClkRstGen = 2'h3;
always @( posedge WrClk or posedge Reset)
begin
if (Reset) WrClkRstGen <= # TCo_C 2'h3;
else
begin
WrClkRstGen[0] <= # TCo_C 1'h0;
WrClkRstGen[1] <= # TCo_C (&RdClkRstGen);
end
end
wire WrClkRst = WrClkRstGen[1];
///////////////////////////////////////////////////
always @( posedge RdClk or posedge Reset)
begin
if (Reset) RdClkRstGen <= # TCo_C 2'h3;
else
begin
RdClkRstGen[0] <= # TCo_C 1'h0;
RdClkRstGen[1] <= # TCo_C (&WrClkRstGen);
end
end
wire RdClkRst = RdClkRstGen[1];
///////////////////////////////////////////////////
wire FifoWrEn = WrEn;
wire [AW_C :0] WrAddrCnt ;
wire [AW_C :0] FifoWrAddr ;
wire FifoWrFull ;
FifoAddrCnt # ( .CounterWidth_C (AW_C))
U1_WrAddrCnt
(
//System Signal
.Reset ( WrClkRst ) , //System Reset
.SysClk ( WrClk ) , //System Clock
//Counter Signal
.ClkEn ( FifoWrEn ) , //(I)Clock Enable
.FifoFlag ( FifoWrFull ) , //(I)Fifo Flag
.AddrCnt ( WrAddrCnt ) , //(O)Address Counter
.Addess ( FifoWrAddr ) //(O)Address Output
);
///////////////////////////////////////////////////
reg [DW_C-1:0] FifoBuff [DD_C-1:0];
always @( posedge WrClk)
begin
if (WrEn & (~WrFull))
begin
FifoBuff[FifoWrAddr[AW_C-1:0]] <= # TCo_C WrData;
end
end
///////////////////////////////////////////////////
///////////////////////////////////////////////////
wire FifoEmpty ;
wire FifoRdEn ;
wire [AW_C :0] RdAddrCnt ;
wire [AW_C :0] FifoRdAddr ;
FifoAddrCnt #( .CounterWidth_C (AW_C))
U2_RdAddrCnt
(
//System Signal
.Reset ( RdClkRst ) , //System Reset
.SysClk ( RdClk ) , //System Clock
//Counter Signal
.ClkEn ( FifoRdEn ) , //(I)Clock Enable
.FifoFlag ( FifoEmpty ) , //(I)Fifo Flag
.AddrCnt ( RdAddrCnt ) , //(O)Address Counter
.Addess ( FifoRdAddr ) //(O)Address Output
);
///////////////////////////////////////////////////
reg [DW_C-1 :0] FifoRdData ;
always @( posedge RdClk)
begin
if (FifoRdEn) FifoRdData <= # TCo_C FifoBuff[FifoRdAddr[AW_C-1:0]];
end
///////////////////////////////////////////////////
assign RdData = FifoRdData ; //(O)Read Data
reg [AW_C:0] WrRdAddr = {AW_C+1{1'h0}};
always @( posedge WrClk)
begin
if (WrClkRst) WrRdAddr <= # TCo_C {AW_C+1{1'h0}} ;
else WrRdAddr <= # TCo_C FifoRdAddr [AW_C:0] ;
end
///////////////////////////////////////////////////////////
wire [AW_C-1:0] WrRdAHex;
wire [AW_C-1:0] WrWrAHex;
GrayDecode #(AW_C) WRAGray2Hex (WrRdAddr [AW_C-1:0] , WrRdAHex[AW_C-1:0]);
GrayDecode #(AW_C) WWAGray2Hex (FifoWrAddr [AW_C-1:0] , WrWrAHex[AW_C-1:0]);
///////////////////////////////////////////////////////////
reg [AW_C-1:0] WrAddrDiff;
always @( posedge WrClk)
begin
if (WrFull) WrAddrDiff <= # TCo_C {AW_C{1'h1}} ;
else WrAddrDiff <= # TCo_C (WrWrAHex - WrRdAHex) ;
end
///////////////////////////////////////////////////////////
assign WrDNum = WrAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo
reg [AW_C:0] WrRdAddrReg = {AW_C+1{1'h0}};
always @( posedge WrClk)
begin
if ( WrClkRst) WrRdAddrReg <= # TCo_C {AW_C+1{1'h0}} ;
else WrRdAddrReg <= # TCo_C WrRdAddr[AW_C : 0] ;
end
///////////////////////////////////////////////////////////
reg RdAddrChg = 1'h0;
reg WrFullClr = 1'h0;
always @( posedge WrClk)
begin
if ( WrClkRst) RdAddrChg <= # TCo_C 1'h0 ;
else RdAddrChg <= # TCo_C (FifoWrFull & (WrRdAddr[AW_C-1:0] != WrRdAddrReg[AW_C-1:0]));
end
always @( posedge WrClk)
begin
if ( WrClkRst) WrFullClr <= # TCo_C 1'h0 ;
else WrFullClr <= # TCo_C (FifoWrFull & RdAddrChg);
end
///////////////////////////////////////////////////////////
reg RdAHighNext = 1'h0;
wire RdAHighRise = (~WrRdAddrReg[AW_C-1]) & WrRdAddr[AW_C-1];
always @( posedge WrClk)
begin
if (WrClkRst ) RdAHighNext <= # TCo_C 1'h0 ;
else if (RdAHighRise) RdAHighNext <= # TCo_C (~WrRdAddr[AW_C]) ;
end
///////////////////////////////////////////////////
wire FullCalc = (WrAddrCnt[AW_C-1:0] == WrRdAddr[AW_C-1:0])
&& (WrAddrCnt[AW_C ] != (WrRdAddr[AW_C-1] ? WrRdAddrReg[AW_C] : RdAHighNext) );
///////////////////////////////////////////////////
reg FullFlag = 1'h0;
always @( posedge WrClk)
begin
if (WrClkRst) FullFlag <= # TCo_C 1'h0;
else if (FullFlag) FullFlag <= # TCo_C (~WrFullClr);
else if (FifoWrEn) FullFlag <= # TCo_C FullCalc;
end
assign FifoWrFull = FullFlag;
///////////////////////////////////////////////////
assign WrFull = FifoWrFull ; //(I)Write Full
reg [AW_C :0] RdWrAddr = {AW_C+1{1'h0}};
always @( posedge RdClk)
begin
if (RdClkRst ) RdWrAddr <= # TCo_C {AW_C+1{1'h0}} ;
else RdWrAddr <= # TCo_C FifoWrAddr [AW_C:0] ;
end
///////////////////////////////////////////////////////////
wire [AW_C-1:0] RdWrAHex;
wire [AW_C-1:0] RdRdAHex;
GrayDecode # (AW_C) RWAGray2Hex (RdWrAddr [AW_C-1:0] , RdWrAHex[AW_C-1:0] );
GrayDecode # (AW_C) RRAGray2Hex (FifoRdAddr [AW_C-1:0] , RdRdAHex[AW_C-1:0] );
///////////////////////////////////////////////////////////
reg [AW_C-1:0] RdAddrDiff;
always @( posedge RdClk)
begin
if (RdEmpty ) RdAddrDiff <= # TCo_C {AW_C{1'h0}} ;
else RdAddrDiff <= # TCo_C (RdWrAHex - RdRdAHex) ;
end
///////////////////////////////////////////////////////////
assign RdDNum = RdAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo
reg [AW_C:0] RdWrAddrReg = {AW_C+1{1'h0}};
always @( posedge RdClk)
begin
if (RdClkRst) RdWrAddrReg <= # TCo_C {AW_C+1{1'h0}} ;
else RdWrAddrReg <= # TCo_C RdWrAddr [AW_C:0] ;
end
///////////////////////////////////////////////////////////
reg WrAddrChg = 1'h0;
reg EmptyClr = 1'h0;
always @( posedge RdClk)
begin
if (RdClkRst) WrAddrChg <= # TCo_C 1'h0 ;
else WrAddrChg <= # TCo_C FifoEmpty & (RdWrAddr[AW_C-1:0] != RdWrAddrReg[AW_C-1:0]);
end
always @( posedge RdClk)
begin
if (RdClkRst) EmptyClr <= # TCo_C 1'h0;
else EmptyClr <= # TCo_C (FifoEmpty & WrAddrChg);
end
///////////////////////////////////////////////////////////
reg WrAHighNext = 1'h0;
wire WrAHighRise = (~RdWrAddrReg[AW_C-1]) & RdWrAddr[AW_C-1];
always @( posedge RdClk)
begin
if (RdClkRst) WrAHighNext <= # TCo_C 1'h0 ;
else if (WrAHighRise) WrAHighNext <= # TCo_C (~RdWrAddr[AW_C]);
end
///////////////////////////////////////////////////////////
wire EmptyCalc = (RdAddrCnt[AW_C-1:0] == RdWrAddr[AW_C-1:0])
&& (RdAddrCnt[AW_C ] == (RdWrAddr[AW_C-1] ? RdWrAddrReg[AW_C] : WrAHighNext));
///////////////////////////////////////////////////////////
reg EmptyFlag = 1'h1;
always @( posedge RdClk)
begin
if (RdClkRst) EmptyFlag <= # TCo_C 1'h1;
else if (EmptyFlag) EmptyFlag <= # TCo_C (~EmptyClr);
else if (FifoRdEn) EmptyFlag <= # TCo_C EmptyCalc;
end
assign FifoEmpty = EmptyFlag;
///////////////////////////////////////////////////////////
reg EmptyReg = 1'h0;
always @( posedge RdClk )
begin
if (RdClkRst) EmptyReg <= # TCo_C 1'h1;
else if (FifoRdEn) EmptyReg <= # TCo_C FifoEmpty;
end
///////////////////////////////////////////////////////////
assign RdEmpty = (FIFO_MODE == "ShowAhead") ? EmptyReg : FifoEmpty; //(O)Read FifoEmpty
reg RdFirst = 1'h0;
always @( posedge RdClk)
begin
if (FIFO_MODE == "ShowAhead")
begin
if (RdClkRst) RdFirst <= # TCo_C 1'h0 ;
else if (RdFirst) RdFirst <= # TCo_C 1'h0 ;
else if (EmptyClr) RdFirst <= # TCo_C RdEmpty ;
end
else RdFirst <= # TCo_C 1'h0 ;
end
///////////////////////////////////////////////////////////
assign FifoRdEn = RdEn || RdFirst ;
///////////////////////////////////////////////////////////
//666666666666666666666666666666666666666666666666666666666
endmodule
//////////////// DaulClkFifo //////////////////////////////
///////////////// FifoAddrCnt /////////////////////////////
module FifoAddrCnt
# (
parameter CounterWidth_C = 9 ,
parameter CW_C = CounterWidth_C
)
(
//System Signal
input Reset , //System Reset
input SysClk , //System Clock
//Counter Signal
input ClkEn , //(I)Clock Enable
input FifoFlag , //(I)Fifo Flag
output [CW_C:0] AddrCnt , //(O)Address Counter
output [CW_C:0] Addess //(O)Address Output
);
//Define Parameter
///////////////////////////////////////////////////////////
localparam TCo_C = 1;
wire [CW_C-1:0] GrayAddrCnt;
wire CarryOut;
GrayCnt #(.CounterWidth_C (CW_C))
U1_AddrCnt
(
//System Signal
.Reset ( Reset ), //System Reset
.SysClk ( SysClk ), //System Clock
//Counter Signal
.SyncClr ( 1'h0 ), //(I)Sync Clear
.ClkEn ( ClkEn ), //(I)Clock Enable
.CarryIn ( ~FifoFlag ), //(I)Carry input
.CarryOut ( CarryOut ), //(O)Carry output
.Count ( GrayAddrCnt ) //(O)Counter Value Output
);
///////////////////////////////////////////////////////////
reg CntHighBit;
always @( posedge SysClk )
begin
if (Reset) CntHighBit <= # TCo_C 1'h0;
else if (ClkEn) CntHighBit <= # TCo_C CntHighBit + CarryOut;
end
///////////////////////////////////////////////////////////
reg [CW_C:0] AddrOut; //(O)Address Output
always @(posedge SysClk)
begin
if (Reset) AddrOut <= # TCo_C {CW_C{1'h0}};
else if (ClkEn) AddrOut <= # TCo_C FifoFlag ? AddrOut : AddrCnt;
end
///////////////////////////////////////////////////////////
assign AddrCnt = {CntHighBit , GrayAddrCnt} ; //(O)Address Counter
assign Addess = AddrOut ; //(O)Address Output
//111111111111111111111111111111111111111111111111111111111
endmodule
/////////////////// FifoAddrCnt //////////////////////////
module GrayCnt
# (
parameter CounterWidth_C = 9 ,
parameter CW_C = CounterWidth_C
)
(
//System Signal
input Reset , //System Reset
input SysClk , //System Clock
//Counter Signal
input SyncClr , //(I)Sync Clear
input ClkEn , //(I)Clock Enable
input CarryIn , //(I)Carry input
output CarryOut , //(O)Carry output
output [CW_C-1:0] Count //(O)Counter Value Output
);
//Define Parameter
///////////////////////////////////////////////////////////
localparam TCo_C = 1;
wire [CW_C:0 ] CryIn ;
wire [CW_C-1:0] CryOut ;
reg [CW_C-1:0] GrayCnt;
assign CryIn[0] = CarryIn;
genvar i;
generate
for(i=0;i<CW_C;i=i+1)
begin : GrayCnt_CrayCntUnit
//////////////
always @( posedge SysClk )
begin
if (Reset) GrayCnt[i] <= # TCo_C (i>1) ? 1'h0: 1'h1 ;
else if (SyncClr) GrayCnt[i] <= # TCo_C (i>1) ? 1'h0: 1'h1 ;
else if (ClkEn) GrayCnt[i] <= # TCo_C GrayCnt[i] + CryIn[i];
end
//////////////
if (i==0)
begin
assign CryOut[0] = GrayCnt[0] && CarryIn;
assign CryIn [1] = ~GrayCnt[0] && CarryIn;
end
else
begin
assign CryOut[i ] = CryOut[ 0] && (~|GrayCnt[i:1]);
assign CryIn [i+1] = CryOut[i-1] && GrayCnt[i ] ;
end
end
endgenerate
wire GrayCarry = CryOut[CW_C-2];
///////////////////////////////////////////////////////////
reg CntHigh = 1'h0;
always @( posedge SysClk)
begin
if (Reset) CntHigh <= # TCo_C 1'h0;
else if (ClkEn) CntHigh <= # TCo_C (CntHigh + GrayCarry);
end
///////////////////////////////////////////////////////////
assign Count = {CntHigh , GrayCnt[CW_C-1:1]} ; //(O)Counter Value Output
assign CarryOut = CntHigh & GrayCarry ; //(O)Carry output
///////////////////////////////////////////////////////////
//111111111111111111111111111111111111111111111111111111111
endmodule
////////////////////// GrayCnt ////////////////////////////
module GrayDecode
# (
parameter DataWidht_C = 8
)
(
input [DataWidht_C-1:0] GrayIn,
output [DataWidht_C-1:0] HexOut
);
//Define Parameter
///////////////////////////////////////////////////////////////
parameter TCo_C = 1;
localparam DW_C = DataWidht_C;
///////////////////////////////////////////////////////////////
reg [DW_C-1:0] Hex;
integer i;
always @ (GrayIn)
begin
Hex[DW_C-1]=GrayIn[DW_C-1];
for(i=DW_C-2;i>=0;i=i-1) Hex[i]=Hex[i+1]^GrayIn[i];
end
assign HexOut = Hex;
///////////////////////////////////////////////////////////////
endmodule

215
fpga/ip/gTSE/T120F324_devkit/apb3_2_axi4_lite.v Normal file
View File

@@ -0,0 +1,215 @@
/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module apb3_2_axi4_lite#(
parameter ADDR_WTH = 10
)
(
//Globle Signals
input clk,
input rstn,
//APB3 Slave Interface
input [ADDR_WTH-1:0] s_apb3_paddr,
input s_apb3_psel,
input s_apb3_penable,
output reg s_apb3_pready,
input s_apb3_pwrite,//0:rd; 1:wr;
input [31:0] s_apb3_pwdata,
output reg [31:0] s_apb3_prdata,
output reg s_apb3_pslverror,
//AXI4-Lite Master Interface
output reg [ADDR_WTH-1:0] m_axi_awaddr,//Write Address. byte address.
output reg m_axi_awvalid,//Write address valid.
input m_axi_awready,//Write address ready.
output reg [31:0] m_axi_wdata,//Write data bus.
output reg m_axi_wvalid,//Write valid.
input m_axi_wready,//Write ready.
input [1:0] m_axi_bresp,//Write response.
input m_axi_bvalid,//Write response valid.
output wire m_axi_bready,//Response ready.
output reg [ADDR_WTH-1:0] m_axi_araddr,//Read address. byte address.
output reg m_axi_arvalid,//Read address valid.
input m_axi_arready,//Read address ready.
input [1:0] m_axi_rresp,//Read response.
input [31:0] m_axi_rdata,//Read data.
input m_axi_rvalid,//Read valid.
output wire m_axi_rready//Read ready.
);
// Parameter Define
parameter State_idle = 3'd0;
parameter State_wsetup = 3'd1;
parameter State_rsetup = 3'd2;
parameter State_ready = 3'd3;
parameter State_err = 3'd4;
// Register Define
reg [2:0] cur_state;
reg [2:0] next_state;
reg [7:0] timeout_cnt;
// Wire Define
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
/*----------------------- FSM Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
cur_state <= State_idle;
else
cur_state <= next_state;
end
always @(*)
begin
case(cur_state)
State_idle :
if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
next_state = State_wsetup;
else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0))
next_state = State_rsetup;
else
next_state = State_idle;
State_wsetup :
if((m_axi_awvalid == 1'b0) && (m_axi_wvalid == 1'b0))
next_state = State_ready;
else if(timeout_cnt[7] == 1'b1)
next_state = State_err;
else
next_state = State_wsetup;
State_rsetup :
if(m_axi_rvalid == 1'b1)
next_state = State_ready;
else if(timeout_cnt[7] == 1'b1)
next_state = State_err;
else
next_state = State_rsetup;
State_ready :
next_state = State_idle;
State_err :
next_state = State_idle;
default :
next_state = State_idle;
endcase
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
timeout_cnt <= 8'h0;
else if((cur_state == State_wsetup) || (cur_state == State_rsetup))
timeout_cnt <= timeout_cnt + 1'b1;
else
timeout_cnt <= 8'h0;
end
/*----------------------- APB3 Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
s_apb3_pready <= 1'b0;
else if((cur_state == State_ready) || (cur_state == State_err))
s_apb3_pready <= 1'b1;
else
s_apb3_pready <= 1'b0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
s_apb3_pslverror <= 1'b0;
else if(cur_state == State_err)
s_apb3_pslverror <= 1'b1;
else
s_apb3_pslverror <= 1'b0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
s_apb3_prdata <= 32'h0;
else if(m_axi_rvalid == 1'b1)
s_apb3_prdata <= m_axi_rdata;
end
/*----------------------- AXI4-Lite Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
m_axi_awaddr <= {ADDR_WTH{1'b0}};
else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
m_axi_awaddr <= s_apb3_paddr;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
m_axi_awvalid <= 1'b0;
else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
m_axi_awvalid <= 1'b1;
else if((m_axi_awready == 1'b1) || (cur_state == State_idle))
m_axi_awvalid <= 1'b0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
m_axi_wdata <= 32'h0;
else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
m_axi_wdata <= s_apb3_pwdata;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
m_axi_wvalid <= 1'b0;
else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
m_axi_wvalid <= 1'b1;
else if((m_axi_wready == 1'b1) || (cur_state == State_idle))
m_axi_wvalid <= 1'b0;
end
assign m_axi_bready = 1'b1;
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
m_axi_araddr <= {ADDR_WTH{1'b0}};
else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0))
m_axi_araddr <= s_apb3_paddr;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
m_axi_arvalid <= 1'b0;
else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0))
m_axi_arvalid <= 1'b1;
else if((m_axi_arready == 1'b1) || (cur_state == State_idle))
m_axi_arvalid <= 1'b0;
end
assign m_axi_rready = 1'b1;
endmodule

61
fpga/ip/gTSE/T120F324_devkit/axi4_st_mux.v Normal file
View File

@@ -0,0 +1,61 @@
/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module axi4_st_mux
(
//Globle Signals
input mux_select,
//Mux In 0 Interface
input [7:0] tdata0,
input tvalid0,
input tlast0,
input tuser0,
output wire tready0,
//Mux In 1 Interface
input [7:0] tdata1,
input tvalid1,
input tlast1,
input tuser1,
output wire tready1,
//Mux Out Interface
output wire [7:0] tdata,
output wire tvalid,
output wire tlast,
output wire tuser,
input tready
);
// Parameter Define
// Register Define
// Wire Define
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
assign tdata = (mux_select) ? tdata1 : tdata0;
assign tvalid = (mux_select) ? tvalid1 : tvalid0;
assign tlast = (mux_select) ? tlast1 : tlast0;
assign tuser = (mux_select) ? tuser1 : tuser0;
assign tready0 = (mux_select) ? 1'b1 : tready;
assign tready1 = (mux_select) ? tready : 1'b1;
endmodule

9844
fpga/ip/gTSE/T120F324_devkit/gTSE.sv Normal file
View File

File diff suppressed because it is too large Load Diff

61
fpga/ip/gTSE/T120F324_devkit/gTSE_define.svh Normal file
View File

@@ -0,0 +1,61 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.288.2.10
// IP Version: 7.1
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam VERSION = 16;
localparam TXFIFO_EN = 1'b1;
localparam RXFIFO_EN = 1'b1;
localparam TXFIFO_DTH = 4096;
localparam RXFIFO_DTH = 4096;
localparam PHY_INTF_MODE = 0;
localparam AXIS_DW = 8;
localparam RGMII_RXC_EDGE = 1'b1;
localparam RGMII_TXC_DLY = 1'b1;
localparam INTER_PACKET_GAP = 6'd12;
localparam MTU_FRAME_LENGTH = 16'd1518;
localparam MAC_SOURCE_ADDRESS = 48'd0;
localparam ENABLE_BROADCAST_FILTERING = 1'b1;
localparam LOOPBACK_EN = 1'b1;
localparam APBIF = 1'b0;
localparam FAMILY = "TITANIUM";

2
fpga/ip/gTSE/T120F324_devkit/header.v Normal file
View File

@@ -0,0 +1,2 @@
//`define SOFT_TAP

8192
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin Normal file
View File

File diff suppressed because it is too large Load Diff

8192
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin Normal file
View File

File diff suppressed because it is too large Load Diff

8192
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin Normal file
View File

File diff suppressed because it is too large Load Diff

8192
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin Normal file
View File

File diff suppressed because it is too large Load Diff

14222
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire.v Normal file
View File

File diff suppressed because it is too large Load Diff

45
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_define.vh Normal file
View File

@@ -0,0 +1,45 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2022.1.196
// IP Version: 2.2
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////

76
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.v Normal file
View File

@@ -0,0 +1,76 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
sapphire u_sapphire(
.io_systemClk ( io_systemClk ),
.jtagCtrl_enable ( jtagCtrl_enable ),
.jtagCtrl_tdi ( jtagCtrl_tdi ),
.jtagCtrl_capture ( jtagCtrl_capture ),
.jtagCtrl_shift ( jtagCtrl_shift ),
.jtagCtrl_update ( jtagCtrl_update ),
.jtagCtrl_reset ( jtagCtrl_reset ),
.jtagCtrl_tdo ( jtagCtrl_tdo ),
.jtagCtrl_tck ( jtagCtrl_tck ),
.system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ),
.system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ),
.system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ),
.system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ),
.system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ),
.system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ),
.system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ),
.system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ),
.system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ),
.system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ),
.system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ),
.system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ),
.system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ),
.system_spi_0_io_ss ( system_spi_0_io_ss ),
.io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ),
.io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ),
.io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ),
.io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ),
.io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ),
.io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ),
.io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ),
.io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ),
.io_asyncReset ( io_asyncReset ),
.io_systemReset ( io_systemReset ),
.system_uart_0_io_txd ( system_uart_0_io_txd ),
.system_uart_0_io_rxd ( system_uart_0_io_rxd )
);

118
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.vhd Normal file
View File

@@ -0,0 +1,118 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2022 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
------------- Begin Cut here for COMPONENT Declaration ------
COMPONENT sapphire is
PORT (
io_systemClk : in std_logic;
jtagCtrl_enable : in std_logic;
jtagCtrl_tdi : in std_logic;
jtagCtrl_capture : in std_logic;
jtagCtrl_shift : in std_logic;
jtagCtrl_update : in std_logic;
jtagCtrl_reset : in std_logic;
jtagCtrl_tdo : out std_logic;
jtagCtrl_tck : in std_logic;
system_spi_0_io_data_0_read : in std_logic;
system_spi_0_io_data_0_write : out std_logic;
system_spi_0_io_data_0_writeEnable : out std_logic;
system_spi_0_io_data_1_read : in std_logic;
system_spi_0_io_data_1_write : out std_logic;
system_spi_0_io_data_1_writeEnable : out std_logic;
system_spi_0_io_data_2_read : in std_logic;
system_spi_0_io_data_2_write : out std_logic;
system_spi_0_io_data_2_writeEnable : out std_logic;
system_spi_0_io_data_3_read : in std_logic;
system_spi_0_io_data_3_write : out std_logic;
system_spi_0_io_data_3_writeEnable : out std_logic;
system_spi_0_io_sclk_write : out std_logic;
system_spi_0_io_ss : out std_logic_vector(0 to 0);
io_apbSlave_0_PADDR : out std_logic_vector(15 downto 0);
io_apbSlave_0_PENABLE : out std_logic;
io_apbSlave_0_PRDATA : in std_logic_vector(31 downto 0);
io_apbSlave_0_PREADY : in std_logic;
io_apbSlave_0_PSEL : out std_logic;
io_apbSlave_0_PSLVERROR : in std_logic;
io_apbSlave_0_PWDATA : out std_logic_vector(31 downto 0);
io_apbSlave_0_PWRITE : out std_logic;
io_asyncReset : in std_logic;
io_systemReset : out std_logic;
system_uart_0_io_txd : out std_logic;
system_uart_0_io_rxd : in std_logic);
END COMPONENT;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_sapphire : sapphire
PORT MAP (
io_systemClk => io_systemClk,
jtagCtrl_enable => jtagCtrl_enable,
jtagCtrl_tdi => jtagCtrl_tdi,
jtagCtrl_capture => jtagCtrl_capture,
jtagCtrl_shift => jtagCtrl_shift,
jtagCtrl_update => jtagCtrl_update,
jtagCtrl_reset => jtagCtrl_reset,
jtagCtrl_tdo => jtagCtrl_tdo,
jtagCtrl_tck => jtagCtrl_tck,
system_spi_0_io_data_0_read => system_spi_0_io_data_0_read,
system_spi_0_io_data_0_write => system_spi_0_io_data_0_write,
system_spi_0_io_data_0_writeEnable => system_spi_0_io_data_0_writeEnable,
system_spi_0_io_data_1_read => system_spi_0_io_data_1_read,
system_spi_0_io_data_1_write => system_spi_0_io_data_1_write,
system_spi_0_io_data_1_writeEnable => system_spi_0_io_data_1_writeEnable,
system_spi_0_io_data_2_read => system_spi_0_io_data_2_read,
system_spi_0_io_data_2_write => system_spi_0_io_data_2_write,
system_spi_0_io_data_2_writeEnable => system_spi_0_io_data_2_writeEnable,
system_spi_0_io_data_3_read => system_spi_0_io_data_3_read,
system_spi_0_io_data_3_write => system_spi_0_io_data_3_write,
system_spi_0_io_data_3_writeEnable => system_spi_0_io_data_3_writeEnable,
system_spi_0_io_sclk_write => system_spi_0_io_sclk_write,
system_spi_0_io_ss => system_spi_0_io_ss,
io_apbSlave_0_PADDR => io_apbSlave_0_PADDR,
io_apbSlave_0_PENABLE => io_apbSlave_0_PENABLE,
io_apbSlave_0_PRDATA => io_apbSlave_0_PRDATA,
io_apbSlave_0_PREADY => io_apbSlave_0_PREADY,
io_apbSlave_0_PSEL => io_apbSlave_0_PSEL,
io_apbSlave_0_PSLVERROR => io_apbSlave_0_PSLVERROR,
io_apbSlave_0_PWDATA => io_apbSlave_0_PWDATA,
io_apbSlave_0_PWRITE => io_apbSlave_0_PWRITE,
io_asyncReset => io_asyncReset,
io_systemReset => io_systemReset,
system_uart_0_io_txd => system_uart_0_io_txd,
system_uart_0_io_rxd => system_uart_0_io_rxd);
------------------------ End INSTANTIATION Template ---------

156
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/settings.json Normal file
View File

@@ -0,0 +1,156 @@
{
"args": [
"-o",
"sapphire",
"--base_path",
"/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "soc",
"name": "efx_soc",
"version": "2.2"
}
],
"conf": {
"HexFile_PathEnable": "0",
"HexFile_Path": "",
"APBSlave0_Size": "65536",
"DEVKIT_CUSTOM": "sapphireBoard_rev0",
"LDSize": "124",
"LDStackSize": "4",
"DEVKIT": "2",
"DEBUG": "1",
"SOFT_TAP": "0",
"TAP_COUNT": "0",
"TAP_SEL": "8",
"Frequency": "50",
"PeriFrequencyEnable": "0",
"PeriFrequency": "50",
"UART2_INT_ID": "3",
"TEST": "0",
"Base_M_AXIS": "3774873600",
"APBSlave0": "1",
"APBSlave2": "0",
"Base_M_IO": "4160749568",
"APBSlave1": "0",
"APBSlave3": "0",
"USER_1_INTR_ID": "17",
"USER_1_INTR": "0",
"USER_0_INTR_ID": "16",
"USER_0_INTR": "0",
"USER_2_INTR": "0",
"USER_2_INTR_ID": "22",
"USER_3_INTR": "0",
"USER_3_INTR_ID": "23",
"USER_4_INTR": "0",
"USER_4_INTR_ID": "24",
"USER_5_INTR": "0",
"USER_5_INTR_ID": "25",
"USER_6_INTR": "0",
"USER_6_INTR_ID": "26",
"USER_7_INTR": "0",
"USER_7_INTR_ID": "27",
"APBSlave4": "0",
"CustomInstruction": "0",
"ATMEXT": "0",
"CMREXT": "0",
"FPEXT": "1",
"FPU": "0",
"LINUX": "0",
"ICACHEWAY": "1",
"DCACHEWAY": "1",
"CpuCount": "1",
"ICacheSize": "4096",
"DCacheSize": "4096",
"Cache": "1",
"DDR": "0",
"DDR_AXI4": "0",
"DDRWidth": "128",
"DDRSize": "3758096384",
"OCRSize": "32768",
"AXISlave": "0",
"AXISlaveSize": "16777216",
"GPIO1_INT_ID1": "15",
"GPIO1_INT_ID0": "14",
"GPIO0_INT_ID1": "13",
"GPIO0_INT_ID0": "12",
"GPIO0": "0",
"GPIO0Width": "4",
"GPIO1Width": "8",
"GPIO1": "0",
"UART0_INT_ID": "1",
"IOSize": "4096",
"UART0_M_Addr": "4096",
"UART1_M_Addr": "8192",
"UART2_M_Addr": "12288",
"SPI0_M_Addr": "24576",
"SPI1_M_Addr": "16384",
"SPI2_M_Addr": "20480",
"I2C0_M_Addr": "40960",
"I2C1_M_Addr": "45056",
"I2C2_M_Addr": "49152",
"GPIO0_M_Addr": "53248",
"GPIO1_M_Addr": "57344",
"APBSlave0_M_Addr": "1048576",
"APBSlave1_M_Addr": "2097152",
"APBSlave2_M_Addr": "3145728",
"APBSlave3_M_Addr": "4194304",
"APBSlave4_M_Addr": "5242880",
"UART0": "1",
"UART2": "0",
"UART1_INT_ID": "2",
"UART1": "0",
"SPI2": "0",
"SPI2DW": "8",
"SPI2SS": "1",
"SPI1_INT_ID": "5",
"SPI1": "0",
"SPI1DW": "8",
"SPI1SS": "1",
"SPI0_INT_ID": "4",
"SPI0": "1",
"SPI0DW": "8",
"SPI0SS": "1",
"I2C2_INT_ID": "10",
"ADDR_Scheme": "0",
"I2C2": "0",
"I2C1": "0",
"SPI2_INT_ID": "6",
"I2C1_INT_ID": "9",
"I2C0_INT_ID": "8",
"I2C0": "0",
"AXIMasterWidth_1": "32",
"AXIMaster_1": "0",
"AXIMasterWidth": "32",
"AXIMaster": "1",
"USER_TIMER0": "0",
"USER_TIMER0_CNT_WIDTH": "12",
"USER_TIMER0_PS_WIDTH": "8",
"USER_TIMER0_INT_ID": "19",
"USER_TIMER0_M_Addr": "61440",
"USER_TIMER1": "0",
"USER_TIMER1_CNT_WIDTH": "12",
"USER_TIMER1_PS_WIDTH": "8",
"USER_TIMER1_INT_ID": "20",
"USER_TIMER1_M_Addr": "65536",
"USER_TIMER2": "0",
"USER_TIMER2_CNT_WIDTH": "12",
"USER_TIMER2_PS_WIDTH": "8",
"USER_TIMER2_INT_ID": "21",
"USER_TIMER2_M_Addr": "69632"
},
"output": {
"external_generator": [],
"external_source": [
"/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_tmpl.v",
"/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire.v",
"/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_define.vh",
"/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_tmpl.vhd"
],
"external_script": [],
"external_embedded_sw": []
},
"sw_version": "2022.1.196",
"generated_date": "2022-08-08T02:57:54.948573"
}

14093
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v Normal file
View File

File diff suppressed because it is too large Load Diff

8192
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin Normal file
View File

File diff suppressed because it is too large Load Diff

8192
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin Normal file
View File

File diff suppressed because it is too large Load Diff

8192
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin Normal file
View File

File diff suppressed because it is too large Load Diff

8192
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin Normal file
View File

File diff suppressed because it is too large Load Diff

23
fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/soc_config Normal file
View File

@@ -0,0 +1,23 @@
--ramHex "/projects/SSE/kmlau/install/efinity/2022.1/ipm/ip/efx_soc/efx_soc/generator/bootloader/bootloader_32K.hex"
--cpuCount 1
--spi name=system_spi_0_io,address=0x014000,interruptId=4,width=8,ssCount=1
--Fpu false
--uart name=system_uart_0_io,address=0x010000,interruptId=1
--L1I true
--dCacheSize 4096
--axiAEnable false
--onChipRamSize 0x8000
--iCacheWays 1
--apbSlave name=io_apbSlave_0,address=0x100000,size=65536
--ddrAEnable false
--iCacheSize 4096
--onChipRamAddress 0xf9000000
--Atomic false
--PeripheralClock false
--softTap false
--customInstruction false
--apbBridgeAddress 0xf8000000
--L1D true
--Linux false
--dCacheWays 1
--systemFrequency 50000000

241
fpga/ip/gTSE/T120F324_devkit/mac_pat_gen.v Normal file
View File

@@ -0,0 +1,241 @@
/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module mac_pat_gen
(
//Globle Signals
input clk,
input rstn,
//Control Interface
input pat_gen_en,
input [15:0] pat_gen_num,//When value is 0, it's infinite mode
input [15:0] pat_gen_ipg,
//MAC Protocol Signals
input [47:0] dst_mac,
input [47:0] src_mac,
input [15:0] mac_dlen,
//AXI4-Stream Interface
input rclk,
input rrstn,
input [7:0] rdata,
input rvalid,
input rlast,
output reg [7:0] tdata,
output reg tvalid,
output reg tlast,
input tready
);
// Parameter Define
localparam IDLE = 2'h0;
localparam PAT_IPG = 2'h1;
localparam PAT_GEN = 2'h2;
// Register Define
reg pat_gen_en_dl1;
reg pat_gen_en_dl2;
reg [1:0] cur_state;
reg [1:0] next_state;
reg pat_en;
reg infinite_en;
reg [15:0] num_cnt;
reg [15:0] ipg_cnt;
reg [15:0] pat_cnt;
reg [15:0] pat_gen_num_r;
reg [15:0] pat_gen_ipg_r;
reg [47:0] dst_mac_r;
reg [47:0] src_mac_r;
reg [15:0] mac_dlen_r;
// Wire Define
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0) begin
pat_gen_num_r <= 16'h0;
pat_gen_ipg_r <= 16'h0;
dst_mac_r <= 48'h0;
src_mac_r <= 48'h0;
mac_dlen_r <= 16'h0;
end
else begin
pat_gen_num_r <= pat_gen_num;
pat_gen_ipg_r <= pat_gen_ipg;
dst_mac_r <= dst_mac;
src_mac_r <= src_mac;
mac_dlen_r <= mac_dlen;
end
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
begin
pat_gen_en_dl1 <= 1'h0;
pat_gen_en_dl2 <= 1'h0;
end
else
begin
pat_gen_en_dl1 <= pat_gen_en;
pat_gen_en_dl2 <= pat_gen_en_dl1;
end
end
/*----------------------- FSM Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
cur_state <= IDLE;
else
cur_state <= next_state;
end
always @(*)
begin
case(cur_state)
IDLE :
if(pat_en == 1'b1)
next_state = PAT_GEN;
else
next_state = IDLE;
PAT_IPG :
if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0)))
next_state = IDLE;
else if(ipg_cnt == pat_gen_ipg_r)
next_state = PAT_GEN;
else
next_state = PAT_IPG;
PAT_GEN :
if((tlast == 1'b1) && (tready == 1'b1))
next_state = PAT_IPG;
else
next_state = PAT_GEN;
default :
next_state = IDLE;
endcase
end
/*----------------------- Generator Control Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
pat_en <= 1'h0;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
pat_en <= 1'h1;
else if((cur_state == IDLE) && (pat_en == 1'b1))
pat_en <= 1'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
infinite_en <= 1'h0;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0))
infinite_en <= 1'h1;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
infinite_en <= 1'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
num_cnt <= 16'h0;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
num_cnt <= pat_gen_num_r;
else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0))
num_cnt <= num_cnt - 1'b1;
end
/*----------------------- Pattern Counter Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ipg_cnt <= 16'h0;
else if(cur_state == PAT_IPG)
ipg_cnt <= ipg_cnt + 1'b1;
else
ipg_cnt <= 8'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
pat_cnt <= 16'h0;
else if(cur_state != PAT_GEN)
pat_cnt <= 16'h0;
else if(tready == 1'b1)
pat_cnt <= pat_cnt + 1'b1;
end
/*----------------------- Pattern Generator Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
tvalid <= 1'b0;
else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1))
tvalid <= 1'b1;
else if((tready == 1'b1) && (tlast == 1'b1))
tvalid <= 1'b0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
tdata <= 8'h0;
else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd14))
case(pat_cnt[3:0])
4'd0 : tdata <= dst_mac_r[5*8 +: 8];
4'd1 : tdata <= dst_mac_r[4*8 +: 8];
4'd2 : tdata <= dst_mac_r[3*8 +: 8];
4'd3 : tdata <= dst_mac_r[2*8 +: 8];
4'd4 : tdata <= dst_mac_r[1*8 +: 8];
4'd5 : tdata <= dst_mac_r[0*8 +: 8];
4'd6 : tdata <= src_mac_r[5*8 +: 8];
4'd7 : tdata <= src_mac_r[4*8 +: 8];
4'd8 : tdata <= src_mac_r[3*8 +: 8];
4'd9 : tdata <= src_mac_r[2*8 +: 8];
4'd10 : tdata <= src_mac_r[1*8 +: 8];
4'd11 : tdata <= src_mac_r[0*8 +: 8];
4'd12 : tdata <= mac_dlen_r[15:8];
4'd13 : tdata <= mac_dlen_r[7:0];
4'd14 : tdata <= 8'h0;//MAC First Data
default : tdata <= tdata + 1'b1;
endcase
else if((cur_state == PAT_GEN) && (tready == 1'b1))
tdata <= tdata + 1'b1;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
tlast <= 1'b0;
else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == mac_dlen_r+16'd13))
tlast <= 1'b1;
else if(tready == 1'b1)
tlast <= 1'b0;
end
endmodule

139
fpga/ip/gTSE/T120F324_devkit/mac_rx2tx.v Normal file
View File

@@ -0,0 +1,139 @@
/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module mac_rx2tx
(
//Globle Signals
//
//Receive AXI4-Stream Interface
input rx_axis_clk,
input rx_axis_rstn,
input [7:0] rx_axis_mac_tdata,
input rx_axis_mac_tvalid,
input rx_axis_mac_tlast,
input rx_axis_mac_tuser,
output reg rx_axis_mac_tready,
//Transmit AXI4-Stream Interface
input tx_axis_clk,
input tx_axis_rstn,
output reg [7:0] tx_axis_mac_tdata,
output reg tx_axis_mac_tvalid,
output reg tx_axis_mac_tlast,
output reg tx_axis_mac_tuser,
input tx_axis_mac_tready
);
// Parameter Define
// Register Define
// Wire Define
wire [9:0] u1_data;
wire u1_wrreq;
wire u1_rdreq;
wire [9:0] u1_q;
wire u1_empty;
wire u1_almfull;
wire [10:0] u1_wrcnt;
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
/*----------------------- Rx Clock Region ----------------------------*/
assign u1_almfull = (u1_wrcnt >= 2045);
always @(posedge rx_axis_clk or negedge rx_axis_rstn)
begin
if(rx_axis_rstn == 1'b0)
rx_axis_mac_tready <= 1'b0;
else if(u1_almfull == 1'b1)
rx_axis_mac_tready <= 1'b0;
else
rx_axis_mac_tready <= 1'b1;
end
/*----------------------- Fifo 1 Region ----------------------------*/
DC_FIFO #(
.FIFO_MODE ("ShowAhead" ),
.DATA_WIDTH (10 ),
.FIFO_DEPTH (2048 )
)
u1
(
//System Signal
.Reset (!rx_axis_rstn ),
//Write Signal
.WrClk (rx_axis_clk ),
.WrEn (u1_wrreq ),
.WrDNum (u1_wrcnt ),
.WrFull ( ),
.WrData (u1_data ),
//Read Signal
.RdClk (tx_axis_clk ),
.RdEn (u1_rdreq ),
.RdDNum ( ),
.RdEmpty (u1_empty ),
.RdData (u1_q )
);
assign u1_data = {rx_axis_mac_tuser,rx_axis_mac_tlast,rx_axis_mac_tdata};
assign u1_wrreq = (rx_axis_mac_tvalid == 1'b1) && (rx_axis_mac_tready == 1'b1);
assign u1_rdreq = (u1_empty == 1'b0) && ((tx_axis_mac_tvalid == 1'b0) || (tx_axis_mac_tready == 1'b1));
/*----------------------- Tx Clock Region ----------------------------*/
always @(posedge tx_axis_clk or negedge tx_axis_rstn)
begin
if(tx_axis_rstn == 1'b0)
tx_axis_mac_tvalid <= 1'b0;
else if(u1_rdreq == 1'b1)
tx_axis_mac_tvalid <= 1'b1;
else if(tx_axis_mac_tready == 1'b1)
tx_axis_mac_tvalid <= 1'b0;
end
always @(posedge tx_axis_clk or negedge tx_axis_rstn)
begin
if(tx_axis_rstn == 1'b0)
tx_axis_mac_tdata <= 8'h0;
else if(u1_rdreq == 1'b1)
tx_axis_mac_tdata <= u1_q[7:0];
else if(tx_axis_mac_tready == 1'b1)
tx_axis_mac_tdata <= 8'h0;
end
always @(posedge tx_axis_clk or negedge tx_axis_rstn)
begin
if(tx_axis_rstn == 1'b0)
tx_axis_mac_tlast <= 1'b0;
else if(u1_rdreq == 1'b1)
tx_axis_mac_tlast <= u1_q[8];
else if(tx_axis_mac_tready == 1'b1)
tx_axis_mac_tlast <= 1'b0;
end
always @(posedge tx_axis_clk or negedge tx_axis_rstn)
begin
if(tx_axis_rstn == 1'b0)
tx_axis_mac_tuser <= 1'b0;
else if((u1_rdreq == 1'b1) && (u1_q[8] == 1'b1))
tx_axis_mac_tuser <= u1_q[9];
else if(tx_axis_mac_tready == 1'b1)
tx_axis_mac_tuser <= 1'b0;
end
endmodule

333
fpga/ip/gTSE/T120F324_devkit/reg_apb3.v Normal file
View File

@@ -0,0 +1,333 @@
/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module reg_apb3#(
parameter ADDR_WTH = 10
)
(
//Globle Signals
//
//APB3 Slave Interface
input s_apb3_clk,
input s_apb3_rstn,
input [ADDR_WTH-1:0] s_apb3_paddr,
input s_apb3_psel,
input s_apb3_penable,
output reg s_apb3_pready,
input s_apb3_pwrite,//0:rd; 1:wr;
input [31:0] s_apb3_pwdata,
output reg [31:0] s_apb3_prdata,
output wire s_apb3_pslverror,
//Cfg Space Registers
//--Example Registers Field
output reg mac_sw_rst,
output reg axi4_st_mux_select,
output reg pat_mux_select,
output reg udp_pat_gen_en,
output reg mac_pat_gen_en,
output reg [15:0] pat_gen_num,
output reg [15:0] pat_gen_ipg,
output reg [47:0] pat_dst_mac,
output reg [47:0] pat_src_mac,
output reg [15:0] pat_mac_dlen,
output reg [31:0] pat_src_ip,
output reg [31:0] pat_dst_ip,
output reg [15:0] pat_src_port,
output reg [15:0] pat_dst_port,
output reg [15:0] pat_udp_dlen,
output reg [1:0] clkmux_sel
);
// Parameter Define
// Register Define
reg [ADDR_WTH-3:0] loc_addr;
reg loc_wr_vld;
reg loc_rd_vld;
// Wire Define
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
//apb3 interface
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
loc_addr <= {ADDR_WTH-2{1'b0}};
else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0))
loc_addr <= s_apb3_paddr[2+:ADDR_WTH-2];
end
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
loc_wr_vld <= 1'b0;
else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
loc_wr_vld <= 1'b1;
else
loc_wr_vld <= 1'b0;
end
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
loc_rd_vld <= 1'b0;
else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0))
loc_rd_vld <= 1'b1;
else
loc_rd_vld <= 1'b0;
end
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
s_apb3_pready <= 1'b0;
else if((loc_wr_vld == 1'b1) || (loc_rd_vld == 1'b1))
s_apb3_pready <= 1'b1;
else
s_apb3_pready <= 1'b0;
end
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
s_apb3_prdata <= 32'h0;
else if(loc_rd_vld == 1'b1)
begin
case(loc_addr)
//Example Registers Field
'h080 : s_apb3_prdata <= {31'h0,mac_sw_rst};
'h081 : s_apb3_prdata <= {30'h0,pat_mux_select,axi4_st_mux_select};
'h082 : s_apb3_prdata <= {30'h0,mac_pat_gen_en,udp_pat_gen_en};
'h083 : s_apb3_prdata <= {pat_gen_ipg,pat_gen_num};
'h084 : s_apb3_prdata <= pat_dst_mac[31:0];
'h085 : s_apb3_prdata <= {16'h0,pat_dst_mac[47:32]};
'h086 : s_apb3_prdata <= pat_src_mac[31:0];
'h087 : s_apb3_prdata <= {16'h0,pat_src_mac[47:32]};
'h088 : s_apb3_prdata <= {16'h0,pat_mac_dlen};
'h089 : s_apb3_prdata <= pat_src_ip;
'h08a : s_apb3_prdata <= pat_dst_ip;
'h08b : s_apb3_prdata <= {pat_dst_port,pat_src_port};
'h08c : s_apb3_prdata <= {16'h0,pat_udp_dlen};
'h08d : s_apb3_prdata <= {30'h0,clkmux_sel};
endcase
end
end
assign s_apb3_pslverror = 1'b0;
/*----------------------------------------------------------------------------------*\
Register Space -- Example Registers Field
\*----------------------------------------------------------------------------------*/
//loc_addr = 0x080; axi_addr = 0x200; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
mac_sw_rst <= 1'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h080))
begin
mac_sw_rst <= s_apb3_pwdata[0];
end
end
//loc_addr = 0x081; axi_addr = 0x204; RW;
//[axi4_st_mux_select] 0:pat tx mode; 1:rx2tx loopback mode;
//[pat_mux_select] 0:udp pat; 1:mac pat;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
axi4_st_mux_select <= 1'h0;
pat_mux_select <= 1'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h081))
begin
axi4_st_mux_select <= s_apb3_pwdata[0];
pat_mux_select <= s_apb3_pwdata[1];
end
end
//loc_addr = 0x082; axi_addr = 0x208; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
udp_pat_gen_en <= 1'h0;
mac_pat_gen_en <= 1'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h082))
begin
udp_pat_gen_en <= s_apb3_pwdata[0];
mac_pat_gen_en <= s_apb3_pwdata[1];
end
end
//loc_addr = 0x083; axi_addr = 0x20c; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_gen_num <= 16'h0;
pat_gen_ipg <= 16'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h083))
begin
pat_gen_num <= s_apb3_pwdata[15:0];
pat_gen_ipg <= s_apb3_pwdata[31:16];
end
end
//loc_addr = 0x084; axi_addr = 0x210; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_dst_mac[31:0] <= 32'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h084))
begin
pat_dst_mac[31:0] <= s_apb3_pwdata[31:0];
end
end
//loc_addr = 0x085; axi_addr = 0x214; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_dst_mac[47:32] <= 16'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h085))
begin
pat_dst_mac[47:32] <= s_apb3_pwdata[15:0];
end
end
//loc_addr = 0x086; axi_addr = 0x218; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_src_mac[31:0] <= 32'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h086))
begin
pat_src_mac[31:0] <= s_apb3_pwdata[31:0];
end
end
//loc_addr = 0x087; axi_addr = 0x21c; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_src_mac[47:32] <= 16'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h087))
begin
pat_src_mac[47:32] <= s_apb3_pwdata[15:0];
end
end
//loc_addr = 0x088; axi_addr = 0x220; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_mac_dlen <= 16'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h088))
begin
pat_mac_dlen <= s_apb3_pwdata[15:0];
end
end
//loc_addr = 0x089; axi_addr = 0x224; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_src_ip <= 32'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h089))
begin
pat_src_ip <= s_apb3_pwdata[31:0];
end
end
//loc_addr = 0x08a; axi_addr = 0x228; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_dst_ip <= 32'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08a))
begin
pat_dst_ip <= s_apb3_pwdata[31:0];
end
end
//loc_addr = 0x08b; axi_addr = 0x22c; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_src_port <= 16'h0;
pat_dst_port <= 16'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08b))
begin
pat_src_port <= s_apb3_pwdata[15:0];
pat_dst_port <= s_apb3_pwdata[31:16];
end
end
//loc_addr = 0x08c; axi_addr = 0x230; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_udp_dlen <= 16'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08c))
begin
pat_udp_dlen <= s_apb3_pwdata[15:0];
end
end
//loc_addr = 0x08d; axi_addr = 0x234; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
clkmux_sel <= 2'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08d))
begin
clkmux_sel <= s_apb3_pwdata[1:0];
end
end
/*----------------------------------------------------------------------------------*\
Register Space -- The End
\*----------------------------------------------------------------------------------*/
endmodule

206
fpga/ip/gTSE/T120F324_devkit/rgmii_2_rmii.v Normal file
View File

@@ -0,0 +1,206 @@
/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module rgmii_2_rmii (
input clk_50m, //50Mhz refclock
input rst_n,
//conduit
input [2:0] eth_speed,
//rgmii interface
input [3:0] rgmii_txd,
input rgmii_tx_ctl,
output wire [3:0] rgmii_rxd,
output wire rgmii_rx_ctl,
output reg rgmii_rxc,
//rmii interface
output wire rmii_clk,
output reg [1:0] rmii_txd,
output reg rmii_txen,
input [1:0] rmii_rxd,
input rmii_crsdv
);
wire [3:0] rxd_c;
wire rx_ctl_c;
reg [3:0] rxd_r;
reg rx_ctl_r;
reg rmii_crsdv_r, shift_en;
reg [4:0] txd_cnt, rxd_cnt;
reg [3:0] rxd_shiftreg;
reg [1:0] shift2;
reg [19:0] shift20;
reg [1:0] rx_ctl_p2;
reg [19:0] rx_ctl_p20;
assign rmii_clk = ~clk_50m; //create 180deg phaseshift
/*--------------- TX path ---------------------*/
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
txd_cnt <= 5'd0;
end
else if (rgmii_tx_ctl) begin
if (((eth_speed == 3'h2) && txd_cnt == 5'd1) ||
((eth_speed == 3'h1) && txd_cnt == 5'd19)) begin
txd_cnt <= 5'd0;
end
else begin
txd_cnt <= txd_cnt + 5'd1;
end
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rmii_txen <= 1'b0;
end
else begin
rmii_txen <= rgmii_tx_ctl;
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rmii_txd <= 2'b00;
end
else begin
if ((eth_speed == 3'h2) && txd_cnt == 5'd0) begin
rmii_txd <= rgmii_txd[1:0];
end
else if ((eth_speed == 3'h2) && txd_cnt == 5'd1) begin
rmii_txd <= rgmii_txd[3:2];
end
if ((eth_speed == 3'h1) && txd_cnt == 5'd0) begin
rmii_txd <= rgmii_txd[1:0];
end
else if ((eth_speed == 3'h1) && txd_cnt == 5'd10) begin
rmii_txd <= rgmii_txd[3:2];
end
end
end
/*------------------ end of TX path ------------------------*/
/*------------ RX path ------------------*/
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rxd_cnt <= 5'd0;
end
else if (rmii_crsdv) begin
if (((eth_speed == 3'h2) && rxd_cnt == 5'd1) || ((eth_speed == 3'h1) && rxd_cnt == 5'd19)) begin
rxd_cnt <= 5'd0;
end
else begin
rxd_cnt <= rxd_cnt + 5'd1;
end
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rxd_shiftreg <= 4'd0;
end
else if (rmii_crsdv) begin
if (eth_speed == 3'h2 || ((eth_speed == 3'h1) && (rxd_cnt == 5'd0 || rxd_cnt == 5'd10))) begin
rxd_shiftreg <= {rmii_rxd, rxd_shiftreg[3:2]};
end
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
shift2 <= 2'b1;
shift20 <= 20'b1;
end
else begin
shift2 <= {shift2[0],shift2[1]};
shift20 <= {shift20[18:0],shift20[19]};
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rgmii_rxc <= 1'b0;
end
else begin
if ((eth_speed == 3'h2 && shift2[1]) || (eth_speed == 3'h1 && (shift20[10]))) begin
rgmii_rxc <= 1'b1;
end
else if ((eth_speed == 3'h2 && shift2[0]) || (eth_speed == 3'h1 && (shift20[0]))) begin
rgmii_rxc <= 1'b0;
end
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rx_ctl_p2 <= 2'd0;
rx_ctl_p20 <= 20'd0;
end
else begin
rx_ctl_p2 <= {rmii_crsdv , rx_ctl_p2[1]};
rx_ctl_p20 <= {rmii_crsdv, rx_ctl_p20[19:1]};
end
end
/*---- shift rxd & rx_ctl so that they are not edge align with rgmii_rxc ----*/
assign rxd_c = (rxd_cnt == 5'd0) ? rxd_shiftreg : rxd_r;
assign rx_ctl_c = (eth_speed == 3'h2) ? rx_ctl_p2[0] : rx_ctl_p20[0];
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rxd_r <= 4'd0;
rx_ctl_r <= 1'd0;
rmii_crsdv_r <= 1'd0;
end
else begin
rxd_r <= rxd_c;
rx_ctl_r <= rx_ctl_c;
rmii_crsdv_r <= rmii_crsdv;
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
shift_en <= 1'd0;
end // to detect if rmii_crsdv assert at the posedge of rgmii_rxc, delay rgmii_rxd & rgmii_rx_ctl if they are aligned with rgmii_rxc
else if (rmii_crsdv && ~rmii_crsdv_r) begin
if (((eth_speed == 3'h2) && shift2[0]) || ((eth_speed == 3'h1) && shift20[11])) begin
shift_en <= 1'd1;
end
else begin
shift_en <= 1'd0;
end
end
end
assign rgmii_rxd = shift_en ? rxd_r : rxd_c;
assign rgmii_rx_ctl = shift_en ? rx_ctl_r : rx_ctl_c;
/*--------------------------------------------------------*/
/*------------------ end of RX path ------------------------*/
endmodule

131
fpga/ip/gTSE/T120F324_devkit/temac_ex.peri.xml Normal file
View File

@@ -0,0 +1,131 @@
<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="temac_ex" device_def="T120F324" location="/projects/DIP/shlim/efx_IP/efx_tsemac/tsemac_reference_design_IPM-v1.0/tsemac/fpga/T120F324_devkit" version="2021.M.268" db_version="20211502" last_change_date="Wed Oct 20 11:50:41 2021" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="1B_1C" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="1D_1E_1F_1G" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="2D" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="2E" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="2F" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="3A" iostd="1.2 V"/>
<efxpt:iobank name="3B" iostd="1.2 V"/>
<efxpt:iobank name="3D_TR_BR" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="4E" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="4F" iostd="3.3 V LVTTL / LVCMOS"/>
<efxpt:iobank name="BL" iostd="1.2 V"/>
<efxpt:iobank name="TL" iostd="1.2 V"/>
</efxpt:iobank_info>
<efxpt:ctrl_info>
<efxpt:ctrl name="cfg" ctrl_def="CONFIG_CTRL0" clock_name="" is_clk_invert="false" cbsel_bus_name="cfg_CBSEL" config_ctrl_name="cfg_CONFIG" ena_capture_name="cfg_ENA" error_status_name="cfg_ERROR" um_signal_status_name="cfg_USR_STATUS" is_remote_update_enable="false" is_user_mode_enable="false"/>
</efxpt:ctrl_info>
</efxpt:device_info>
<efxpt:gpio_info device_def="T120F324">
<efxpt:gpio name="clk_50m_ext" gpio_def="GPIOR_186" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="clk_50m_ext" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="phy_mdc" gpio_def="GPIOT_RXN12" mode="output" bus_name="" is_lvds_gpio="true" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="phy_mdc" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:gpio name="phy_mdio" gpio_def="GPIOT_RXP13" mode="inout" bus_name="" is_lvds_gpio="true" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="phy_mdi" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="phy_mdo" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
<efxpt:output_enable_config name="phy_mdo_en" is_register="false" clock_name="" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="phy_rstn" gpio_def="GPIOT_RXN13" mode="output" bus_name="" is_lvds_gpio="true" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="phy_rstn" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="rgmii_rx_ctl" gpio_def="GPIOT_RXP12" mode="input" bus_name="" is_lvds_gpio="true" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="rgmii_rx_ctl" name_ddio_lo="rgmii_rx_ctl_LO" conn_type="normal" is_register="true" clock_name="rgmii_rxc" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="rgmii_rxc" gpio_def="GPIOL_73" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="rgmii_rxc" name_ddio_lo="" conn_type="gclk" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="rgmii_rxd[0]" gpio_def="GPIOL_62" mode="input" bus_name="rgmii_rxd" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="rgmii_rxd_HI[0]" name_ddio_lo="rgmii_rxd_LO[0]" conn_type="normal" is_register="true" clock_name="rgmii_rxc" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="resync"/>
</efxpt:gpio>
<efxpt:gpio name="rgmii_rxd[1]" gpio_def="GPIOL_63" mode="input" bus_name="rgmii_rxd" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="rgmii_rxd_HI[1]" name_ddio_lo="rgmii_rxd_LO[1]" conn_type="normal" is_register="true" clock_name="rgmii_rxc" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="resync"/>
</efxpt:gpio>
<efxpt:gpio name="rgmii_rxd[2]" gpio_def="GPIOL_17" mode="input" bus_name="rgmii_rxd" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="rgmii_rxd_HI[2]" name_ddio_lo="rgmii_rxd_LO[2]" conn_type="normal" is_register="true" clock_name="rgmii_rxc" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="resync"/>
</efxpt:gpio>
<efxpt:gpio name="rgmii_rxd[3]" gpio_def="GPIOL_75" mode="input" bus_name="rgmii_rxd" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="rgmii_rxd_HI[3]" name_ddio_lo="rgmii_rxd_LO[3]" conn_type="normal" is_register="true" clock_name="rgmii_rxc" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="resync"/>
</efxpt:gpio>
<efxpt:gpio name="rgmii_tx_ctl" gpio_def="GPIOT_RXP11" mode="output" bus_name="" is_lvds_gpio="true" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="rgmii_tx_ctl" name_ddio_lo="rgmii_tx_ctl_HI" register_option="register" clock_name="clk_125m" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="4"/>
</efxpt:gpio>
<efxpt:gpio name="rgmii_txc" gpio_def="GPIOL_72" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="rgmii_txc_HI" name_ddio_lo="rgmii_txc_LO" register_option="register" clock_name="clk_125m_90deg" is_clock_inverted="true" is_slew_rate="false" tied_option="none" ddio_type="resync" drive_strength="4"/>
</efxpt:gpio>
<efxpt:gpio name="rgmii_txd[0]" gpio_def="GPIOR_173" mode="output" bus_name="rgmii_txd" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="rgmii_txd_HI[0]" name_ddio_lo="rgmii_txd_LO[0]" register_option="register" clock_name="clk_125m" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="resync" drive_strength="4"/>
</efxpt:gpio>
<efxpt:gpio name="rgmii_txd[1]" gpio_def="GPIOR_174" mode="output" bus_name="rgmii_txd" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="rgmii_txd_HI[1]" name_ddio_lo="rgmii_txd_LO[1]" register_option="register" clock_name="clk_125m" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="resync" drive_strength="4"/>
</efxpt:gpio>
<efxpt:gpio name="rgmii_txd[2]" gpio_def="GPIOR_183" mode="output" bus_name="rgmii_txd" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="rgmii_txd_HI[2]" name_ddio_lo="rgmii_txd_LO[2]" register_option="register" clock_name="clk_125m" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="resync" drive_strength="4"/>
</efxpt:gpio>
<efxpt:gpio name="rgmii_txd[3]" gpio_def="GPIOR_178" mode="output" bus_name="rgmii_txd" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="rgmii_txd_HI[3]" name_ddio_lo="rgmii_txd_LO[3]" register_option="register" clock_name="clk_125m" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="resync" drive_strength="4"/>
</efxpt:gpio>
<efxpt:gpio name="sw6" gpio_def="GPIOT_RXP29" mode="input" bus_name="" is_lvds_gpio="true" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="sw6" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="weak pullup" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="system_spi_0_io_data_0" gpio_def="GPIOL_08" mode="inout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="system_spi_0_io_data_0_read" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="clk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="system_spi_0_io_data_0_write" name_ddio_lo="" register_option="register" clock_name="clk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
<efxpt:output_enable_config name="system_spi_0_io_data_0_writeEnable" is_register="true" clock_name="clk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="system_spi_0_io_data_1" gpio_def="GPIOL_09" mode="inout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="system_spi_0_io_data_1_read" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="clk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
<efxpt:output_config name="system_spi_0_io_data_1_write" name_ddio_lo="" register_option="register" clock_name="clk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
<efxpt:output_enable_config name="system_spi_0_io_data_1_writeEnable" is_register="true" clock_name="clk" is_clock_inverted="false"/>
</efxpt:gpio>
<efxpt:gpio name="system_spi_0_io_sclk_write" gpio_def="GPIOL_01" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="system_spi_0_io_sclk_write" name_ddio_lo="" register_option="register" clock_name="clk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="system_spi_0_io_ss" gpio_def="GPIOL_00" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="system_spi_0_io_ss" name_ddio_lo="" register_option="register" clock_name="clk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
</efxpt:gpio>
<efxpt:gpio name="system_uart_0_io_rxd" gpio_def="GPIOT_RXN20" mode="input" bus_name="" is_lvds_gpio="true" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="system_uart_0_io_rxd" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="system_uart_0_io_txd" gpio_def="GPIOT_RXP20" mode="output" bus_name="" is_lvds_gpio="true" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="system_uart_0_io_txd" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
</efxpt:gpio>
<efxpt:global_unused_config state="input with weak pullup"/>
<efxpt:bus name="rgmii_txd" mode="output" msb="3" lsb="0"/>
<efxpt:bus name="rgmii_rxd" mode="input" msb="3" lsb="0"/>
</efxpt:gpio_info>
<efxpt:pll_info>
<efxpt:pll name="pll_0" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.0000" multiplier="5" pre_divider="2" post_divider="4" reset_name="pll_rstn" locked_name="pll_0_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:output_clock name="clk" number="0" out_divider="5" adv_out_phase_shift="0"/>
<efxpt:output_clock name="clk_125m" number="1" out_divider="2" adv_out_phase_shift="0"/>
<efxpt:output_clock name="clk_125m_90deg" number="2" out_divider="2" adv_out_phase_shift="90"/>
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="2" clksel_name="" feedback_clock_name="clk_125m" feedback_mode="core"/>
</efxpt:pll>
</efxpt:pll_info>
<efxpt:lvds_info/>
<efxpt:mipi_info/>
<efxpt:jtag_info>
<efxpt:jtag name="jtag_inst1" jtag_def="JTAG_USER1">
<efxpt:gen_pin>
<efxpt:pin name="jtag_inst1_CAPTURE" type_name="CAPTURE" is_bus="false"/>
<efxpt:pin name="jtag_inst1_DRCK" type_name="DRCK" is_bus="false"/>
<efxpt:pin name="jtag_inst1_RESET" type_name="RESET" is_bus="false"/>
<efxpt:pin name="jtag_inst1_RUNTEST" type_name="RUNTEST" is_bus="false"/>
<efxpt:pin name="jtag_inst1_SEL" type_name="SEL" is_bus="false"/>
<efxpt:pin name="jtag_inst1_SHIFT" type_name="SHIFT" is_bus="false"/>
<efxpt:pin name="jtag_inst1_TCK" type_name="TCK" is_bus="false"/>
<efxpt:pin name="jtag_inst1_TDI" type_name="TDI" is_bus="false"/>
<efxpt:pin name="jtag_inst1_TMS" type_name="TMS" is_bus="false"/>
<efxpt:pin name="jtag_inst1_UPDATE" type_name="UPDATE" is_bus="false"/>
<efxpt:pin name="jtag_inst1_TDO" type_name="TDO" is_bus="false"/>
</efxpt:gen_pin>
</efxpt:jtag>
</efxpt:jtag_info>
<efxpt:ddr_info/>
</efxpt:design_db>

563
fpga/ip/gTSE/T120F324_devkit/temac_ex.v Normal file
View File

@@ -0,0 +1,563 @@
/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
//`include "header.v" // use JTAG hard block
module temac_ex
(
//Globle Signals
//----pll_0
input clk,
input clk_125m,
input pll_0_locked,
input sw6,
output wire pll_rstn,
//TEMAC PHY RGMII Interface
output wire [3:0] rgmii_txd_HI,
output wire [3:0] rgmii_txd_LO,
output wire rgmii_txc_HI,
output wire rgmii_txc_LO,
input [3:0] rgmii_rxd_HI,
input [3:0] rgmii_rxd_LO,
`ifdef TITANIUM
output wire rgmii_tx_ctl_HI,
output wire rgmii_tx_ctl_LO,
input rgmii_rx_ctl_HI,
input rgmii_rx_ctl_LO,
input mux_clk,
output [1:0] mux_clk_sw,
`else
input rgmii_rxc,
output wire rgmii_tx_ctl,
input rgmii_rx_ctl,
`endif
//TEMAC PHY Ctr Interface
output wire phy_rstn,
//hardware Jtag Interface
`ifndef SIM_MODE
`ifndef SOFT_TAP
input jtag_inst1_TCK,
input jtag_inst1_TDI,
output wire jtag_inst1_TDO,
input jtag_inst1_SEL,
input jtag_inst1_CAPTURE,
input jtag_inst1_SHIFT,
input jtag_inst1_UPDATE,
input jtag_inst1_RESET,
`else
//software Jtag Interface
input io_jtag_tms,
input io_jtag_tdi,
output wire io_jtag_tdo,
input io_jtag_tck,
`endif
//Debug Signals
//output wire [1:0] debug_led
output wire system_uart_0_io_txd,
input system_uart_0_io_rxd,
`endif
output system_spi_0_io_sclk_write,
output system_spi_0_io_data_0_writeEnable,
input system_spi_0_io_data_0_read,
output system_spi_0_io_data_0_write,
output system_spi_0_io_data_1_writeEnable,
input system_spi_0_io_data_1_read,
output system_spi_0_io_data_1_write,
output system_spi_0_io_ss,
//TEMAC PHY MDIO Interface
input phy_mdi,
output wire phy_mdo,
output wire phy_mdo_en,
output wire phy_mdc
);
// Parameter Define
`include "gTSE_define.svh"
// Register Define
// Wire Define
wire clk_50m;
wire clk_50m_rstn;
wire mac_reset;
wire proto_reset;
wire mac_rstn;
//AXI4-Stream Interface
wire rx_axis_clk;
wire [7:0] rx_axis_mac_tdata;
wire rx_axis_mac_tvalid;
wire rx_axis_mac_tlast;
wire rx_axis_mac_tuser;
wire rx_axis_mac_tready;
wire tx_axis_clk;
wire [7:0] tx_axis_mac_tdata;
wire tx_axis_mac_tvalid;
wire tx_axis_mac_tlast;
wire tx_axis_mac_tuser;
wire tx_axis_mac_tready;
wire [7:0] udp_tx_axis_mac_tdata;
wire udp_tx_axis_mac_tvalid;
wire udp_tx_axis_mac_tlast;
wire udp_tx_axis_mac_tready;
wire [7:0] mac_tx_axis_mac_tdata;
wire mac_tx_axis_mac_tvalid;
wire mac_tx_axis_mac_tlast;
wire mac_tx_axis_mac_tready;
wire [7:0] pat_tx_axis_mac_tdata;
wire pat_tx_axis_mac_tvalid;
wire pat_tx_axis_mac_tlast;
wire pat_tx_axis_mac_tuser;
wire pat_tx_axis_mac_tready;
wire [7:0] loop_tx_axis_mac_tdata;
wire loop_tx_axis_mac_tvalid;
wire loop_tx_axis_mac_tlast;
wire loop_tx_axis_mac_tuser;
wire loop_tx_axis_mac_tready;
//RiscV APB3 Interface
wire [15:0] apb3_paddr;
wire apb3_psel;
wire apb3_penable;
wire apb3_pready;
wire apb3_pwrite;
wire [31:0] apb3_pwdata;
wire [31:0] apb3_prdata;
wire apb3_pslverror;
//Mac APB3 Interface
wire [9:0] mac_apb3_paddr;
wire mac_apb3_psel;
wire mac_apb3_penable;
wire mac_apb3_pready;
wire mac_apb3_pwrite;
wire [31:0] mac_apb3_pwdata;
wire [31:0] mac_apb3_prdata;
wire mac_apb3_pslverror;
//Ex APB3 Interface
wire [9:0] ex_apb3_paddr;
wire ex_apb3_psel;
wire ex_apb3_penable;
wire ex_apb3_pready;
wire ex_apb3_pwrite;
wire [31:0] ex_apb3_pwdata;
wire [31:0] ex_apb3_prdata;
wire ex_apb3_pslverror;
//AXI4-Lite Interface
wire [9:0] axi_awaddr;
wire axi_awvalid;
wire axi_awready;
wire [31:0] axi_wdata;
wire axi_wvalid;
wire axi_wready;
wire [1:0] axi_bresp;
wire axi_bvalid;
wire axi_bready;
wire [9:0] axi_araddr;
wire axi_arvalid;
wire axi_arready;
wire [1:0] axi_rresp;
wire [31:0] axi_rdata;
wire axi_rvalid;
wire axi_rready;
//Cfg Space Registers
wire mac_sw_rst;
wire axi4_st_mux_select;
wire pat_mux_select;
wire udp_pat_gen_en;
wire mac_pat_gen_en;
wire [15:0] pat_gen_num;
wire [15:0] pat_gen_ipg;
wire [47:0] pat_dst_mac;
wire [47:0] pat_src_mac;
wire [15:0] pat_mac_dlen;
wire [31:0] pat_src_ip;
wire [31:0] pat_dst_ip;
wire [15:0] pat_src_port;
wire [15:0] pat_dst_port;
wire [15:0] pat_udp_dlen;
//TSE DDIO
`ifdef TITANIUM
wire rgmii_rxc;
assign rgmii_rxc = mux_clk;
`else
wire rgmii_rx_ctl_LO;
wire rgmii_rx_ctl_HI;
wire rgmii_tx_ctl_LO;
wire rgmii_tx_ctl_HI;
assign rgmii_tx_ctl = rgmii_tx_ctl_HI | rgmii_tx_ctl_LO ;
assign rgmii_rx_ctl_HI = rgmii_rx_ctl ;
assign rgmii_rx_ctl_LO = rgmii_rx_ctl ;
`endif
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
assign pll_rstn = 1;
/*----------------------- Clock Region -----------------------*/
//In full throughput usecase, rx_axis_clk and tx_axis_clk should be set to 125Mhz or above.
//In this example design, these clocks are set to 50Mhz because the UDP/MAC pattern generator has
//high combi logic and couldn't meet timing at 125Mhz.
assign rx_axis_clk = clk;//clk_125m;
assign tx_axis_clk = clk;//clk_125m;
/*----------------------- Reset Region -----------------------*/
//assign pll_0_reset = 1'b0;
assign clk_50m = clk;
assign phy_rstn = sw6;
assign clk_50m_rstn = pll_0_locked;
assign mac_reset = ~pll_0_locked;
assign proto_reset = mac_sw_rst;
assign mac_rstn = ~(mac_reset || proto_reset);
/*----------------------- MCU Module ----------------------------*/
`ifndef SIM_MODE
sapphire u_mcu
(
//user custom ports
//SOC
.io_systemClk (clk_50m ),
.io_asyncReset (1'b0 ),
.system_uart_0_io_txd (system_uart_0_io_txd ),
.system_uart_0_io_rxd (system_uart_0_io_rxd ),
.system_spi_0_io_sclk_write (system_spi_0_io_sclk_write ),
.system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable ),
.system_spi_0_io_data_0_read (system_spi_0_io_data_0_read ),
.system_spi_0_io_data_0_write (system_spi_0_io_data_0_write ),
.system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable ),
.system_spi_0_io_data_1_read (system_spi_0_io_data_1_read ),
.system_spi_0_io_data_1_write (system_spi_0_io_data_1_write ),
.system_spi_0_io_ss (system_spi_0_io_ss ),
.jtagCtrl_tck (jtag_inst1_TCK ),
.jtagCtrl_tdi (jtag_inst1_TDI ),
.jtagCtrl_tdo (jtag_inst1_TDO ),
.jtagCtrl_enable (jtag_inst1_SEL ),
.jtagCtrl_capture (jtag_inst1_CAPTURE ),
.jtagCtrl_shift (jtag_inst1_SHIFT ),
.jtagCtrl_update (jtag_inst1_UPDATE ),
.jtagCtrl_reset (jtag_inst1_RESET ),
//APB3 Master Interface
.io_apbSlave_0_PADDR (apb3_paddr ),
.io_apbSlave_0_PSEL (apb3_psel ),
.io_apbSlave_0_PENABLE (apb3_penable ),
.io_apbSlave_0_PREADY (apb3_pready ),
.io_apbSlave_0_PWRITE (apb3_pwrite ),
.io_apbSlave_0_PWDATA (apb3_pwdata ),
.io_apbSlave_0_PRDATA (apb3_prdata ),
.io_apbSlave_0_PSLVERROR (apb3_pslverror )
);
`endif
assign apb3_pready = (apb3_paddr[9] == 1'b0) ? mac_apb3_pready : ex_apb3_pready;
assign apb3_prdata = (apb3_paddr[9] == 1'b0) ? mac_apb3_prdata : ex_apb3_prdata;
assign apb3_pslverror = (apb3_paddr[9] == 1'b0) ? mac_apb3_pslverror : ex_apb3_pslverror;
assign mac_apb3_paddr = apb3_paddr[9:0];
assign mac_apb3_psel = (apb3_paddr[9] == 1'b0) ? apb3_psel : 1'b0;
assign mac_apb3_penable = apb3_penable;
assign mac_apb3_pwrite = apb3_pwrite;
assign mac_apb3_pwdata = apb3_pwdata;
assign ex_apb3_paddr = apb3_paddr[9:0];
assign ex_apb3_psel = (apb3_paddr[9] == 1'b1) ? apb3_psel : 1'b0;
assign ex_apb3_penable = apb3_penable;
assign ex_apb3_pwrite = apb3_pwrite;
assign ex_apb3_pwdata = apb3_pwdata;
apb3_2_axi4_lite#(
.ADDR_WTH (10 )
)
u_apb3_2_axi4_lite
(
//Globle Signals
.clk (clk_50m ),
.rstn (clk_50m_rstn ),
//APB3 Slave Interface
.s_apb3_paddr (mac_apb3_paddr ),
.s_apb3_psel (mac_apb3_psel ),
.s_apb3_penable (mac_apb3_penable ),
.s_apb3_pready (mac_apb3_pready ),
.s_apb3_pwrite (mac_apb3_pwrite ),
.s_apb3_pwdata (mac_apb3_pwdata ),
.s_apb3_prdata (mac_apb3_prdata ),
.s_apb3_pslverror (mac_apb3_pslverror ),
//AXI4-Lite Master Interface
.m_axi_awaddr (axi_awaddr ),
.m_axi_awvalid (axi_awvalid ),
.m_axi_awready (axi_awready ),
.m_axi_wdata (axi_wdata ),
.m_axi_wvalid (axi_wvalid ),
.m_axi_wready (axi_wready ),
.m_axi_bresp (axi_bresp ),
.m_axi_bvalid (axi_bvalid ),
.m_axi_bready (axi_bready ),
.m_axi_araddr (axi_araddr ),
.m_axi_arvalid (axi_arvalid ),
.m_axi_arready (axi_arready ),
.m_axi_rresp (axi_rresp ),
.m_axi_rdata (axi_rdata ),
.m_axi_rvalid (axi_rvalid ),
.m_axi_rready (axi_rready )
);
reg_apb3#(
.ADDR_WTH (10 )
)
u_reg_apb3
(
//Globle Signals
//
//APB3 Slave Interface
.s_apb3_clk (clk_50m ),
.s_apb3_rstn (clk_50m_rstn ),
.s_apb3_paddr (ex_apb3_paddr ),
.s_apb3_psel (ex_apb3_psel ),
.s_apb3_penable (ex_apb3_penable ),
.s_apb3_pready (ex_apb3_pready ),
.s_apb3_pwrite (ex_apb3_pwrite ),
.s_apb3_pwdata (ex_apb3_pwdata ),
.s_apb3_prdata (ex_apb3_prdata ),
.s_apb3_pslverror (ex_apb3_pslverror ),
//Cfg Space Registers
//--Example Registers Field
.mac_sw_rst (mac_sw_rst ),
.axi4_st_mux_select (axi4_st_mux_select ),
.pat_mux_select (pat_mux_select ),
.udp_pat_gen_en (udp_pat_gen_en ),
.mac_pat_gen_en (mac_pat_gen_en ),
.pat_gen_num (pat_gen_num ),
.pat_gen_ipg (pat_gen_ipg ),
.pat_dst_mac (pat_dst_mac ),
.pat_src_mac (pat_src_mac ),
.pat_mac_dlen (pat_mac_dlen ),
.pat_src_ip (pat_src_ip ),
.pat_dst_ip (pat_dst_ip ),
.pat_src_port (pat_src_port ),
.pat_dst_port (pat_dst_port ),
.pat_udp_dlen (pat_udp_dlen ),
.clkmux_sel (mux_clk_sw )
);
//generate if (PATTERN_TYPE == 0) begin //UDP
//
//assign mac_tx_axis_mac_tdata = 8'h0;
//assign mac_tx_axis_mac_tvalid = 1'b0;
//assign mac_tx_axis_mac_tlast = 1'b0;
/*----------------------- The Ethernet Pattern Module -----------------------*/
udp_pat_gen u_udp_pat_gen
(
//Globle Signals
.clk (tx_axis_clk ),
.rstn (mac_rstn ),
//Control Interface
.pat_gen_en (udp_pat_gen_en ),
.pat_gen_num (pat_gen_num ),
.pat_gen_ipg (pat_gen_ipg ),
//MAC Protocol Signals
.dst_mac (pat_dst_mac ),
.src_mac (pat_src_mac ),
//IP Protocol Signals
.src_ip (pat_src_ip ),
.dst_ip (pat_dst_ip ),
//UDP Protocol Signals
.src_port (pat_src_port ),
.dst_port (pat_dst_port ),
.udp_dlen (pat_udp_dlen ),
//AXI4-Stream Interface
.rclk (rx_axis_clk ),
.rrstn (mac_rstn ),
.rdata (rx_axis_mac_tdata ),
.rvalid (rx_axis_mac_tvalid ),
.rlast (rx_axis_mac_tlast ),
.tdata (udp_tx_axis_mac_tdata ),
.tvalid (udp_tx_axis_mac_tvalid ),
.tlast (udp_tx_axis_mac_tlast ),
.tready (udp_tx_axis_mac_tready )
);
//end
//else begin //MAC
//
//assign udp_tx_axis_mac_tdata = 8'h0;
//assign udp_tx_axis_mac_tvalid = 1'b0;
//assign udp_tx_axis_mac_tlast = 1'b0;
mac_pat_gen u_mac_pat_gen
(
//Globle Signals
.clk (tx_axis_clk ),
.rstn (mac_rstn ),
//Control Interface
.pat_gen_en (mac_pat_gen_en ),
.pat_gen_num (pat_gen_num ),
.pat_gen_ipg (pat_gen_ipg ),
//MAC Protocol Signals
.dst_mac (pat_dst_mac ),
.src_mac (pat_src_mac ),
.mac_dlen (pat_mac_dlen ),
//AXI4-Stream Interface
.rclk (rx_axis_clk ),
.rrstn (mac_rstn ),
.rdata (rx_axis_mac_tdata ),
.rvalid (rx_axis_mac_tvalid ),
.rlast (rx_axis_mac_tlast ),
.tdata (mac_tx_axis_mac_tdata ),
.tvalid (mac_tx_axis_mac_tvalid ),
.tlast (mac_tx_axis_mac_tlast ),
.tready (mac_tx_axis_mac_tready )
);
//end
//endgenerate
axi4_st_mux u_pat_mux
(
//Globle Signals
.mux_select (pat_mux_select ),//0:udp pat; 1:mac pat;
//Mux In 0 Interface
.tdata0 (udp_tx_axis_mac_tdata ),
.tvalid0 (udp_tx_axis_mac_tvalid ),
.tlast0 (udp_tx_axis_mac_tlast ),
.tuser0 (1'b0 ),
.tready0 (udp_tx_axis_mac_tready ),
//Mux In 1 Interface
.tdata1 (mac_tx_axis_mac_tdata ),
.tvalid1 (mac_tx_axis_mac_tvalid ),
.tlast1 (mac_tx_axis_mac_tlast ),
.tuser1 (1'b0 ),
.tready1 (mac_tx_axis_mac_tready ),
//Mux Out Interface
.tdata (pat_tx_axis_mac_tdata ),
.tvalid (pat_tx_axis_mac_tvalid ),
.tlast (pat_tx_axis_mac_tlast ),
.tuser (pat_tx_axis_mac_tuser ),
.tready (pat_tx_axis_mac_tready )
);
/*----------------------- The Tx AXI4 St Mux Module -----------------------*/
axi4_st_mux u_tx_axi4st_mux
(
//Globle Signals
.mux_select (axi4_st_mux_select ),//0:pat; 1:rx2tx loopback;
//Mux In 0 Interface
.tdata0 (pat_tx_axis_mac_tdata ),
.tvalid0 (pat_tx_axis_mac_tvalid ),
.tlast0 (pat_tx_axis_mac_tlast ),
.tuser0 (pat_tx_axis_mac_tuser ),
.tready0 (pat_tx_axis_mac_tready ),
//Mux In 1 Interface
.tdata1 (loop_tx_axis_mac_tdata ),
.tvalid1 (loop_tx_axis_mac_tvalid ),
.tlast1 (loop_tx_axis_mac_tlast ),
.tuser1 (loop_tx_axis_mac_tuser ),
.tready1 (loop_tx_axis_mac_tready ),
//Mux Out Interface
.tdata (tx_axis_mac_tdata ),
.tvalid (tx_axis_mac_tvalid ),
.tlast (tx_axis_mac_tlast ),
.tuser (tx_axis_mac_tuser ),
.tready (tx_axis_mac_tready )
);
/*----------------------- The Tri-mode Ethernet MAC core -----------------------*/
gTSE u_tsemac
(
//Globle Signals
.mac_reset (mac_reset ),
.proto_reset (proto_reset ),
.tx_mac_aclk (clk_125m ),
.rx_mac_aclk ( ),
.eth_speed ( ),
//Receive AXI4-Stream Interface
.rx_axis_clk (rx_axis_clk ),
.rx_axis_mac_tdata (rx_axis_mac_tdata ),
.rx_axis_mac_tvalid (rx_axis_mac_tvalid ),
.rx_axis_mac_tlast (rx_axis_mac_tlast ),
.rx_axis_mac_tstrb (),
.rx_axis_mac_tuser (rx_axis_mac_tuser ),
.rx_axis_mac_tready (rx_axis_mac_tready ),
//Transmit AXI4-Stream Interface
.tx_axis_clk (tx_axis_clk ),
.tx_axis_mac_tdata (tx_axis_mac_tdata ),
.tx_axis_mac_tvalid (tx_axis_mac_tvalid ),
.tx_axis_mac_tlast (tx_axis_mac_tlast ),
.tx_axis_mac_tstrb (1'b1 ),
.tx_axis_mac_tuser (tx_axis_mac_tuser ),
.tx_axis_mac_tready (tx_axis_mac_tready ),
//--RGMII Interface
.rgmii_txd_HI (rgmii_txd_HI ),
.rgmii_txd_LO (rgmii_txd_LO ),
.rgmii_tx_ctl_HI (rgmii_tx_ctl_HI ),
.rgmii_tx_ctl_LO (rgmii_tx_ctl_LO ),
.rgmii_txc_HI (rgmii_txc_HI ),
.rgmii_txc_LO (rgmii_txc_LO ),
.rgmii_rxd_HI (rgmii_rxd_HI ),
.rgmii_rxd_LO (rgmii_rxd_LO ),
.rgmii_rx_ctl_HI (rgmii_rx_ctl_HI ),
.rgmii_rx_ctl_LO (rgmii_rx_ctl_LO ),
.rgmii_rxc (rgmii_rxc ),
//AXI4-Lite Interface
.s_axi_aclk (clk_50m ),
.s_axi_awaddr (axi_awaddr ),
.s_axi_awvalid (axi_awvalid ),
.s_axi_awready (axi_awready ),
.s_axi_wdata (axi_wdata ),
.s_axi_wvalid (axi_wvalid ),
.s_axi_wready (axi_wready ),
.s_axi_bresp (axi_bresp ),
.s_axi_bvalid (axi_bvalid ),
.s_axi_bready (axi_bready ),
.s_axi_araddr (axi_araddr ),
.s_axi_arvalid (axi_arvalid ),
.s_axi_arready (axi_arready ),
.s_axi_rresp (axi_rresp ),
.s_axi_rdata (axi_rdata ),
.s_axi_rvalid (axi_rvalid ),
.s_axi_rready (axi_rready ),
//MDIO Interface
.Mdo (phy_mdo ),
.MdoEn (phy_mdo_en ),
.Mdi (phy_mdi ),
.Mdc (phy_mdc )
);
/*----------------------- User Interface Loopback Module ----------------------------*/
mac_rx2tx u_mac_rx2tx
(
//Globle Signals
//
//Receive AXI4-Stream Interface
.rx_axis_clk (rx_axis_clk ),
.rx_axis_rstn (mac_rstn ),
.rx_axis_mac_tdata (rx_axis_mac_tdata ),
.rx_axis_mac_tvalid (rx_axis_mac_tvalid ),
.rx_axis_mac_tlast (rx_axis_mac_tlast ),
.rx_axis_mac_tuser (rx_axis_mac_tuser ),
.rx_axis_mac_tready (rx_axis_mac_tready ),
//Transmit AXI4-Stream Interface
.tx_axis_clk (tx_axis_clk ),
.tx_axis_rstn (mac_rstn ),
.tx_axis_mac_tdata (loop_tx_axis_mac_tdata ),
.tx_axis_mac_tvalid (loop_tx_axis_mac_tvalid ),
.tx_axis_mac_tlast (loop_tx_axis_mac_tlast ),
.tx_axis_mac_tuser (loop_tx_axis_mac_tuser ),
.tx_axis_mac_tready (loop_tx_axis_mac_tready )
);
endmodule

92
fpga/ip/gTSE/T120F324_devkit/temac_ex.xml Normal file
View File

@@ -0,0 +1,92 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="temac_ex" description="" last_change_date="Wed November 17 2021 12:59:07" location="/projects/SWIP/shlim/efx_IP/efx_tsemac/fpga/T120F324_devkit" sw_version="2021.M.296" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T120F324"/>
<efx:timing_model name="C4"/>
</efx:device_info>
<efx:design_info def_veri_version="verilog_2k" def_vhdl_version="vhdl_2008">
<efx:top_module name="temac_ex"/>
<efx:design_file name="udp_pat_gen.v" version="default" library="default"/>
<efx:design_file name="mac_rx2tx.v" version="default" library="default"/>
<efx:design_file name="rgmii_2_rmii.v" version="default" library="default"/>
<efx:design_file name="reg_apb3.v" version="default" library="default"/>
<efx:design_file name="DaulClkFifo.v" version="default" library="default"/>
<efx:design_file name="temac_ex.v" version="default" library="default"/>
<efx:design_file name="mac_pat_gen.v" version="default" library="default"/>
<efx:design_file name="gTSE.sv" version="default" library="default"/>
<efx:design_file name="axi4_st_mux.v" version="default" library="default"/>
<efx:design_file name="header.v" version="default" library="default"/>
<efx:design_file name="apb3_2_axi4_lite.v" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
</efx:design_info>
<efx:constraint_info>
<efx:sdc_file name="timing.sdc"/>
<efx:inter_file name=""/>
</efx:constraint_info>
<efx:sim_info/>
<efx:misc_info/>
<efx:ip_info>
<efx:ip instance_name="sapphire" path="ip/sapphire/settings.json">
<efx:ip_src_file name="sapphire.v"/>
</efx:ip>
</efx:ip_info>
<efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
<efx:param name="mode" value="speed" value_type="e_option"/>
<efx:param name="max_ram" value="-1" value_type="e_integer"/>
<efx:param name="max_mult" value="-1" value_type="e_integer"/>
<efx:param name="infer-clk-enable" value="3" value_type="e_option"/>
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/>
<efx:param name="fanout-limit" value="0" value_type="e_integer"/>
<efx:param name="seq_opt" value="0" value_type="e_option"/>
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="retiming" value="1" value_type="e_option"/>
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/>
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="include" value="ip/sapphire" value_type="e_string"/>
<efx:param name="min-sr-fanout" value="0" value_type="e_integer"/>
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
<efx:param name="operator-sharing" value="0" value_type="e_option"/>
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/>
<efx:param name="blackbox-error" value="1" value_type="e_option"/>
<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
<efx:param name="verbose" value="off" value_type="e_bool"/>
<efx:param name="seed" value="8" value_type="e_integer"/>
<efx:param name="placer_effort_level" value="2" value_type="e_option"/>
<efx:param name="max_threads" value="-1" value_type="e_integer"/>
<efx:param name="beneficial_skew" value="on" value_type="e_option"/>
</efx:place_and_route>
<efx:bitstream_generation tool_name="efx_pgm">
<efx:param name="mode" value="active" value_type="e_option"/>
<efx:param name="width" value="1" value_type="e_option"/>
<efx:param name="cold_boot" value="off" value_type="e_bool"/>
<efx:param name="cascade" value="off" value_type="e_option"/>
<efx:param name="enable_roms" value="on" value_type="e_option"/>
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
<efx:param name="enable_crc_check" value="off" value_type="e_bool"/>
<efx:param name="bitstream_compression" value="on" value_type="e_bool"/>
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option"/>
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
<efx:param name="generate_bit" value="on" value_type="e_bool"/>
<efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
<efx:param name="generate_hex" value="on" value_type="e_bool"/>
<efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
<efx:param name="jtag_usercode" value="0xFFFFFFFF"/>
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
<efx:param name="profile" value="NONE" value_type="e_string"/>
</efx:debugger>
</efx:project>

53
fpga/ip/gTSE/T120F324_devkit/timing.sdc Normal file
View File

@@ -0,0 +1,53 @@
################################## Clock Constraints ##########################
create_clock -period 20.00 clk
create_clock -period 8.00 clk_125m
create_clock -waveform {2.00 6.00} -period 8.00 clk_125m_90deg
create_clock -period 8.00 rgmii_rxc
create_clock -period 100.00 [get_ports {jtag_inst1_TCK}]
####################################################################################################################################
# Timing Mode Constrains
####################################################################################################################################
set_clock_groups -exclusive -group {clk} -group {clk_125m} -group {clk_125m_90deg} -group {rgmii_rxc} -group {jtag_inst1_TCK}
# GPIO Constraints
####################
set_input_delay -clock rgmii_rxc -max 6.168 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}]
set_input_delay -clock rgmii_rxc -min 3.084 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}]
set_input_delay -clock rgmii_rxc -max 6.168 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}]
set_input_delay -clock rgmii_rxc -min 3.084 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}]
set_input_delay -clock rgmii_rxc -max 6.168 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}]
set_input_delay -clock rgmii_rxc -min 3.084 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}]
set_input_delay -clock rgmii_rxc -max 6.168 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}]
set_input_delay -clock rgmii_rxc -min 3.084 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}]
set_output_delay -clock_fall -clock clk_125m_90deg -max -4.700 [get_ports {rgmii_txc_LO rgmii_txc_HI}]
set_output_delay -clock_fall -clock clk_125m_90deg -min -2.571 [get_ports {rgmii_txc_LO rgmii_txc_HI}]
set_output_delay -clock clk_125m -max -4.700 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}]
set_output_delay -clock clk_125m -min -2.571 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}]
set_output_delay -clock clk_125m -max -4.700 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}]
set_output_delay -clock clk_125m -min -2.571 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}]
set_output_delay -clock clk_125m -max -4.700 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}]
set_output_delay -clock clk_125m -min -2.571 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}]
set_output_delay -clock clk_125m -max -4.700 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}]
set_output_delay -clock clk_125m -min -2.571 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}]
# LVDS RX GPIO Constraints
############################
set_input_delay -clock rgmii_rxc -max 6.100 [get_ports {rgmii_rx_ctl}]
set_input_delay -clock rgmii_rxc -min 3.050 [get_ports {rgmii_rx_ctl}]
set_output_delay -clock clk_125m -max -5.210 [get_ports {rgmii_tx_ctl}]
set_output_delay -clock clk_125m -min -2.480 [get_ports {rgmii_tx_ctl}]
# LVDS Rx Constraints
####################
# JTAG Constraints
####################
set_output_delay -clock jtag_inst1_TCK -max 0.111 [get_ports {jtag_inst1_TDO}]
set_output_delay -clock jtag_inst1_TCK -min 0.053 [get_ports {jtag_inst1_TDO}]
set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.267 [get_ports {jtag_inst1_CAPTURE}]
set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.134 [get_ports {jtag_inst1_CAPTURE}]
set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.231 [get_ports {jtag_inst1_SEL}]
set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.116 [get_ports {jtag_inst1_SEL}]
set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.321 [get_ports {jtag_inst1_SHIFT}]
set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.161 [get_ports {jtag_inst1_SHIFT}]

497
fpga/ip/gTSE/T120F324_devkit/udp_pat_gen.v Normal file
View File

@@ -0,0 +1,497 @@
/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module udp_pat_gen
(
//Globle Signals
input clk,
input rstn,
//Control Interface
input pat_gen_en,
input [15:0] pat_gen_num,//When value is 0, it's infinite mode
input [15:0] pat_gen_ipg,
//MAC Protocol Signals
input [47:0] dst_mac,
input [47:0] src_mac,
//IP Protocol Signals
input [31:0] src_ip,
input [31:0] dst_ip,
//UDP Protocol Signals
input [15:0] udp_dlen,
input [15:0] src_port,
input [15:0] dst_port,
//AXI4-Stream Interface
input rclk,
input rrstn,
input [7:0] rdata,
input rvalid,
input rlast,
output reg [7:0] tdata,
output reg tvalid,
output reg tlast,
input tready
);
// Parameter Define
localparam VER = 4'h4;//IPv4
localparam IHL = 4'h5;//Internet Header Length
localparam TOS = 8'h0;//Type Of Service
localparam FLG = 3'h0;//Flags
localparam TTL = 8'h40;//Time To Live
localparam PTC = 8'h11;//UDP Protocol
localparam IDLE = 3'h0;
localparam UDP_CHKSUM = 3'h1;
localparam IP_CHKSUM = 3'h2;
localparam PAT_IPG = 3'h3;
localparam PAT_GEN = 3'h4;
// Register Define
reg [2:0] cur_state;
reg [2:0] next_state;
reg pat_gen_en_dl1;
reg pat_gen_en_dl2;
reg [31:0] src_ip_r;
reg [31:0] dst_ip_r;
reg [15:0] src_port_r;
reg [15:0] dst_port_r;
reg pat_en;
reg infinite_en;
reg [15:0] num_cnt;
reg [15:0] udp_chksum_cnt;
reg [3:0] ip_chksum_cnt;
reg [15:0] ipg_cnt;
reg [15:0] pat_cnt;
reg [15:0] udp_len;
reg [15:0] udp_chksum_num;
reg [7:0] udp_data_h;
reg [7:0] udp_data_l;
reg [16:0] udp_chksum_r;
reg [15:0] udp_chksum;
reg [15:0] ip_len;
reg [15:0] ip_id;
reg [12:0] ip_ofs;
reg [16:0] ip_chksum_r;
reg [15:0] ip_chksum;
reg [15:0] pat_gen_num_r;
reg [15:0] pat_gen_ipg_r;
reg [47:0] dst_mac_r;
reg [47:0] src_mac_r;
reg [15:0] udp_dlen_r;
// Wire Define
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0) begin
pat_gen_num_r <= 16'h0;
pat_gen_ipg_r <= 16'h0;
dst_mac_r <= 48'h0;
src_mac_r <= 48'h0;
udp_dlen_r <= 16'h0;
end
else begin
pat_gen_num_r <= pat_gen_num;
pat_gen_ipg_r <= pat_gen_ipg;
dst_mac_r <= dst_mac;
src_mac_r <= src_mac;
udp_dlen_r <= udp_dlen;
end
end
/*----------------------- FSM Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
cur_state <= IDLE;
else
cur_state <= next_state;
end
always @(*)
begin
case(cur_state)
IDLE :
if(pat_en == 1'b1)
next_state = UDP_CHKSUM;
else
next_state = IDLE;
UDP_CHKSUM :
if(udp_chksum_cnt == udp_chksum_num)
next_state = IP_CHKSUM;
else
next_state = UDP_CHKSUM;
IP_CHKSUM :
if(ip_chksum_cnt == 4'd9)
next_state = PAT_GEN;
else
next_state = IP_CHKSUM;
PAT_IPG :
if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0)))
next_state = IDLE;
else if(ipg_cnt == pat_gen_ipg_r)
next_state = IP_CHKSUM;
else
next_state = PAT_IPG;
PAT_GEN :
if((tlast == 1'b1) && (tready == 1'b1))
next_state = PAT_IPG;
else
next_state = PAT_GEN;
default :
next_state = IDLE;
endcase
end
/*----------------------- Generator Control Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
begin
pat_gen_en_dl1 <= 1'h0;
pat_gen_en_dl2 <= 1'h0;
end
else
begin
pat_gen_en_dl1 <= pat_gen_en;
pat_gen_en_dl2 <= pat_gen_en_dl1;
end
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
begin
src_ip_r <= 32'h0;
dst_ip_r <= 32'h0;
src_port_r <= 16'h0;
dst_port_r <= 16'h0;
end
else
begin
src_ip_r <= src_ip;
dst_ip_r <= dst_ip;
src_port_r <= src_port;
dst_port_r <= dst_port;
end
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
pat_en <= 1'h0;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
pat_en <= 1'h1;
else if((cur_state == IDLE) && (pat_en == 1'b1))
pat_en <= 1'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
infinite_en <= 1'h0;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0))
infinite_en <= 1'h1;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
infinite_en <= 1'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
num_cnt <= 16'h0;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
num_cnt <= pat_gen_num_r;
else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0))
num_cnt <= num_cnt - 1'b1;
end
/*----------------------- UDP Protocol Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
udp_len <= 16'h0;
else
udp_len <= udp_dlen_r + 16'd8;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
udp_chksum_num <= 16'h0;
else if(udp_dlen_r[0] == 1'b1)
udp_chksum_num <= udp_dlen_r[15:1] + 16'd10;
else
udp_chksum_num <= udp_dlen_r[15:1] + 16'd9;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
begin
udp_data_h <= 8'h0;
udp_data_l <= 8'h0;
end
else if(cur_state == IDLE)
begin
udp_data_h <= 8'h0;
udp_data_l <= 8'h1;
end
else if((cur_state == UDP_CHKSUM) && (udp_chksum_cnt >= 16'h9))
begin
udp_data_h <= udp_data_h + 8'h2;
udp_data_l <= udp_data_l + 8'h2;
end
end
//udp checksum calculate
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
udp_chksum_r <= 17'h0;
else if(cur_state == IDLE)
udp_chksum_r <= 17'h0;
else if(cur_state == UDP_CHKSUM) begin
if (udp_chksum_cnt <= 16'd8) begin
case(udp_chksum_cnt[3:0])
4'd0 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[31:16] + udp_chksum_r[16];
4'd1 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[15:0] + udp_chksum_r[16];
4'd2 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[31:16] + udp_chksum_r[16];
4'd3 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[15:0] + udp_chksum_r[16];
4'd4 : udp_chksum_r <= udp_chksum_r[15:0] + 16'h11 + udp_chksum_r[16];
4'd5 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16];
4'd6 : udp_chksum_r <= udp_chksum_r[15:0] + src_port_r + udp_chksum_r[16];
4'd7 : udp_chksum_r <= udp_chksum_r[15:0] + dst_port_r + udp_chksum_r[16];
4'd8 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16];
default : udp_chksum_r <= 17'h0;
endcase
end
else begin
if(udp_chksum_cnt == udp_chksum_num)
udp_chksum_r <= udp_chksum_r[15:0] + udp_chksum_r[16];
else if((udp_chksum_cnt == udp_chksum_num-1) && (udp_dlen_r[0] == 1'b1))
udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,8'h0} + udp_chksum_r[16];
else
udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,udp_data_l} + udp_chksum_r[16];
end
end
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
udp_chksum <= 16'h0;
else
udp_chksum <= ~udp_chksum_r[15:0];
end
/*----------------------- IP Protocol Region ----------------------------*/
//IP Frame Total Length
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_len <= 16'h0;
else
ip_len <= udp_len + 16'd20;
end
//IP Frame Identification
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_id <= 16'h0;
else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1))
ip_id <= ip_id + 1'b1;
end
//IP Frame Fragment Offset
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_chksum <= 16'h0;
else
ip_chksum <= ~ip_chksum_r[15:0];
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_ofs <= 13'h0;
end
//ip checksum calculate
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_chksum_r <= 16'h0;
else if(cur_state == IDLE)
ip_chksum_r <= 16'h0;
else if(cur_state == IP_CHKSUM) begin
case(ip_chksum_cnt)
4'd0 : ip_chksum_r <= ip_chksum_r[15:0] + {VER,IHL,TOS} + ip_chksum_r[16];
4'd1 : ip_chksum_r <= ip_chksum_r[15:0] + ip_len + ip_chksum_r[16];
4'd2 : ip_chksum_r <= ip_chksum_r[15:0] + ip_id + ip_chksum_r[16];
4'd3 : ip_chksum_r <= ip_chksum_r[15:0] + {FLG,ip_ofs} + ip_chksum_r[16];
4'd4 : ip_chksum_r <= ip_chksum_r[15:0] + {TTL,PTC} + ip_chksum_r[16];
4'd5 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[31:16] + ip_chksum_r[16];
4'd6 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[15:0] + ip_chksum_r[16];
4'd7 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[31:16] + ip_chksum_r[16];
4'd8 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[15:0] + ip_chksum_r[16];
4'd9 : ip_chksum_r <= ip_chksum_r[15:0] + ip_chksum_r[16];
endcase
end
else if(cur_state == PAT_IPG)
ip_chksum_r <= 16'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_chksum <= 16'h0;
else
ip_chksum <= ~ip_chksum_r[15:0];
end
/*----------------------- Pattern Counter Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
udp_chksum_cnt <= 16'h0;
else if(cur_state == UDP_CHKSUM)
udp_chksum_cnt <= udp_chksum_cnt + 1'b1;
else
udp_chksum_cnt <= 16'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_chksum_cnt <= 4'h0;
else if(cur_state == IP_CHKSUM)
ip_chksum_cnt <= ip_chksum_cnt + 1'b1;
else
ip_chksum_cnt <= 4'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ipg_cnt <= 16'h0;
else if(cur_state == PAT_IPG)
ipg_cnt <= ipg_cnt + 1'b1;
else
ipg_cnt <= 8'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
pat_cnt <= 16'h0;
else if(cur_state != PAT_GEN)
pat_cnt <= 16'h0;
else if(tready == 1'b1)
pat_cnt <= pat_cnt + 1'b1;
end
/*----------------------- Pattern Generator Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
tvalid <= 1'b0;
else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1))
tvalid <= 1'b1;
else if((tready == 1'b1) && (tlast == 1'b1))
tvalid <= 1'b0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
tdata <= 8'h0;
else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd42))
case(pat_cnt[5:0])
6'd0 : tdata <= dst_mac_r[5*8 +: 8];
6'd1 : tdata <= dst_mac_r[4*8 +: 8];
6'd2 : tdata <= dst_mac_r[3*8 +: 8];
6'd3 : tdata <= dst_mac_r[2*8 +: 8];
6'd4 : tdata <= dst_mac_r[1*8 +: 8];
6'd5 : tdata <= dst_mac_r[0*8 +: 8];
6'd6 : tdata <= src_mac_r[5*8 +: 8];
6'd7 : tdata <= src_mac_r[4*8 +: 8];
6'd8 : tdata <= src_mac_r[3*8 +: 8];
6'd9 : tdata <= src_mac_r[2*8 +: 8];
6'd10 : tdata <= src_mac_r[1*8 +: 8];
6'd11 : tdata <= src_mac_r[0*8 +: 8];
6'd12 : tdata <= 8'h08;
6'd13 : tdata <= 8'h00;
6'd14 : tdata <= {VER,IHL};
6'd15 : tdata <= TOS;
6'd16 : tdata <= ip_len[15:8];
6'd17 : tdata <= ip_len[7:0];
6'd18 : tdata <= ip_id[15:8];
6'd19 : tdata <= ip_id[7:0];
6'd20 : tdata <= {FLG,ip_ofs[12:8]};
6'd21 : tdata <= ip_ofs[7:0];
6'd22 : tdata <= TTL;
6'd23 : tdata <= PTC;
6'd24 : tdata <= ip_chksum[15:8];
6'd25 : tdata <= ip_chksum[7:0];
6'd26 : tdata <= src_ip_r[3*8 +: 8];
6'd27 : tdata <= src_ip_r[2*8 +: 8];
6'd28 : tdata <= src_ip_r[1*8 +: 8];
6'd29 : tdata <= src_ip_r[0*8 +: 8];
6'd30 : tdata <= dst_ip_r[3*8 +: 8];
6'd31 : tdata <= dst_ip_r[2*8 +: 8];
6'd32 : tdata <= dst_ip_r[1*8 +: 8];
6'd33 : tdata <= dst_ip_r[0*8 +: 8];
6'd34 : tdata <= src_port_r[15:8];
6'd35 : tdata <= src_port_r[7:0];
6'd36 : tdata <= dst_port_r[15:8];
6'd37 : tdata <= dst_port_r[7:0];
6'd38 : tdata <= udp_len[15:8];
6'd39 : tdata <= udp_len[7:0];
6'd40 : tdata <= udp_chksum[15:8];
6'd41 : tdata <= udp_chksum[7:0];
6'd42 : tdata <= 8'h0;//UDP First Data
default : tdata <= tdata + 1'b1;
endcase
else if((cur_state == PAT_GEN) && (tready == 1'b1))
tdata <= tdata + 1'b1;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
tlast <= 1'b0;
else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == ip_len+16'd13))
tlast <= 1'b1;
else if(tready == 1'b1)
tlast <= 1'b0;
end
endmodule