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Byron Lathi
2026-04-14 21:34:37 -07:00
commit 50f8791588
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fpga/ip/gTSE/Testbench/DaulClkFifo.v Normal file
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`timescale 1ns/100ps
module DC_FIFO
# (
parameter FIFO_MODE = "Normal" , //"Normal"; //"ShowAhead"
parameter DATA_WIDTH = 8 ,
parameter FIFO_DEPTH = 512 ,
parameter AW_C = $clog2(FIFO_DEPTH),
parameter DW_C = DATA_WIDTH ,
parameter DD_C = 2**AW_C
)
(
//System Signal
input Reset , //System Reset
//Write Signal
input WrClk , //(I)Wirte Clock
input WrEn , //(I)Write Enable
output [AW_C-1:0] WrDNum , //(O)Write Data Number In Fifo
output WrFull , //(I)Write Full
input [DW_C -1:0] WrData , //(I)Write Data
//Read Signal
input RdClk , //(I)Read Clock
input RdEn , //(I)Read Enable
output [AW_C-1:0] RdDNum , //(O)Radd Data Number In Fifo
output RdEmpty , //(O)Read FifoEmpty
output [DW_C-1 :0] RdData //(O)Read Data
);
//Define Parameter
///////////////////////////////////////////////////////////////
localparam TCo_C = 0 ;
reg [1:0] WrClkRstGen = 2'h3;
reg [1:0] RdClkRstGen = 2'h3;
always @( posedge WrClk or posedge Reset)
begin
if (Reset) WrClkRstGen <= # TCo_C 2'h3;
else
begin
WrClkRstGen[0] <= # TCo_C 1'h0;
WrClkRstGen[1] <= # TCo_C (&RdClkRstGen);
end
end
wire WrClkRst = WrClkRstGen[1];
///////////////////////////////////////////////////
always @( posedge RdClk or posedge Reset)
begin
if (Reset) RdClkRstGen <= # TCo_C 2'h3;
else
begin
RdClkRstGen[0] <= # TCo_C 1'h0;
RdClkRstGen[1] <= # TCo_C (&WrClkRstGen);
end
end
wire RdClkRst = RdClkRstGen[1];
///////////////////////////////////////////////////
wire FifoWrEn = WrEn;
wire [AW_C :0] WrAddrCnt ;
wire [AW_C :0] FifoWrAddr ;
wire FifoWrFull ;
FifoAddrCnt # ( .CounterWidth_C (AW_C))
U1_WrAddrCnt
(
//System Signal
.Reset ( WrClkRst ) , //System Reset
.SysClk ( WrClk ) , //System Clock
//Counter Signal
.ClkEn ( FifoWrEn ) , //(I)Clock Enable
.FifoFlag ( FifoWrFull ) , //(I)Fifo Flag
.AddrCnt ( WrAddrCnt ) , //(O)Address Counter
.Addess ( FifoWrAddr ) //(O)Address Output
);
///////////////////////////////////////////////////
reg [DW_C-1:0] FifoBuff [DD_C-1:0];
always @( posedge WrClk)
begin
if (WrEn & (~WrFull))
begin
FifoBuff[FifoWrAddr[AW_C-1:0]] <= # TCo_C WrData;
end
end
///////////////////////////////////////////////////
///////////////////////////////////////////////////
wire FifoEmpty ;
wire FifoRdEn ;
wire [AW_C :0] RdAddrCnt ;
wire [AW_C :0] FifoRdAddr ;
FifoAddrCnt #( .CounterWidth_C (AW_C))
U2_RdAddrCnt
(
//System Signal
.Reset ( RdClkRst ) , //System Reset
.SysClk ( RdClk ) , //System Clock
//Counter Signal
.ClkEn ( FifoRdEn ) , //(I)Clock Enable
.FifoFlag ( FifoEmpty ) , //(I)Fifo Flag
.AddrCnt ( RdAddrCnt ) , //(O)Address Counter
.Addess ( FifoRdAddr ) //(O)Address Output
);
///////////////////////////////////////////////////
reg [DW_C-1 :0] FifoRdData ;
always @( posedge RdClk)
begin
if (FifoRdEn) FifoRdData <= # TCo_C FifoBuff[FifoRdAddr[AW_C-1:0]];
end
///////////////////////////////////////////////////
assign RdData = FifoRdData ; //(O)Read Data
reg [AW_C:0] WrRdAddr = {AW_C+1{1'h0}};
always @( posedge WrClk)
begin
if (WrClkRst) WrRdAddr <= # TCo_C {AW_C+1{1'h0}} ;
else WrRdAddr <= # TCo_C FifoRdAddr [AW_C:0] ;
end
///////////////////////////////////////////////////////////
wire [AW_C-1:0] WrRdAHex;
wire [AW_C-1:0] WrWrAHex;
GrayDecode #(AW_C) WRAGray2Hex (WrRdAddr [AW_C-1:0] , WrRdAHex[AW_C-1:0]);
GrayDecode #(AW_C) WWAGray2Hex (FifoWrAddr [AW_C-1:0] , WrWrAHex[AW_C-1:0]);
///////////////////////////////////////////////////////////
reg [AW_C-1:0] WrAddrDiff;
always @( posedge WrClk)
begin
if (WrFull) WrAddrDiff <= # TCo_C {AW_C{1'h1}} ;
else WrAddrDiff <= # TCo_C (WrWrAHex - WrRdAHex) ;
end
///////////////////////////////////////////////////////////
assign WrDNum = WrAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo
reg [AW_C:0] WrRdAddrReg = {AW_C+1{1'h0}};
always @( posedge WrClk)
begin
if ( WrClkRst) WrRdAddrReg <= # TCo_C {AW_C+1{1'h0}} ;
else WrRdAddrReg <= # TCo_C WrRdAddr[AW_C : 0] ;
end
///////////////////////////////////////////////////////////
reg RdAddrChg = 1'h0;
reg WrFullClr = 1'h0;
always @( posedge WrClk)
begin
if ( WrClkRst) RdAddrChg <= # TCo_C 1'h0 ;
else RdAddrChg <= # TCo_C (FifoWrFull & (WrRdAddr[AW_C-1:0] != WrRdAddrReg[AW_C-1:0]));
end
always @( posedge WrClk)
begin
if ( WrClkRst) WrFullClr <= # TCo_C 1'h0 ;
else WrFullClr <= # TCo_C (FifoWrFull & RdAddrChg);
end
///////////////////////////////////////////////////////////
reg RdAHighNext = 1'h0;
wire RdAHighRise = (~WrRdAddrReg[AW_C-1]) & WrRdAddr[AW_C-1];
always @( posedge WrClk)
begin
if (WrClkRst ) RdAHighNext <= # TCo_C 1'h0 ;
else if (RdAHighRise) RdAHighNext <= # TCo_C (~WrRdAddr[AW_C]) ;
end
///////////////////////////////////////////////////
wire FullCalc = (WrAddrCnt[AW_C-1:0] == WrRdAddr[AW_C-1:0])
&& (WrAddrCnt[AW_C ] != (WrRdAddr[AW_C-1] ? WrRdAddrReg[AW_C] : RdAHighNext) );
///////////////////////////////////////////////////
reg FullFlag = 1'h0;
always @( posedge WrClk)
begin
if (WrClkRst) FullFlag <= # TCo_C 1'h0;
else if (FullFlag) FullFlag <= # TCo_C (~WrFullClr);
else if (FifoWrEn) FullFlag <= # TCo_C FullCalc;
end
assign FifoWrFull = FullFlag;
///////////////////////////////////////////////////
assign WrFull = FifoWrFull ; //(I)Write Full
reg [AW_C :0] RdWrAddr = {AW_C+1{1'h0}};
always @( posedge RdClk)
begin
if (RdClkRst ) RdWrAddr <= # TCo_C {AW_C+1{1'h0}} ;
else RdWrAddr <= # TCo_C FifoWrAddr [AW_C:0] ;
end
///////////////////////////////////////////////////////////
wire [AW_C-1:0] RdWrAHex;
wire [AW_C-1:0] RdRdAHex;
GrayDecode # (AW_C) RWAGray2Hex (RdWrAddr [AW_C-1:0] , RdWrAHex[AW_C-1:0] );
GrayDecode # (AW_C) RRAGray2Hex (FifoRdAddr [AW_C-1:0] , RdRdAHex[AW_C-1:0] );
///////////////////////////////////////////////////////////
reg [AW_C-1:0] RdAddrDiff;
always @( posedge RdClk)
begin
if (RdEmpty ) RdAddrDiff <= # TCo_C {AW_C{1'h0}} ;
else RdAddrDiff <= # TCo_C (RdWrAHex - RdRdAHex) ;
end
///////////////////////////////////////////////////////////
assign RdDNum = RdAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo
reg [AW_C:0] RdWrAddrReg = {AW_C+1{1'h0}};
always @( posedge RdClk)
begin
if (RdClkRst) RdWrAddrReg <= # TCo_C {AW_C+1{1'h0}} ;
else RdWrAddrReg <= # TCo_C RdWrAddr [AW_C:0] ;
end
///////////////////////////////////////////////////////////
reg WrAddrChg = 1'h0;
reg EmptyClr = 1'h0;
always @( posedge RdClk)
begin
if (RdClkRst) WrAddrChg <= # TCo_C 1'h0 ;
else WrAddrChg <= # TCo_C FifoEmpty & (RdWrAddr[AW_C-1:0] != RdWrAddrReg[AW_C-1:0]);
end
always @( posedge RdClk)
begin
if (RdClkRst) EmptyClr <= # TCo_C 1'h0;
else EmptyClr <= # TCo_C (FifoEmpty & WrAddrChg);
end
///////////////////////////////////////////////////////////
reg WrAHighNext = 1'h0;
wire WrAHighRise = (~RdWrAddrReg[AW_C-1]) & RdWrAddr[AW_C-1];
always @( posedge RdClk)
begin
if (RdClkRst) WrAHighNext <= # TCo_C 1'h0 ;
else if (WrAHighRise) WrAHighNext <= # TCo_C (~RdWrAddr[AW_C]);
end
///////////////////////////////////////////////////////////
wire EmptyCalc = (RdAddrCnt[AW_C-1:0] == RdWrAddr[AW_C-1:0])
&& (RdAddrCnt[AW_C ] == (RdWrAddr[AW_C-1] ? RdWrAddrReg[AW_C] : WrAHighNext));
///////////////////////////////////////////////////////////
reg EmptyFlag = 1'h1;
always @( posedge RdClk)
begin
if (RdClkRst) EmptyFlag <= # TCo_C 1'h1;
else if (EmptyFlag) EmptyFlag <= # TCo_C (~EmptyClr);
else if (FifoRdEn) EmptyFlag <= # TCo_C EmptyCalc;
end
assign FifoEmpty = EmptyFlag;
///////////////////////////////////////////////////////////
reg EmptyReg = 1'h0;
always @( posedge RdClk )
begin
if (RdClkRst) EmptyReg <= # TCo_C 1'h1;
else if (FifoRdEn) EmptyReg <= # TCo_C FifoEmpty;
end
///////////////////////////////////////////////////////////
assign RdEmpty = (FIFO_MODE == "ShowAhead") ? EmptyReg : FifoEmpty; //(O)Read FifoEmpty
reg RdFirst = 1'h0;
always @( posedge RdClk)
begin
if (FIFO_MODE == "ShowAhead")
begin
if (RdClkRst) RdFirst <= # TCo_C 1'h0 ;
else if (RdFirst) RdFirst <= # TCo_C 1'h0 ;
else if (EmptyClr) RdFirst <= # TCo_C RdEmpty ;
end
else RdFirst <= # TCo_C 1'h0 ;
end
///////////////////////////////////////////////////////////
assign FifoRdEn = RdEn || RdFirst ;
///////////////////////////////////////////////////////////
//666666666666666666666666666666666666666666666666666666666
endmodule
//////////////// DaulClkFifo //////////////////////////////
///////////////// FifoAddrCnt /////////////////////////////
module FifoAddrCnt
# (
parameter CounterWidth_C = 9 ,
parameter CW_C = CounterWidth_C
)
(
//System Signal
input Reset , //System Reset
input SysClk , //System Clock
//Counter Signal
input ClkEn , //(I)Clock Enable
input FifoFlag , //(I)Fifo Flag
output [CW_C:0] AddrCnt , //(O)Address Counter
output [CW_C:0] Addess //(O)Address Output
);
//Define Parameter
///////////////////////////////////////////////////////////
localparam TCo_C = 1;
wire [CW_C-1:0] GrayAddrCnt;
wire CarryOut;
GrayCnt #(.CounterWidth_C (CW_C))
U1_AddrCnt
(
//System Signal
.Reset ( Reset ), //System Reset
.SysClk ( SysClk ), //System Clock
//Counter Signal
.SyncClr ( 1'h0 ), //(I)Sync Clear
.ClkEn ( ClkEn ), //(I)Clock Enable
.CarryIn ( ~FifoFlag ), //(I)Carry input
.CarryOut ( CarryOut ), //(O)Carry output
.Count ( GrayAddrCnt ) //(O)Counter Value Output
);
///////////////////////////////////////////////////////////
reg CntHighBit;
always @( posedge SysClk )
begin
if (Reset) CntHighBit <= # TCo_C 1'h0;
else if (ClkEn) CntHighBit <= # TCo_C CntHighBit + CarryOut;
end
///////////////////////////////////////////////////////////
reg [CW_C:0] AddrOut; //(O)Address Output
always @(posedge SysClk)
begin
if (Reset) AddrOut <= # TCo_C {CW_C{1'h0}};
else if (ClkEn) AddrOut <= # TCo_C FifoFlag ? AddrOut : AddrCnt;
end
///////////////////////////////////////////////////////////
assign AddrCnt = {CntHighBit , GrayAddrCnt} ; //(O)Address Counter
assign Addess = AddrOut ; //(O)Address Output
//111111111111111111111111111111111111111111111111111111111
endmodule
/////////////////// FifoAddrCnt //////////////////////////
module GrayCnt
# (
parameter CounterWidth_C = 9 ,
parameter CW_C = CounterWidth_C
)
(
//System Signal
input Reset , //System Reset
input SysClk , //System Clock
//Counter Signal
input SyncClr , //(I)Sync Clear
input ClkEn , //(I)Clock Enable
input CarryIn , //(I)Carry input
output CarryOut , //(O)Carry output
output [CW_C-1:0] Count //(O)Counter Value Output
);
//Define Parameter
///////////////////////////////////////////////////////////
localparam TCo_C = 1;
wire [CW_C:0 ] CryIn ;
wire [CW_C-1:0] CryOut ;
reg [CW_C-1:0] GrayCnt;
assign CryIn[0] = CarryIn;
genvar i;
generate
for(i=0;i<CW_C;i=i+1)
begin : GrayCnt_CrayCntUnit
//////////////
always @( posedge SysClk )
begin
if (Reset) GrayCnt[i] <= # TCo_C (i>1) ? 1'h0: 1'h1 ;
else if (SyncClr) GrayCnt[i] <= # TCo_C (i>1) ? 1'h0: 1'h1 ;
else if (ClkEn) GrayCnt[i] <= # TCo_C GrayCnt[i] + CryIn[i];
end
//////////////
if (i==0)
begin
assign CryOut[0] = GrayCnt[0] && CarryIn;
assign CryIn [1] = ~GrayCnt[0] && CarryIn;
end
else
begin
assign CryOut[i ] = CryOut[ 0] && (~|GrayCnt[i:1]);
assign CryIn [i+1] = CryOut[i-1] && GrayCnt[i ] ;
end
end
endgenerate
wire GrayCarry = CryOut[CW_C-2];
///////////////////////////////////////////////////////////
reg CntHigh = 1'h0;
always @( posedge SysClk)
begin
if (Reset) CntHigh <= # TCo_C 1'h0;
else if (ClkEn) CntHigh <= # TCo_C (CntHigh + GrayCarry);
end
///////////////////////////////////////////////////////////
assign Count = {CntHigh , GrayCnt[CW_C-1:1]} ; //(O)Counter Value Output
assign CarryOut = CntHigh & GrayCarry ; //(O)Carry output
///////////////////////////////////////////////////////////
//111111111111111111111111111111111111111111111111111111111
endmodule
////////////////////// GrayCnt ////////////////////////////
module GrayDecode
# (
parameter DataWidht_C = 8
)
(
input [DataWidht_C-1:0] GrayIn,
output [DataWidht_C-1:0] HexOut
);
//Define Parameter
///////////////////////////////////////////////////////////////
parameter TCo_C = 1;
localparam DW_C = DataWidht_C;
///////////////////////////////////////////////////////////////
reg [DW_C-1:0] Hex;
integer i;
always @ (GrayIn)
begin
Hex[DW_C-1]=GrayIn[DW_C-1];
for(i=DW_C-2;i>=0;i=i-1) Hex[i]=Hex[i+1]^GrayIn[i];
end
assign HexOut = Hex;
///////////////////////////////////////////////////////////////
endmodule

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fpga/ip/gTSE/Testbench/ODDR.v Normal file
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`timescale 1 ps / 1 ps
`celldefine
module ODDR (Q, C, CE, D1, D2, R, S);
output Q;
input C;
input CE;
input D1;
input D2;
input R;
input S;
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D1_INVERTED = 1'b0;
parameter [0:0] IS_D2_INVERTED = 1'b0;
parameter SRTYPE = "SYNC";
parameter ROC_WIDTH = 100000;
localparam MODULE_NAME = "ODDR";
pulldown P1 (R);
pulldown P2 (S);
reg GSR;
reg q_out = INIT, qd2_posedge_int;
wire c_in,delay_c;
wire ce_in,delay_ce;
wire d1_in,delay_d1;
wire d2_in,delay_d2;
wire gsr_in;
wire r_in,delay_r;
wire s_in,delay_s;
assign gsr_in = GSR;
assign Q = q_out;
initial begin
GSR = 1'b1;
#(ROC_WIDTH)
GSR = 1'b0;
end
initial begin
if ((INIT != 0) && (INIT != 1)) begin
$display("Attribute Syntax Error : The attribute INIT on %s instance %m is set to %d. Legal values for this attribute are 0 or 1.", MODULE_NAME, INIT);
#1 $finish;
end
if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on %s instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", MODULE_NAME, DDR_CLK_EDGE);
#1 $finish;
end
if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on %s instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", MODULE_NAME, SRTYPE);
#1 $finish;
end
end // initial begin
always @(gsr_in or r_in or s_in) begin
if (gsr_in == 1'b1) begin
assign q_out = INIT;
assign qd2_posedge_int = INIT;
end
else if (gsr_in == 1'b0) begin
if (r_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q_out = 1'b0;
assign qd2_posedge_int = 1'b0;
end
else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q_out = 1'b1;
assign qd2_posedge_int = 1'b1;
end
else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
deassign q_out;
deassign qd2_posedge_int;
end
else if (r_in == 1'b0 && s_in == 1'b0) begin
deassign q_out;
deassign qd2_posedge_int;
end
end // if (gsr_in == 1'b0)
end // always @ (gsr_in or r_in or s_in)
always @(posedge c_in) begin
if (r_in == 1'b1) begin
q_out <= 1'b0;
qd2_posedge_int <= 1'b0;
end
else if (r_in == 1'b0 && s_in == 1'b1) begin
q_out <= 1'b1;
qd2_posedge_int <= 1'b1;
end
else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
q_out <= d1_in;
qd2_posedge_int <= d2_in;
end
// CR 527698
else if (ce_in == 1'b0 && r_in == 1'b0 && s_in == 1'b0) begin
qd2_posedge_int <= q_out;
end
end // always @ (posedge c_in)
always @(negedge c_in) begin
if (r_in == 1'b1)
q_out <= 1'b0;
else if (r_in == 1'b0 && s_in == 1'b1)
q_out <= 1'b1;
else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
if (DDR_CLK_EDGE == "SAME_EDGE")
q_out <= qd2_posedge_int;
else if (DDR_CLK_EDGE == "OPPOSITE_EDGE")
q_out <= d2_in;
end
end // always @ (negedge c_in)
assign delay_c = C;
assign delay_ce = CE;
assign delay_d1 = D1;
assign delay_d2 = D2;
assign delay_r = R;
assign delay_s = S;
assign c_in = IS_C_INVERTED ^ delay_c;
assign ce_in = delay_ce;
assign d1_in = IS_D1_INVERTED ^ delay_d1;
assign d2_in = IS_D2_INVERTED ^ delay_d2;
assign r_in = delay_r;
assign s_in = delay_s;
//*** Timing Checks Start here
specify
(C => Q) = (100:100:100, 100:100:100);
(posedge R => (Q +: 0)) = (0:0:0, 0:0:0);
(posedge S => (Q +: 0)) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule // ODDR
`endcelldefine

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fpga/ip/gTSE/Testbench/aldec/gTSE.sv Normal file
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fpga/ip/gTSE/Testbench/apb3_2_axi4_lite.v Normal file
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/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module apb3_2_axi4_lite#(
parameter ADDR_WTH = 10
)
(
//Globle Signals
input clk,
input rstn,
//APB3 Slave Interface
input [ADDR_WTH-1:0] s_apb3_paddr,
input s_apb3_psel,
input s_apb3_penable,
output reg s_apb3_pready,
input s_apb3_pwrite,//0:rd; 1:wr;
input [31:0] s_apb3_pwdata,
output reg [31:0] s_apb3_prdata,
output reg s_apb3_pslverror,
//AXI4-Lite Master Interface
output reg [ADDR_WTH-1:0] m_axi_awaddr,//Write Address. byte address.
output reg m_axi_awvalid,//Write address valid.
input m_axi_awready,//Write address ready.
output reg [31:0] m_axi_wdata,//Write data bus.
output reg m_axi_wvalid,//Write valid.
input m_axi_wready,//Write ready.
input [1:0] m_axi_bresp,//Write response.
input m_axi_bvalid,//Write response valid.
output wire m_axi_bready,//Response ready.
output reg [ADDR_WTH-1:0] m_axi_araddr,//Read address. byte address.
output reg m_axi_arvalid,//Read address valid.
input m_axi_arready,//Read address ready.
input [1:0] m_axi_rresp,//Read response.
input [31:0] m_axi_rdata,//Read data.
input m_axi_rvalid,//Read valid.
output wire m_axi_rready//Read ready.
);
// Parameter Define
parameter State_idle = 3'd0;
parameter State_wsetup = 3'd1;
parameter State_rsetup = 3'd2;
parameter State_ready = 3'd3;
parameter State_err = 3'd4;
// Register Define
reg [2:0] cur_state;
reg [2:0] next_state;
reg [7:0] timeout_cnt;
// Wire Define
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
/*----------------------- FSM Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
cur_state <= State_idle;
else
cur_state <= next_state;
end
always @(*)
begin
case(cur_state)
State_idle :
if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
next_state = State_wsetup;
else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0))
next_state = State_rsetup;
else
next_state = State_idle;
State_wsetup :
if((m_axi_awvalid == 1'b0) && (m_axi_wvalid == 1'b0))
next_state = State_ready;
else if(timeout_cnt[7] == 1'b1)
next_state = State_err;
else
next_state = State_wsetup;
State_rsetup :
if(m_axi_rvalid == 1'b1)
next_state = State_ready;
else if(timeout_cnt[7] == 1'b1)
next_state = State_err;
else
next_state = State_rsetup;
State_ready :
next_state = State_idle;
State_err :
next_state = State_idle;
default :
next_state = State_idle;
endcase
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
timeout_cnt <= 8'h0;
else if((cur_state == State_wsetup) || (cur_state == State_rsetup))
timeout_cnt <= timeout_cnt + 1'b1;
else
timeout_cnt <= 8'h0;
end
/*----------------------- APB3 Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
s_apb3_pready <= 1'b0;
else if((cur_state == State_ready) || (cur_state == State_err))
s_apb3_pready <= 1'b1;
else
s_apb3_pready <= 1'b0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
s_apb3_pslverror <= 1'b0;
else if(cur_state == State_err)
s_apb3_pslverror <= 1'b1;
else
s_apb3_pslverror <= 1'b0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
s_apb3_prdata <= 32'h0;
else if(m_axi_rvalid == 1'b1)
s_apb3_prdata <= m_axi_rdata;
end
/*----------------------- AXI4-Lite Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
m_axi_awaddr <= {ADDR_WTH{1'b0}};
else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
m_axi_awaddr <= s_apb3_paddr;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
m_axi_awvalid <= 1'b0;
else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
m_axi_awvalid <= 1'b1;
else if((m_axi_awready == 1'b1) || (cur_state == State_idle))
m_axi_awvalid <= 1'b0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
m_axi_wdata <= 32'h0;
else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
m_axi_wdata <= s_apb3_pwdata;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
m_axi_wvalid <= 1'b0;
else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
m_axi_wvalid <= 1'b1;
else if((m_axi_wready == 1'b1) || (cur_state == State_idle))
m_axi_wvalid <= 1'b0;
end
assign m_axi_bready = 1'b1;
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
m_axi_araddr <= {ADDR_WTH{1'b0}};
else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0))
m_axi_araddr <= s_apb3_paddr;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
m_axi_arvalid <= 1'b0;
else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0))
m_axi_arvalid <= 1'b1;
else if((m_axi_arready == 1'b1) || (cur_state == State_idle))
m_axi_arvalid <= 1'b0;
end
assign m_axi_rready = 1'b1;
endmodule

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/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module axi4_st_mux
(
//Globle Signals
input mux_select,
//Mux In 0 Interface
input [7:0] tdata0,
input tvalid0,
input tlast0,
input tuser0,
output wire tready0,
//Mux In 1 Interface
input [7:0] tdata1,
input tvalid1,
input tlast1,
input tuser1,
output wire tready1,
//Mux Out Interface
output wire [7:0] tdata,
output wire tvalid,
output wire tlast,
output wire tuser,
input tready
);
// Parameter Define
// Register Define
// Wire Define
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
assign tdata = (mux_select) ? tdata1 : tdata0;
assign tvalid = (mux_select) ? tvalid1 : tvalid0;
assign tlast = (mux_select) ? tlast1 : tlast0;
assign tuser = (mux_select) ? tuser1 : tuser0;
assign tready0 = (mux_select) ? 1'b1 : tready;
assign tready1 = (mux_select) ? tready : 1'b1;
endmodule

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.288.2.10
// IP Version: 7.1
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam VERSION = 16;
localparam TXFIFO_EN = 1'b1;
localparam RXFIFO_EN = 1'b1;
localparam TXFIFO_DTH = 4096;
localparam RXFIFO_DTH = 4096;
localparam PHY_INTF_MODE = 0;
localparam AXIS_DW = 8;
localparam RGMII_RXC_EDGE = 1'b1;
localparam RGMII_TXC_DLY = 1'b1;
localparam INTER_PACKET_GAP = 6'd12;
localparam MTU_FRAME_LENGTH = 16'd1518;
localparam MAC_SOURCE_ADDRESS = 48'd0;
localparam ENABLE_BROADCAST_FILTERING = 1'b1;
localparam LOOPBACK_EN = 1'b1;
localparam APBIF = 1'b0;
localparam FAMILY = "TITANIUM";

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`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif

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/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module mac_pat_gen
(
//Globle Signals
input clk,
input rstn,
//Control Interface
input pat_gen_en,
input [15:0] pat_gen_num,//When value is 0, it's infinite mode
input [15:0] pat_gen_ipg,
//MAC Protocol Signals
input [47:0] dst_mac,
input [47:0] src_mac,
input [15:0] mac_dlen,
//AXI4-Stream Interface
input rclk,
input rrstn,
input [7:0] rdata,
input rvalid,
input rlast,
output reg [7:0] tdata,
output reg tvalid,
output reg tlast,
input tready
);
// Parameter Define
localparam IDLE = 2'h0;
localparam PAT_IPG = 2'h1;
localparam PAT_GEN = 2'h2;
// Register Define
reg pat_gen_en_dl1;
reg pat_gen_en_dl2;
reg [1:0] cur_state;
reg [1:0] next_state;
reg pat_en;
reg infinite_en;
reg [15:0] num_cnt;
reg [15:0] ipg_cnt;
reg [15:0] pat_cnt;
reg [15:0] pat_gen_num_r;
reg [15:0] pat_gen_ipg_r;
reg [47:0] dst_mac_r;
reg [47:0] src_mac_r;
reg [15:0] mac_dlen_r;
// Wire Define
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0) begin
pat_gen_num_r <= 16'h0;
pat_gen_ipg_r <= 16'h0;
dst_mac_r <= 48'h0;
src_mac_r <= 48'h0;
mac_dlen_r <= 16'h0;
end
else begin
pat_gen_num_r <= pat_gen_num;
pat_gen_ipg_r <= pat_gen_ipg;
dst_mac_r <= dst_mac;
src_mac_r <= src_mac;
mac_dlen_r <= mac_dlen;
end
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
begin
pat_gen_en_dl1 <= 1'h0;
pat_gen_en_dl2 <= 1'h0;
end
else
begin
pat_gen_en_dl1 <= pat_gen_en;
pat_gen_en_dl2 <= pat_gen_en_dl1;
end
end
/*----------------------- FSM Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
cur_state <= IDLE;
else
cur_state <= next_state;
end
always @(*)
begin
case(cur_state)
IDLE :
if(pat_en == 1'b1)
next_state = PAT_GEN;
else
next_state = IDLE;
PAT_IPG :
if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0)))
next_state = IDLE;
else if(ipg_cnt == pat_gen_ipg_r)
next_state = PAT_GEN;
else
next_state = PAT_IPG;
PAT_GEN :
if((tlast == 1'b1) && (tready == 1'b1))
next_state = PAT_IPG;
else
next_state = PAT_GEN;
default :
next_state = IDLE;
endcase
end
/*----------------------- Generator Control Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
pat_en <= 1'h0;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
pat_en <= 1'h1;
else if((cur_state == IDLE) && (pat_en == 1'b1))
pat_en <= 1'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
infinite_en <= 1'h0;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0))
infinite_en <= 1'h1;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
infinite_en <= 1'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
num_cnt <= 16'h0;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
num_cnt <= pat_gen_num_r;
else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0))
num_cnt <= num_cnt - 1'b1;
end
/*----------------------- Pattern Counter Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ipg_cnt <= 16'h0;
else if(cur_state == PAT_IPG)
ipg_cnt <= ipg_cnt + 1'b1;
else
ipg_cnt <= 8'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
pat_cnt <= 16'h0;
else if(cur_state != PAT_GEN)
pat_cnt <= 16'h0;
else if(tready == 1'b1)
pat_cnt <= pat_cnt + 1'b1;
end
/*----------------------- Pattern Generator Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
tvalid <= 1'b0;
else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1))
tvalid <= 1'b1;
else if((tready == 1'b1) && (tlast == 1'b1))
tvalid <= 1'b0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
tdata <= 8'h0;
else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd14))
case(pat_cnt[3:0])
4'd0 : tdata <= dst_mac_r[5*8 +: 8];
4'd1 : tdata <= dst_mac_r[4*8 +: 8];
4'd2 : tdata <= dst_mac_r[3*8 +: 8];
4'd3 : tdata <= dst_mac_r[2*8 +: 8];
4'd4 : tdata <= dst_mac_r[1*8 +: 8];
4'd5 : tdata <= dst_mac_r[0*8 +: 8];
4'd6 : tdata <= src_mac_r[5*8 +: 8];
4'd7 : tdata <= src_mac_r[4*8 +: 8];
4'd8 : tdata <= src_mac_r[3*8 +: 8];
4'd9 : tdata <= src_mac_r[2*8 +: 8];
4'd10 : tdata <= src_mac_r[1*8 +: 8];
4'd11 : tdata <= src_mac_r[0*8 +: 8];
4'd12 : tdata <= mac_dlen_r[15:8];
4'd13 : tdata <= mac_dlen_r[7:0];
4'd14 : tdata <= 8'h0;//MAC First Data
default : tdata <= tdata + 1'b1;
endcase
else if((cur_state == PAT_GEN) && (tready == 1'b1))
tdata <= tdata + 1'b1;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
tlast <= 1'b0;
else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == mac_dlen_r+16'd13))
tlast <= 1'b1;
else if(tready == 1'b1)
tlast <= 1'b0;
end
endmodule

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/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module mac_rx2tx
(
//Globle Signals
//
//Receive AXI4-Stream Interface
input rx_axis_clk,
input rx_axis_rstn,
input [7:0] rx_axis_mac_tdata,
input rx_axis_mac_tvalid,
input rx_axis_mac_tlast,
input rx_axis_mac_tuser,
output reg rx_axis_mac_tready,
//Transmit AXI4-Stream Interface
input tx_axis_clk,
input tx_axis_rstn,
output reg [7:0] tx_axis_mac_tdata,
output reg tx_axis_mac_tvalid,
output reg tx_axis_mac_tlast,
output reg tx_axis_mac_tuser,
input tx_axis_mac_tready
);
// Parameter Define
// Register Define
// Wire Define
wire [9:0] u1_data;
wire u1_wrreq;
wire u1_rdreq;
wire [9:0] u1_q;
wire u1_empty;
wire u1_almfull;
wire [10:0] u1_wrcnt;
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
/*----------------------- Rx Clock Region ----------------------------*/
assign u1_almfull = (u1_wrcnt >= 2045);
always @(posedge rx_axis_clk or negedge rx_axis_rstn)
begin
if(rx_axis_rstn == 1'b0)
rx_axis_mac_tready <= 1'b0;
else if(u1_almfull == 1'b1)
rx_axis_mac_tready <= 1'b0;
else
rx_axis_mac_tready <= 1'b1;
end
/*----------------------- Fifo 1 Region ----------------------------*/
DC_FIFO #(
.FIFO_MODE ("ShowAhead" ),
.DATA_WIDTH (10 ),
.FIFO_DEPTH (2048 )
)
u1
(
//System Signal
.Reset (!rx_axis_rstn ),
//Write Signal
.WrClk (rx_axis_clk ),
.WrEn (u1_wrreq ),
.WrDNum (u1_wrcnt ),
.WrFull ( ),
.WrData (u1_data ),
//Read Signal
.RdClk (tx_axis_clk ),
.RdEn (u1_rdreq ),
.RdDNum ( ),
.RdEmpty (u1_empty ),
.RdData (u1_q )
);
assign u1_data = {rx_axis_mac_tuser,rx_axis_mac_tlast,rx_axis_mac_tdata};
assign u1_wrreq = (rx_axis_mac_tvalid == 1'b1) && (rx_axis_mac_tready == 1'b1);
assign u1_rdreq = (u1_empty == 1'b0) && ((tx_axis_mac_tvalid == 1'b0) || (tx_axis_mac_tready == 1'b1));
/*----------------------- Tx Clock Region ----------------------------*/
always @(posedge tx_axis_clk or negedge tx_axis_rstn)
begin
if(tx_axis_rstn == 1'b0)
tx_axis_mac_tvalid <= 1'b0;
else if(u1_rdreq == 1'b1)
tx_axis_mac_tvalid <= 1'b1;
else if(tx_axis_mac_tready == 1'b1)
tx_axis_mac_tvalid <= 1'b0;
end
always @(posedge tx_axis_clk or negedge tx_axis_rstn)
begin
if(tx_axis_rstn == 1'b0)
tx_axis_mac_tdata <= 8'h0;
else if(u1_rdreq == 1'b1)
tx_axis_mac_tdata <= u1_q[7:0];
else if(tx_axis_mac_tready == 1'b1)
tx_axis_mac_tdata <= 8'h0;
end
always @(posedge tx_axis_clk or negedge tx_axis_rstn)
begin
if(tx_axis_rstn == 1'b0)
tx_axis_mac_tlast <= 1'b0;
else if(u1_rdreq == 1'b1)
tx_axis_mac_tlast <= u1_q[8];
else if(tx_axis_mac_tready == 1'b1)
tx_axis_mac_tlast <= 1'b0;
end
always @(posedge tx_axis_clk or negedge tx_axis_rstn)
begin
if(tx_axis_rstn == 1'b0)
tx_axis_mac_tuser <= 1'b0;
else if((u1_rdreq == 1'b1) && (u1_q[8] == 1'b1))
tx_axis_mac_tuser <= u1_q[9];
else if(tx_axis_mac_tready == 1'b1)
tx_axis_mac_tuser <= 1'b0;
end
endmodule

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onerror {quit -f}
vlib work
vlog -sv -timescale 1ns/1ps +define+SIM+SIM_MODE+EFX_SIM -sv ./temac_ex.v ./apb3_2_axi4_lite.v ./axi4_st_mux.v ./mac_pat_gen.v ./mac_rx2tx.v ./reg_apb3.v ./udp_pat_gen.v ./tb_header.v ./tb_top.v ./ODDR.v ./glbl.v ./DaulClkFifo.v ./modelsim/gTSE.sv
vsim -t ns work.tb_top -gui -voptargs="+acc"
log -r /*
run -all

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/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module reg_apb3#(
parameter ADDR_WTH = 10
)
(
//Globle Signals
//
//APB3 Slave Interface
input s_apb3_clk,
input s_apb3_rstn,
input [ADDR_WTH-1:0] s_apb3_paddr,
input s_apb3_psel,
input s_apb3_penable,
output reg s_apb3_pready,
input s_apb3_pwrite,//0:rd; 1:wr;
input [31:0] s_apb3_pwdata,
output reg [31:0] s_apb3_prdata,
output wire s_apb3_pslverror,
//Cfg Space Registers
//--Example Registers Field
output reg mac_sw_rst,
output reg axi4_st_mux_select,
output reg pat_mux_select,
output reg udp_pat_gen_en,
output reg mac_pat_gen_en,
output reg [15:0] pat_gen_num,
output reg [15:0] pat_gen_ipg,
output reg [47:0] pat_dst_mac,
output reg [47:0] pat_src_mac,
output reg [15:0] pat_mac_dlen,
output reg [31:0] pat_src_ip,
output reg [31:0] pat_dst_ip,
output reg [15:0] pat_src_port,
output reg [15:0] pat_dst_port,
output reg [15:0] pat_udp_dlen,
output reg [1:0] clkmux_sel
);
// Parameter Define
// Register Define
reg [ADDR_WTH-3:0] loc_addr;
reg loc_wr_vld;
reg loc_rd_vld;
// Wire Define
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
//apb3 interface
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
loc_addr <= {ADDR_WTH-2{1'b0}};
else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0))
loc_addr <= s_apb3_paddr[2+:ADDR_WTH-2];
end
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
loc_wr_vld <= 1'b0;
else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1))
loc_wr_vld <= 1'b1;
else
loc_wr_vld <= 1'b0;
end
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
loc_rd_vld <= 1'b0;
else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0))
loc_rd_vld <= 1'b1;
else
loc_rd_vld <= 1'b0;
end
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
s_apb3_pready <= 1'b0;
else if((loc_wr_vld == 1'b1) || (loc_rd_vld == 1'b1))
s_apb3_pready <= 1'b1;
else
s_apb3_pready <= 1'b0;
end
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
s_apb3_prdata <= 32'h0;
else if(loc_rd_vld == 1'b1)
begin
case(loc_addr)
//Example Registers Field
'h080 : s_apb3_prdata <= {31'h0,mac_sw_rst};
'h081 : s_apb3_prdata <= {30'h0,pat_mux_select,axi4_st_mux_select};
'h082 : s_apb3_prdata <= {30'h0,mac_pat_gen_en,udp_pat_gen_en};
'h083 : s_apb3_prdata <= {pat_gen_ipg,pat_gen_num};
'h084 : s_apb3_prdata <= pat_dst_mac[31:0];
'h085 : s_apb3_prdata <= {16'h0,pat_dst_mac[47:32]};
'h086 : s_apb3_prdata <= pat_src_mac[31:0];
'h087 : s_apb3_prdata <= {16'h0,pat_src_mac[47:32]};
'h088 : s_apb3_prdata <= {16'h0,pat_mac_dlen};
'h089 : s_apb3_prdata <= pat_src_ip;
'h08a : s_apb3_prdata <= pat_dst_ip;
'h08b : s_apb3_prdata <= {pat_dst_port,pat_src_port};
'h08c : s_apb3_prdata <= {16'h0,pat_udp_dlen};
'h08d : s_apb3_prdata <= {30'h0,clkmux_sel};
endcase
end
end
assign s_apb3_pslverror = 1'b0;
/*----------------------------------------------------------------------------------*\
Register Space -- Example Registers Field
\*----------------------------------------------------------------------------------*/
//loc_addr = 0x080; axi_addr = 0x200; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
mac_sw_rst <= 1'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h080))
begin
mac_sw_rst <= s_apb3_pwdata[0];
end
end
//loc_addr = 0x081; axi_addr = 0x204; RW;
//[axi4_st_mux_select] 0:pat tx mode; 1:rx2tx loopback mode;
//[pat_mux_select] 0:udp pat; 1:mac pat;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
axi4_st_mux_select <= 1'h0;
pat_mux_select <= 1'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h081))
begin
axi4_st_mux_select <= s_apb3_pwdata[0];
pat_mux_select <= s_apb3_pwdata[1];
end
end
//loc_addr = 0x082; axi_addr = 0x208; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
udp_pat_gen_en <= 1'h0;
mac_pat_gen_en <= 1'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h082))
begin
udp_pat_gen_en <= s_apb3_pwdata[0];
mac_pat_gen_en <= s_apb3_pwdata[1];
end
end
//loc_addr = 0x083; axi_addr = 0x20c; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_gen_num <= 16'h0;
pat_gen_ipg <= 16'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h083))
begin
pat_gen_num <= s_apb3_pwdata[15:0];
pat_gen_ipg <= s_apb3_pwdata[31:16];
end
end
//loc_addr = 0x084; axi_addr = 0x210; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_dst_mac[31:0] <= 32'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h084))
begin
pat_dst_mac[31:0] <= s_apb3_pwdata[31:0];
end
end
//loc_addr = 0x085; axi_addr = 0x214; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_dst_mac[47:32] <= 16'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h085))
begin
pat_dst_mac[47:32] <= s_apb3_pwdata[15:0];
end
end
//loc_addr = 0x086; axi_addr = 0x218; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_src_mac[31:0] <= 32'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h086))
begin
pat_src_mac[31:0] <= s_apb3_pwdata[31:0];
end
end
//loc_addr = 0x087; axi_addr = 0x21c; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_src_mac[47:32] <= 16'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h087))
begin
pat_src_mac[47:32] <= s_apb3_pwdata[15:0];
end
end
//loc_addr = 0x088; axi_addr = 0x220; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_mac_dlen <= 16'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h088))
begin
pat_mac_dlen <= s_apb3_pwdata[15:0];
end
end
//loc_addr = 0x089; axi_addr = 0x224; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_src_ip <= 32'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h089))
begin
pat_src_ip <= s_apb3_pwdata[31:0];
end
end
//loc_addr = 0x08a; axi_addr = 0x228; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_dst_ip <= 32'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08a))
begin
pat_dst_ip <= s_apb3_pwdata[31:0];
end
end
//loc_addr = 0x08b; axi_addr = 0x22c; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_src_port <= 16'h0;
pat_dst_port <= 16'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08b))
begin
pat_src_port <= s_apb3_pwdata[15:0];
pat_dst_port <= s_apb3_pwdata[31:16];
end
end
//loc_addr = 0x08c; axi_addr = 0x230; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
pat_udp_dlen <= 16'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08c))
begin
pat_udp_dlen <= s_apb3_pwdata[15:0];
end
end
//loc_addr = 0x08d; axi_addr = 0x234; RW;
always @(posedge s_apb3_clk or negedge s_apb3_rstn)
begin
if(s_apb3_rstn == 1'b0)
begin
clkmux_sel <= 2'h0;
end
else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08d))
begin
clkmux_sel <= s_apb3_pwdata[1:0];
end
end
/*----------------------------------------------------------------------------------*\
Register Space -- The End
\*----------------------------------------------------------------------------------*/
endmodule

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fpga/ip/gTSE/Testbench/rgmii_2_rmii.v Normal file
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/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module rgmii_2_rmii (
input clk_50m, //50Mhz refclock
input rst_n,
//conduit
input [2:0] eth_speed,
//rgmii interface
input [3:0] rgmii_txd,
input rgmii_tx_ctl,
output wire [3:0] rgmii_rxd,
output wire rgmii_rx_ctl,
output reg rgmii_rxc,
//rmii interface
output wire rmii_clk,
output reg [1:0] rmii_txd,
output reg rmii_txen,
input [1:0] rmii_rxd,
input rmii_crsdv
);
wire [3:0] rxd_c;
wire rx_ctl_c;
reg [3:0] rxd_r;
reg rx_ctl_r;
reg rmii_crsdv_r, shift_en;
reg [4:0] txd_cnt, rxd_cnt;
reg [3:0] rxd_shiftreg;
reg [1:0] shift2;
reg [19:0] shift20;
reg [1:0] rx_ctl_p2;
reg [19:0] rx_ctl_p20;
assign rmii_clk = ~clk_50m; //create 180deg phaseshift
/*--------------- TX path ---------------------*/
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
txd_cnt <= 5'd0;
end
else if (rgmii_tx_ctl) begin
if (((eth_speed == 3'h2) && txd_cnt == 5'd1) ||
((eth_speed == 3'h1) && txd_cnt == 5'd19)) begin
txd_cnt <= 5'd0;
end
else begin
txd_cnt <= txd_cnt + 5'd1;
end
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rmii_txen <= 1'b0;
end
else begin
rmii_txen <= rgmii_tx_ctl;
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rmii_txd <= 2'b00;
end
else begin
if ((eth_speed == 3'h2) && txd_cnt == 5'd0) begin
rmii_txd <= rgmii_txd[1:0];
end
else if ((eth_speed == 3'h2) && txd_cnt == 5'd1) begin
rmii_txd <= rgmii_txd[3:2];
end
if ((eth_speed == 3'h1) && txd_cnt == 5'd0) begin
rmii_txd <= rgmii_txd[1:0];
end
else if ((eth_speed == 3'h1) && txd_cnt == 5'd10) begin
rmii_txd <= rgmii_txd[3:2];
end
end
end
/*------------------ end of TX path ------------------------*/
/*------------ RX path ------------------*/
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rxd_cnt <= 5'd0;
end
else if (rmii_crsdv) begin
if (((eth_speed == 3'h2) && rxd_cnt == 5'd1) || ((eth_speed == 3'h1) && rxd_cnt == 5'd19)) begin
rxd_cnt <= 5'd0;
end
else begin
rxd_cnt <= rxd_cnt + 5'd1;
end
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rxd_shiftreg <= 4'd0;
end
else if (rmii_crsdv) begin
if (eth_speed == 3'h2 || ((eth_speed == 3'h1) && (rxd_cnt == 5'd0 || rxd_cnt == 5'd10))) begin
rxd_shiftreg <= {rmii_rxd, rxd_shiftreg[3:2]};
end
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
shift2 <= 2'b1;
shift20 <= 20'b1;
end
else begin
shift2 <= {shift2[0],shift2[1]};
shift20 <= {shift20[18:0],shift20[19]};
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rgmii_rxc <= 1'b0;
end
else begin
if ((eth_speed == 3'h2 && shift2[1]) || (eth_speed == 3'h1 && (shift20[10]))) begin
rgmii_rxc <= 1'b1;
end
else if ((eth_speed == 3'h2 && shift2[0]) || (eth_speed == 3'h1 && (shift20[0]))) begin
rgmii_rxc <= 1'b0;
end
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rx_ctl_p2 <= 2'd0;
rx_ctl_p20 <= 20'd0;
end
else begin
rx_ctl_p2 <= {rmii_crsdv , rx_ctl_p2[1]};
rx_ctl_p20 <= {rmii_crsdv, rx_ctl_p20[19:1]};
end
end
/*---- shift rxd & rx_ctl so that they are not edge align with rgmii_rxc ----*/
assign rxd_c = (rxd_cnt == 5'd0) ? rxd_shiftreg : rxd_r;
assign rx_ctl_c = (eth_speed == 3'h2) ? rx_ctl_p2[0] : rx_ctl_p20[0];
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
rxd_r <= 4'd0;
rx_ctl_r <= 1'd0;
rmii_crsdv_r <= 1'd0;
end
else begin
rxd_r <= rxd_c;
rx_ctl_r <= rx_ctl_c;
rmii_crsdv_r <= rmii_crsdv;
end
end
always @(posedge clk_50m or negedge rst_n)
begin
if (!rst_n) begin
shift_en <= 1'd0;
end // to detect if rmii_crsdv assert at the posedge of rgmii_rxc, delay rgmii_rxd & rgmii_rx_ctl if they are aligned with rgmii_rxc
else if (rmii_crsdv && ~rmii_crsdv_r) begin
if (((eth_speed == 3'h2) && shift2[0]) || ((eth_speed == 3'h1) && shift20[11])) begin
shift_en <= 1'd1;
end
else begin
shift_en <= 1'd0;
end
end
end
assign rgmii_rxd = shift_en ? rxd_r : rxd_c;
assign rgmii_rx_ctl = shift_en ? rx_ctl_r : rx_ctl_c;
/*--------------------------------------------------------*/
/*------------------ end of RX path ------------------------*/
endmodule

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fpga/ip/gTSE/Testbench/tb_header.v Normal file
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`define SIM_MODE

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/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns/100ps
`define SIM_MODE
`define RXFIFO_EN 1
`define RXFIFO_DTH 2048
`define TXFIFO_EN 1
`define TXFIFO_DTH 2048
module tb_top(
);
`include "gTSE_define.svh"
// Parameter Define
parameter TSET_CASE = 1;//Values range from "1" to "9"
parameter MAC_SPEED = 2;//4:1000M; 2:100M; 1:10M;
parameter PAT_TYPE = 1;//0:UDP Pattern; 1:MAC Pattern;
parameter DST_MAC_H = 16'habcd;
parameter DST_MAC_L = 32'hef22_1100;
parameter SRC_MAC_H = 16'heae8;
parameter SRC_MAC_L = 32'h5e00_60c8;
parameter MAC_DLEN = 16'd64;
parameter SRC_IP = 32'hc0a80164;
parameter DST_IP = 32'hc0a80165;
parameter SRC_PORT = 16'h0521;
parameter DST_PORT = 16'h2715;
parameter UDP_DLEN = 16'h64;
// Register Define
reg Reset;
reg clk_50m=0;
reg clk_125m=0;
reg clk_25m=0;
reg clk_2m5=0;
reg err_ins=0;
//--mac_reg command_config
reg tx_ena=0;
reg rx_ena=0;
reg xon_gen=0;
reg promis_en=0;
reg pad_en=0;
reg crc_fwd=0;
reg pause_ignore=0;
reg tx_addr_ins=0;
reg sw_reset=0;
reg loop_ena=0;
reg [2:0] eth_speed=0;
reg xoff_gen=0;
reg cnt_reset=0;
//--APB3 Interface
reg [9:0] m_apb3_paddr=0;
reg m_apb3_psel=0;
reg m_apb3_penable=0;
reg m_apb3_pwrite=0;
reg [31:0] m_apb3_pwdata=0;
// Wire Define
wire [31:0] mac_command_config;
//--Transmit AXI4-Stream Interface
wire tx_axis_clk;
wire [7:0] tx_axis_mac_tdata;
wire tx_axis_mac_tvalid;
wire tx_axis_mac_tlast;
wire tx_axis_mac_tuser;
wire tx_axis_mac_tready;
//--APB3 Interface
wire m_apb3_pready;
wire [31:0] m_apb3_prdata;
wire m_apb3_pslverror;
//--AXI4-Lite Interface
wire [9:0] axi_awaddr;
wire axi_awvalid;
wire axi_awready;
wire [31:0] axi_wdata;
wire axi_wvalid;
wire axi_wready;
wire [1:0] axi_bresp;
wire axi_bvalid;
wire axi_bready;
wire [9:0] axi_araddr;
wire axi_arvalid;
wire axi_arready;
wire [1:0] axi_rresp;
wire [31:0] axi_rdata;
wire axi_rvalid;
wire axi_rready;
//--RGMII Interface
wire [3:0] rgmii_txd_HI;
wire [3:0] rgmii_txd_LO;
wire rgmii_tx_ctl;
wire rgmii_txc_HI;
wire rgmii_txc_LO;
wire rgmii_txc;
wire [3:0] rgmii_rxd_HI;
wire [3:0] rgmii_rxd_LO;
wire rgmii_rx_ctl;
wire rgmii_rxc;
wire rx_data_rlast;
wire udp_rx_data_rlast;
wire rx_data_ruser;
integer i;
//-----------------------------------------------------------------------------------//
// THE Sim Behavior
//-----------------------------------------------------------------------------------//
initial
begin
//$shm_open("test.shm");
//$shm_probe(tb_top,"ACMTF");
Reset <=1;
#20
Reset <=0;
init_task();
if(TSET_CASE == 1)
test_case_1_task();
else if(TSET_CASE == 2)
test_case_2_task();
else if(TSET_CASE == 3)
test_case_3_task();
else if(TSET_CASE == 4)
test_case_4_task();
else if(TSET_CASE == 5)
test_case_5_task();
else if(TSET_CASE == 6)
test_case_6_task();
else if(TSET_CASE == 7)
test_case_7_task();
else if(TSET_CASE == 8)
test_case_8_task();
else if(TSET_CASE == 9)
test_case_9_task();
#5000
$display("TEST PASSED");
$finish(1);
end
//-----------------------------------------------------------------------------------//
// THE Clock Generate
//-----------------------------------------------------------------------------------//
always clk_50m = #(10) ~clk_50m;
always clk_2m5 = #(200) ~clk_2m5;
always clk_25m = #(20) ~clk_25m;
always clk_125m = #(4) ~clk_125m;
//-----------------------------------------------------------------------------------//
// THE Sim Condition
//-----------------------------------------------------------------------------------//
assign u_temac_ex.apb3_paddr = m_apb3_paddr;
assign u_temac_ex.apb3_psel = m_apb3_psel;
assign u_temac_ex.apb3_penable = m_apb3_penable;
assign m_apb3_pready = u_temac_ex.apb3_pready;
assign u_temac_ex.apb3_pwrite = m_apb3_pwrite;
assign u_temac_ex.apb3_pwdata = m_apb3_pwdata;
assign m_apb3_prdata = u_temac_ex.apb3_prdata;
assign m_apb3_pslverror = u_temac_ex.apb3_pslverror;
assign rx_data_rlast = u_temac_ex.u_mac_pat_gen.rlast;
assign rx_data_ruser = u_temac_ex.rx_axis_mac_tlast;
assign udp_rx_data_rlast = u_temac_ex.u_udp_pat_gen.rlast;
assign mac_command_config = {cnt_reset,7'h0,
1'h0,xoff_gen,3'h0,eth_speed[2:0],
loop_ena,1'h0,sw_reset,3'h0,tx_addr_ins,pause_ignore,
1'h0,crc_fwd,pad_en,promis_en,1'h0,xon_gen,rx_ena,tx_ena};
assign rgmii_rxd_HI = (err_ins) ? 4'h0 : rgmii_txd_LO;
assign rgmii_rxd_LO = (err_ins) ? 4'h0 : rgmii_txd_HI;
assign rgmii_rx_ctl = rgmii_tx_ctl;
assign rgmii_rxc = rgmii_txc;
reg [7:0] rx_data_cnt;
reg rdata_mismatch;
always @(posedge clk_125m or negedge Reset)
begin
if(Reset == 1'b0)
rx_data_cnt <= 8'h0;
else if(u_temac_ex.rx_axis_mac_tlast)
rx_data_cnt <= 8'h0;
else if(u_temac_ex.rx_axis_mac_tvalid)
rx_data_cnt <= rx_data_cnt + 1'b1;
end
always @(posedge clk_125m or negedge Reset)
begin
if(Reset == 1'b0)
rdata_mismatch <= 1'b0;
else if (u_temac_ex.rx_axis_mac_tlast)
rdata_mismatch <= 1'b0;
else if(u_temac_ex.rx_axis_mac_tvalid && rx_data_cnt >= 8'd42) begin
if ((rx_data_cnt - u_temac_ex.rx_axis_mac_tdata) != 8'd42)
rdata_mismatch <= 1'b1;
end
end
//-----------------------------------------------------------------------------------//
// THE DUT RX
//-----------------------------------------------------------------------------------//
temac_ex u_temac_ex
(
//Globle Signals
//----pll_0
//output wire pll_0_reset,
.clk (clk_50m ),
.clk_125m (clk_125m ),
.pll_0_locked (!Reset ),
.sw6 (),
//TEMAC PHY RGMII Interface
.rgmii_txd_HI (rgmii_txd_HI ),
.rgmii_txd_LO (rgmii_txd_LO ),
.rgmii_tx_ctl (rgmii_tx_ctl ),
.rgmii_txc_HI (rgmii_txc_HI ),
.rgmii_txc_LO (rgmii_txc_LO ),
.rgmii_rxd_HI (rgmii_rxd_HI ),
.rgmii_rxd_LO (rgmii_rxd_LO ),
.rgmii_rx_ctl (rgmii_rx_ctl ),
.rgmii_rxc (rgmii_rxc ),
//TEMAC PHY MDIO Interface
.phy_mdi (1'b0 ),
.phy_mdo ( ),
.phy_mdo_en ( ),
.phy_mdc ( )
);
/*----------------------- ODDR Region ----------------------------*/
//rgmii_txc
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE" )// "OPPOSITE_EDGE" or "SAME_EDGE"
) rgmii_txc_ddr (
.Q (rgmii_txc ),// 1-bit DDR output
.C (clk_125m ),// 1-bit clock input
.CE (1'b1 ),// 1-bit clock enable input
.D1 (rgmii_txc_HI ),// 1-bit data input (positive edge)
.D2 (rgmii_txc_LO ),// 1-bit data input (negative edge)
.R (1'b0 ),// 1-bit reset
.S (1'b0 )// 1-bit set
);
//-----------------------------------------------------------------------------------//
// THE Base Task
//-----------------------------------------------------------------------------------//
//apb3 bus wr task
task apb3_wr;
input [9:0] awaddr;
input [31:0] wdata;
begin
@(posedge clk_50m);
m_apb3_paddr <= awaddr;
m_apb3_pwrite <= 1'b1;
m_apb3_psel <= 1'b1;
m_apb3_pwdata <= wdata;
@(posedge clk_50m);
m_apb3_penable <= 1;
wait(m_apb3_pready);
@(posedge clk_50m);
m_apb3_paddr <= 0;
m_apb3_pwrite <= 0;
m_apb3_psel <= 0;
m_apb3_pwdata <= 1'b0;
m_apb3_penable <= 0;
@(posedge clk_50m);
end
endtask
//apb3 bus rd task
task apb3_rd;
input [9:0] araddr;
begin
@(posedge clk_50m);
m_apb3_paddr <= araddr;
m_apb3_pwrite <= 1'b0;
m_apb3_psel <= 1'b1;
@(posedge clk_50m);
m_apb3_penable <= 1;
wait(m_apb3_pready);
@(posedge clk_50m);
m_apb3_paddr <= 0;
m_apb3_pwrite <= 0;
m_apb3_psel <= 0;
m_apb3_penable <= 0;
@(posedge clk_50m);
end
endtask
//initial task
task init_task;
begin
//initial mac_reg
tx_ena <= 1'h1;
rx_ena <= 1'h1;
xon_gen <= 1'h0;
promis_en <= 1'h0;
pad_en <= 1'h0;
crc_fwd <= 1'h0;
pause_ignore <= 1'h0;
tx_addr_ins <= 1'h0;
sw_reset <= 1'h0;
loop_ena <= 1'h0;
eth_speed[2:0] <= MAC_SPEED;
xoff_gen <= 1'h0;
cnt_reset <= 1'h0;
@(posedge clk_50m);
$display("---- Configure TSE MAC IP register setting ----");
apb3_wr('h2*4,mac_command_config);//mac_reg command_config
//initial ex_reg
apb3_wr('h84*4,DST_MAC_L);//ex_reg pat_dst_mac[31:0]
apb3_wr('h85*4,DST_MAC_H);//ex_reg pat_dst_mac[47:32]
apb3_wr('h86*4,SRC_MAC_L);//ex_reg pat_src_mac[31:0]
apb3_wr('h87*4,SRC_MAC_H);//ex_reg pat_src_mac[47:32]
apb3_wr('h89*4,SRC_IP);//ex_reg pat_src_ip
apb3_wr('h8a*4,DST_IP);//ex_reg pat_dst_ip
apb3_wr('h8b*4,{DST_PORT,SRC_PORT});//ex_reg pat_dst_port & pat_src_port
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h81*4,32'h0);//ex_reg pat_mux_select & axi4_st_mux_select
end
else
begin
apb3_wr('h81*4,32'h2);//ex_reg pat_mux_select & axi4_st_mux_select
end
end
endtask
//pause frame generator task
task pause_gen_task;
input [15:0] pause_quant;
begin
apb3_wr('h6*4,pause_quant);//mac_reg pause_quant
xoff_gen <= 1'h1;
@(posedge clk_50m);
apb3_wr('h2*4,mac_command_config);//mac_reg command_config
wait(u_temac_ex.u_tsemac.u_efx_mac1gbe.inst_tsemac.u_tsemac.u_tx_engine.u_tx_ctr.cur_state == 4'd4);
xoff_gen <= 1'h0;
@(posedge clk_50m);
apb3_wr('h2*4,mac_command_config);//mac_reg command_config
end
endtask
task check_rdata_task;
input integer i;
input [1:0] check_error_bit;
begin
while (rx_data_rlast == 0) @(posedge clk_125m);
if (check_error_bit == 2'b01) begin
apb3_rd('h22*4); // read ifInErrors
if (|m_apb3_prdata == 0) begin
$display("%t - Error: Expecting MAC packet ifInErrors to go high, ifInErrors = %h", $time, m_apb3_prdata);
$fatal("FAIL: simulation fail");
end
else begin
$display("%t - Correct MAC packet %d, received", $time, i);
end
end
else if (check_error_bit == 2'b10) begin
if (rx_data_ruser == 0) begin
$display("%t - Error: Expecting MAC packet rx_data_ruser to go high, rx_data_ruser = %h", $time, rx_data_ruser);
$fatal("FAIL: simulation fail");
end
else begin
$display("%t - MAC packet %d is filtered", $time, i);
end
end
else begin
apb3_rd('h22*4); // read ifInErrors
if (rdata_mismatch != 0) begin
$display("%t - Error: Received data mismatch", $time);
$fatal("FAIL: simulation fail");
end
if (|m_apb3_prdata != 0) begin
$display("%t - Error: There is an Error in the MAC received packet, ifInErrors = %h", $time, m_apb3_prdata);
$fatal("FAIL: simulation fail");
end
else begin
$display("%t - Correct MAC packet %d, received", $time, i);
end
end
end
endtask
task check_udp_rdata_task;
input integer i;
input [1:0] check_error_bit;
begin
while (rx_data_rlast == 0) @(posedge clk_125m);
if (check_error_bit == 2'b01) begin
apb3_rd('h22*4); // read ifInErrors
if (|m_apb3_prdata == 0) begin
$display("%t - Error: Expecting UDP packet ifInErrors to go high, ifInErrors = %h", $time, m_apb3_prdata);
$fatal("FAIL: simulation fail");
end
else begin
$display("%t - Correct UDP packet %d, received", $time, i);
end
end
else if (check_error_bit == 2'b10) begin
if (rx_data_ruser == 0) begin
$display("%t - Error: Expecting UDP packet rx_data_ruser to go high, rx_data_ruser = %h", $time, rx_data_ruser);
$fatal("FAIL: simulation fail");
end
else begin
$display("%t - UDP packet %d is filtered", $time, i);
end
end
else begin
apb3_rd('h22*4); // read ifInErrors
if (rdata_mismatch != 0) begin
$display("%t - Error: Received data mismatch", $time);
$fatal("FAIL: simulation fail");
end
if (|m_apb3_prdata != 0) begin
$display("%t - Error: There is an Error in the UDP received packet, ifInErrors = %h", $time, m_apb3_prdata);
$fatal("FAIL: simulation fail");
end
else begin
$display("%t - Correct UDP packet %d, received", $time, i);
end
end
end
endtask
//-----------------------------------------------------------------------------------//
// THE Test Case Task
//-----------------------------------------------------------------------------------//
task test_case_1_task;
begin
apb3_wr('h81*4,32'h2);//ex_reg pat_mux_select & axi4_st_mux_select
apb3_wr('h88*4,MAC_DLEN);//ex_reg pat_mac_dlen
apb3_wr('h83*4,{16'h10,16'h3E8});//ex_reg pat_gen_ipg & pat_gen_num
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
for (i=0; i<16'h3E8; i = i + 1) begin
check_rdata_task(i, 2'b00);
end
end
endtask
task test_case_2_task;
begin
apb3_wr('h81*4,32'h0);//ex_reg pat_mux_select & axi4_st_mux_select
apb3_wr('h8c*4,UDP_DLEN);//ex_reg pat_udp_dlen
apb3_wr('h83*4,{16'hff,16'h3E8});//ex_reg pat_gen_ipg & pat_gen_num
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
for (i=0; i<16'h3E8; i = i + 1) begin
check_udp_rdata_task(i, 2'b00);
end
end
endtask
task test_case_3_task;
begin
begin // to transmit tx packet after rx pause frame finished processed
apb3_wr('h88*4,16'd100);//ex_reg pat_mac_dlen
apb3_wr('h8c*4,16'd100);//ex_reg pat_udp_dlen
apb3_wr('h83*4,{16'hf,16'h2});//ex_reg pat_gen_ipg & pat_gen_num
//Send 2 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_udp_rdata_task(0, 2'b00);
check_udp_rdata_task(1, 2'b00);
end
else
begin
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_rdata_task(0, 2'b00);
check_rdata_task(1, 2'b00);
end
//send 1 pause frames
pause_gen_task(16'd8);
while (rx_data_rlast == 0) @(posedge clk_125m);
#1000 // to have some buffer to make sure the core process rx pause frame entirely
//Send 2 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_udp_rdata_task(2, 2'b00);
check_udp_rdata_task(3, 2'b00);
end
else
begin
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_rdata_task(2, 2'b00);
check_rdata_task(3, 2'b00);
end
end
begin
//Send 2 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_udp_rdata_task(4, 2'b00);
check_udp_rdata_task(5, 2'b00);
end
else
begin
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_rdata_task(4, 2'b00);
check_rdata_task(5, 2'b00);
end
//send 1 pause frames
pause_gen_task(16'd8);
//Send 2 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
// check to make sure entire pause frame is received
while (rx_data_rlast == 0) @(posedge clk_125m);
repeat(1) @(posedge clk_125m);
check_udp_rdata_task(6, 2'b00);
check_udp_rdata_task(7, 2'b00);
end
else
begin
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
// check to make sure entire pause frame is received
while (rx_data_rlast == 0) @(posedge clk_125m);
repeat(1) @(posedge clk_125m);
check_rdata_task(8, 2'b00);
check_rdata_task(9, 2'b00);
end
end
end
endtask
task test_case_4_task;
begin
apb3_wr('h83*4,{16'hf,16'h1});//ex_reg pat_gen_ipg & pat_gen_num
//Send 1 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h5*4,16'd9000+46);//mac_reg frm_length
apb3_wr('h8c*4,16'd9000);//ex_reg pat_udp_dlen
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_udp_rdata_task(0, 2'b00);
end
else
begin
apb3_wr('h5*4,16'd9000+18);//mac_reg frm_length
apb3_wr('h88*4,16'd9000);//ex_reg pat_mac_dlen
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_rdata_task(0, 2'b00);
end
//Send 1 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h8c*4,16'd9001);//ex_reg pat_udp_dlen
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_udp_rdata_task(1, 2'b01);
end
else
begin
apb3_wr('h88*4,16'd9001);//ex_reg pat_mac_dlen
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_rdata_task(1, 2'b01);
end
end
endtask
task test_case_5_task;
begin
apb3_wr('h83*4,{16'hf,16'd20});//ex_reg pat_gen_ipg & pat_gen_num
for (i=0; i<20; i = i + 1) begin
apb3_wr('h88*4,i);//ex_reg pat_mac_dlen
apb3_wr('h8c*4,i);//ex_reg pat_udp_dlen
//Send 1 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_udp_rdata_task(i, 2'b00);
end
else
begin
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_rdata_task(i, 2'b00);
end
end
end
endtask
task test_case_6_task;
begin
apb3_wr('h88*4,16'd64);//ex_reg pat_mac_dlen
apb3_wr('h8c*4,16'd64);//ex_reg pat_udp_dlen
apb3_wr('h83*4,{16'hf,16'h1});//ex_reg pat_gen_ipg & pat_gen_num
//Send 1 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_udp_rdata_task(0, 2'b00);
end
else
begin
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_rdata_task(0, 2'b00);
end
//Send 1 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_udp_rdata_task(1, 2'b00);
end
else
begin
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_rdata_task(1, 2'b00);
end
//Send 1 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h8c*4,16'd200);//ex_reg pat_udp_dlen
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
$display("%t Wait for rgmii_rx_ctl to go high", $time);
wait(u_temac_ex.u_tsemac.u_efx_mac1gbe.inst_tsemac.rgmii_rx_ctl_HI == 1);
repeat(20) @(posedge rgmii_rxc);
err_ins <= 1'b1;
$display("%t - insert error", $time);
repeat(4) @(posedge rgmii_rxc);
err_ins <= 1'b0;
$display("%t - deassert error", $time);
check_udp_rdata_task(2, 2'b01);
end
else
begin
apb3_wr('h88*4,16'd200);//ex_reg pat_mac_dlen
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
$display("%t Wait for rgmii_rx_ctl to go high", $time);
wait(u_temac_ex.u_tsemac.u_efx_mac1gbe.inst_tsemac.rgmii_rx_ctl_HI == 1);
repeat(20) @(posedge rgmii_rxc);
err_ins <= 1'b1;
$display("%t - insert error", $time);
repeat(4) @(posedge rgmii_rxc);
err_ins <= 1'b0;
$display("%t - deassert error", $time);
check_rdata_task(2, 2'b01);
end
end
endtask
task test_case_7_task;
begin
apb3_wr('h88*4,16'd64);//ex_reg pat_mac_dlen
apb3_wr('h8c*4,16'd64);//ex_reg pat_udp_dlen
apb3_wr('h83*4,{16'hf,16'h1});//ex_reg pat_gen_ipg & pat_gen_num
//Send 1 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_udp_rdata_task(0, 2'b00);
end
else
begin
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_rdata_task(0, 2'b00);
end
apb3_wr('h51*4,32'hffffffff);//mac_reg mac_addr_mask[31:0]
apb3_wr('h52*4,16'hffff);//mac_reg mac_addr_mask[47:32]
//Send 1 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_udp_rdata_task(1, 2'b10);
end
else
begin
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_rdata_task(1, 2'b10);
end
apb3_wr('h84*4,32'hffffffff);//ex_reg pat_dst_mac[31:0]
apb3_wr('h85*4,16'hffff);//ex_reg pat_dst_mac[47:32]
//Send 1 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_udp_rdata_task(2, 2'b01);
end
else
begin
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_rdata_task(2, 2'b01);
end
apb3_wr('h50*4,32'h1);//mac_reg broadcast_filter_en
//Send 1 mac frames
if(PAT_TYPE == 1'b0)
begin
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_udp_rdata_task(3, 2'b10);
end
else
begin
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
check_rdata_task(3, 2'b10);
end
end
endtask
task test_case_8_task; // small packet length & small inter-gap
begin
apb3_wr('h81*4,32'h2);//ex_reg pat_mux_select & axi4_st_mux_select
apb3_wr('h88*4,MAC_DLEN);//ex_reg pat_mac_dlen
apb3_wr('h83*4,{16'd12,16'd100});//ex_reg pat_gen_ipg & pat_gen_num
apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
for (i=0; i<16'd100; i = i + 1) begin
check_rdata_task(i, 2'b00);
end
end
endtask
task test_case_9_task; // small packet length & small inter-gap
begin
apb3_wr('h81*4,32'h0);//ex_reg pat_mux_select & axi4_st_mux_select
apb3_wr('h8c*4,UDP_DLEN);//ex_reg pat_udp_dlen
apb3_wr('h83*4,{16'd12,16'd100});//ex_reg pat_gen_ipg & pat_gen_num
apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en
apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en
for (i=0; i<16'd100; i = i + 1) begin
check_udp_rdata_task(i, 2'b00);
end
end
endtask
endmodule

563
fpga/ip/gTSE/Testbench/temac_ex.v Normal file
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/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
//`include "header.v" // use JTAG hard block
module temac_ex
(
//Globle Signals
//----pll_0
input clk,
input clk_125m,
input pll_0_locked,
input sw6,
output wire pll_rstn,
//TEMAC PHY RGMII Interface
output wire [3:0] rgmii_txd_HI,
output wire [3:0] rgmii_txd_LO,
output wire rgmii_txc_HI,
output wire rgmii_txc_LO,
input [3:0] rgmii_rxd_HI,
input [3:0] rgmii_rxd_LO,
`ifdef TITANIUM
output wire rgmii_tx_ctl_HI,
output wire rgmii_tx_ctl_LO,
input rgmii_rx_ctl_HI,
input rgmii_rx_ctl_LO,
input mux_clk,
output [1:0] mux_clk_sw,
`else
input rgmii_rxc,
output wire rgmii_tx_ctl,
input rgmii_rx_ctl,
`endif
//TEMAC PHY Ctr Interface
output wire phy_rstn,
//hardware Jtag Interface
`ifndef SIM_MODE
`ifndef SOFT_TAP
input jtag_inst1_TCK,
input jtag_inst1_TDI,
output wire jtag_inst1_TDO,
input jtag_inst1_SEL,
input jtag_inst1_CAPTURE,
input jtag_inst1_SHIFT,
input jtag_inst1_UPDATE,
input jtag_inst1_RESET,
`else
//software Jtag Interface
input io_jtag_tms,
input io_jtag_tdi,
output wire io_jtag_tdo,
input io_jtag_tck,
`endif
//Debug Signals
//output wire [1:0] debug_led
output wire system_uart_0_io_txd,
input system_uart_0_io_rxd,
`endif
output system_spi_0_io_sclk_write,
output system_spi_0_io_data_0_writeEnable,
input system_spi_0_io_data_0_read,
output system_spi_0_io_data_0_write,
output system_spi_0_io_data_1_writeEnable,
input system_spi_0_io_data_1_read,
output system_spi_0_io_data_1_write,
output system_spi_0_io_ss,
//TEMAC PHY MDIO Interface
input phy_mdi,
output wire phy_mdo,
output wire phy_mdo_en,
output wire phy_mdc
);
// Parameter Define
`include "gTSE_define.svh"
// Register Define
// Wire Define
wire clk_50m;
wire clk_50m_rstn;
wire mac_reset;
wire proto_reset;
wire mac_rstn;
//AXI4-Stream Interface
wire rx_axis_clk;
wire [7:0] rx_axis_mac_tdata;
wire rx_axis_mac_tvalid;
wire rx_axis_mac_tlast;
wire rx_axis_mac_tuser;
wire rx_axis_mac_tready;
wire tx_axis_clk;
wire [7:0] tx_axis_mac_tdata;
wire tx_axis_mac_tvalid;
wire tx_axis_mac_tlast;
wire tx_axis_mac_tuser;
wire tx_axis_mac_tready;
wire [7:0] udp_tx_axis_mac_tdata;
wire udp_tx_axis_mac_tvalid;
wire udp_tx_axis_mac_tlast;
wire udp_tx_axis_mac_tready;
wire [7:0] mac_tx_axis_mac_tdata;
wire mac_tx_axis_mac_tvalid;
wire mac_tx_axis_mac_tlast;
wire mac_tx_axis_mac_tready;
wire [7:0] pat_tx_axis_mac_tdata;
wire pat_tx_axis_mac_tvalid;
wire pat_tx_axis_mac_tlast;
wire pat_tx_axis_mac_tuser;
wire pat_tx_axis_mac_tready;
wire [7:0] loop_tx_axis_mac_tdata;
wire loop_tx_axis_mac_tvalid;
wire loop_tx_axis_mac_tlast;
wire loop_tx_axis_mac_tuser;
wire loop_tx_axis_mac_tready;
//RiscV APB3 Interface
wire [15:0] apb3_paddr;
wire apb3_psel;
wire apb3_penable;
wire apb3_pready;
wire apb3_pwrite;
wire [31:0] apb3_pwdata;
wire [31:0] apb3_prdata;
wire apb3_pslverror;
//Mac APB3 Interface
wire [9:0] mac_apb3_paddr;
wire mac_apb3_psel;
wire mac_apb3_penable;
wire mac_apb3_pready;
wire mac_apb3_pwrite;
wire [31:0] mac_apb3_pwdata;
wire [31:0] mac_apb3_prdata;
wire mac_apb3_pslverror;
//Ex APB3 Interface
wire [9:0] ex_apb3_paddr;
wire ex_apb3_psel;
wire ex_apb3_penable;
wire ex_apb3_pready;
wire ex_apb3_pwrite;
wire [31:0] ex_apb3_pwdata;
wire [31:0] ex_apb3_prdata;
wire ex_apb3_pslverror;
//AXI4-Lite Interface
wire [9:0] axi_awaddr;
wire axi_awvalid;
wire axi_awready;
wire [31:0] axi_wdata;
wire axi_wvalid;
wire axi_wready;
wire [1:0] axi_bresp;
wire axi_bvalid;
wire axi_bready;
wire [9:0] axi_araddr;
wire axi_arvalid;
wire axi_arready;
wire [1:0] axi_rresp;
wire [31:0] axi_rdata;
wire axi_rvalid;
wire axi_rready;
//Cfg Space Registers
wire mac_sw_rst;
wire axi4_st_mux_select;
wire pat_mux_select;
wire udp_pat_gen_en;
wire mac_pat_gen_en;
wire [15:0] pat_gen_num;
wire [15:0] pat_gen_ipg;
wire [47:0] pat_dst_mac;
wire [47:0] pat_src_mac;
wire [15:0] pat_mac_dlen;
wire [31:0] pat_src_ip;
wire [31:0] pat_dst_ip;
wire [15:0] pat_src_port;
wire [15:0] pat_dst_port;
wire [15:0] pat_udp_dlen;
//TSE DDIO
`ifdef TITANIUM
wire rgmii_rxc;
assign rgmii_rxc = mux_clk;
`else
wire rgmii_rx_ctl_LO;
wire rgmii_rx_ctl_HI;
wire rgmii_tx_ctl_LO;
wire rgmii_tx_ctl_HI;
assign rgmii_tx_ctl = rgmii_tx_ctl_HI | rgmii_tx_ctl_LO ;
assign rgmii_rx_ctl_HI = rgmii_rx_ctl ;
assign rgmii_rx_ctl_LO = rgmii_rx_ctl ;
`endif
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
assign pll_rstn = 1;
/*----------------------- Clock Region -----------------------*/
//In full throughput usecase, rx_axis_clk and tx_axis_clk should be set to 125Mhz or above.
//In this example design, these clocks are set to 50Mhz because the UDP/MAC pattern generator has
//high combi logic and couldn't meet timing at 125Mhz.
assign rx_axis_clk = clk;//clk_125m;
assign tx_axis_clk = clk;//clk_125m;
/*----------------------- Reset Region -----------------------*/
//assign pll_0_reset = 1'b0;
assign clk_50m = clk;
assign phy_rstn = sw6;
assign clk_50m_rstn = pll_0_locked;
assign mac_reset = ~pll_0_locked;
assign proto_reset = mac_sw_rst;
assign mac_rstn = ~(mac_reset || proto_reset);
/*----------------------- MCU Module ----------------------------*/
`ifndef SIM_MODE
sapphire u_mcu
(
//user custom ports
//SOC
.io_systemClk (clk_50m ),
.io_asyncReset (1'b0 ),
.system_uart_0_io_txd (system_uart_0_io_txd ),
.system_uart_0_io_rxd (system_uart_0_io_rxd ),
.system_spi_0_io_sclk_write (system_spi_0_io_sclk_write ),
.system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable ),
.system_spi_0_io_data_0_read (system_spi_0_io_data_0_read ),
.system_spi_0_io_data_0_write (system_spi_0_io_data_0_write ),
.system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable ),
.system_spi_0_io_data_1_read (system_spi_0_io_data_1_read ),
.system_spi_0_io_data_1_write (system_spi_0_io_data_1_write ),
.system_spi_0_io_ss (system_spi_0_io_ss ),
.jtagCtrl_tck (jtag_inst1_TCK ),
.jtagCtrl_tdi (jtag_inst1_TDI ),
.jtagCtrl_tdo (jtag_inst1_TDO ),
.jtagCtrl_enable (jtag_inst1_SEL ),
.jtagCtrl_capture (jtag_inst1_CAPTURE ),
.jtagCtrl_shift (jtag_inst1_SHIFT ),
.jtagCtrl_update (jtag_inst1_UPDATE ),
.jtagCtrl_reset (jtag_inst1_RESET ),
//APB3 Master Interface
.io_apbSlave_0_PADDR (apb3_paddr ),
.io_apbSlave_0_PSEL (apb3_psel ),
.io_apbSlave_0_PENABLE (apb3_penable ),
.io_apbSlave_0_PREADY (apb3_pready ),
.io_apbSlave_0_PWRITE (apb3_pwrite ),
.io_apbSlave_0_PWDATA (apb3_pwdata ),
.io_apbSlave_0_PRDATA (apb3_prdata ),
.io_apbSlave_0_PSLVERROR (apb3_pslverror )
);
`endif
assign apb3_pready = (apb3_paddr[9] == 1'b0) ? mac_apb3_pready : ex_apb3_pready;
assign apb3_prdata = (apb3_paddr[9] == 1'b0) ? mac_apb3_prdata : ex_apb3_prdata;
assign apb3_pslverror = (apb3_paddr[9] == 1'b0) ? mac_apb3_pslverror : ex_apb3_pslverror;
assign mac_apb3_paddr = apb3_paddr[9:0];
assign mac_apb3_psel = (apb3_paddr[9] == 1'b0) ? apb3_psel : 1'b0;
assign mac_apb3_penable = apb3_penable;
assign mac_apb3_pwrite = apb3_pwrite;
assign mac_apb3_pwdata = apb3_pwdata;
assign ex_apb3_paddr = apb3_paddr[9:0];
assign ex_apb3_psel = (apb3_paddr[9] == 1'b1) ? apb3_psel : 1'b0;
assign ex_apb3_penable = apb3_penable;
assign ex_apb3_pwrite = apb3_pwrite;
assign ex_apb3_pwdata = apb3_pwdata;
apb3_2_axi4_lite#(
.ADDR_WTH (10 )
)
u_apb3_2_axi4_lite
(
//Globle Signals
.clk (clk_50m ),
.rstn (clk_50m_rstn ),
//APB3 Slave Interface
.s_apb3_paddr (mac_apb3_paddr ),
.s_apb3_psel (mac_apb3_psel ),
.s_apb3_penable (mac_apb3_penable ),
.s_apb3_pready (mac_apb3_pready ),
.s_apb3_pwrite (mac_apb3_pwrite ),
.s_apb3_pwdata (mac_apb3_pwdata ),
.s_apb3_prdata (mac_apb3_prdata ),
.s_apb3_pslverror (mac_apb3_pslverror ),
//AXI4-Lite Master Interface
.m_axi_awaddr (axi_awaddr ),
.m_axi_awvalid (axi_awvalid ),
.m_axi_awready (axi_awready ),
.m_axi_wdata (axi_wdata ),
.m_axi_wvalid (axi_wvalid ),
.m_axi_wready (axi_wready ),
.m_axi_bresp (axi_bresp ),
.m_axi_bvalid (axi_bvalid ),
.m_axi_bready (axi_bready ),
.m_axi_araddr (axi_araddr ),
.m_axi_arvalid (axi_arvalid ),
.m_axi_arready (axi_arready ),
.m_axi_rresp (axi_rresp ),
.m_axi_rdata (axi_rdata ),
.m_axi_rvalid (axi_rvalid ),
.m_axi_rready (axi_rready )
);
reg_apb3#(
.ADDR_WTH (10 )
)
u_reg_apb3
(
//Globle Signals
//
//APB3 Slave Interface
.s_apb3_clk (clk_50m ),
.s_apb3_rstn (clk_50m_rstn ),
.s_apb3_paddr (ex_apb3_paddr ),
.s_apb3_psel (ex_apb3_psel ),
.s_apb3_penable (ex_apb3_penable ),
.s_apb3_pready (ex_apb3_pready ),
.s_apb3_pwrite (ex_apb3_pwrite ),
.s_apb3_pwdata (ex_apb3_pwdata ),
.s_apb3_prdata (ex_apb3_prdata ),
.s_apb3_pslverror (ex_apb3_pslverror ),
//Cfg Space Registers
//--Example Registers Field
.mac_sw_rst (mac_sw_rst ),
.axi4_st_mux_select (axi4_st_mux_select ),
.pat_mux_select (pat_mux_select ),
.udp_pat_gen_en (udp_pat_gen_en ),
.mac_pat_gen_en (mac_pat_gen_en ),
.pat_gen_num (pat_gen_num ),
.pat_gen_ipg (pat_gen_ipg ),
.pat_dst_mac (pat_dst_mac ),
.pat_src_mac (pat_src_mac ),
.pat_mac_dlen (pat_mac_dlen ),
.pat_src_ip (pat_src_ip ),
.pat_dst_ip (pat_dst_ip ),
.pat_src_port (pat_src_port ),
.pat_dst_port (pat_dst_port ),
.pat_udp_dlen (pat_udp_dlen ),
.clkmux_sel (mux_clk_sw )
);
//generate if (PATTERN_TYPE == 0) begin //UDP
//
//assign mac_tx_axis_mac_tdata = 8'h0;
//assign mac_tx_axis_mac_tvalid = 1'b0;
//assign mac_tx_axis_mac_tlast = 1'b0;
/*----------------------- The Ethernet Pattern Module -----------------------*/
udp_pat_gen u_udp_pat_gen
(
//Globle Signals
.clk (tx_axis_clk ),
.rstn (mac_rstn ),
//Control Interface
.pat_gen_en (udp_pat_gen_en ),
.pat_gen_num (pat_gen_num ),
.pat_gen_ipg (pat_gen_ipg ),
//MAC Protocol Signals
.dst_mac (pat_dst_mac ),
.src_mac (pat_src_mac ),
//IP Protocol Signals
.src_ip (pat_src_ip ),
.dst_ip (pat_dst_ip ),
//UDP Protocol Signals
.src_port (pat_src_port ),
.dst_port (pat_dst_port ),
.udp_dlen (pat_udp_dlen ),
//AXI4-Stream Interface
.rclk (rx_axis_clk ),
.rrstn (mac_rstn ),
.rdata (rx_axis_mac_tdata ),
.rvalid (rx_axis_mac_tvalid ),
.rlast (rx_axis_mac_tlast ),
.tdata (udp_tx_axis_mac_tdata ),
.tvalid (udp_tx_axis_mac_tvalid ),
.tlast (udp_tx_axis_mac_tlast ),
.tready (udp_tx_axis_mac_tready )
);
//end
//else begin //MAC
//
//assign udp_tx_axis_mac_tdata = 8'h0;
//assign udp_tx_axis_mac_tvalid = 1'b0;
//assign udp_tx_axis_mac_tlast = 1'b0;
mac_pat_gen u_mac_pat_gen
(
//Globle Signals
.clk (tx_axis_clk ),
.rstn (mac_rstn ),
//Control Interface
.pat_gen_en (mac_pat_gen_en ),
.pat_gen_num (pat_gen_num ),
.pat_gen_ipg (pat_gen_ipg ),
//MAC Protocol Signals
.dst_mac (pat_dst_mac ),
.src_mac (pat_src_mac ),
.mac_dlen (pat_mac_dlen ),
//AXI4-Stream Interface
.rclk (rx_axis_clk ),
.rrstn (mac_rstn ),
.rdata (rx_axis_mac_tdata ),
.rvalid (rx_axis_mac_tvalid ),
.rlast (rx_axis_mac_tlast ),
.tdata (mac_tx_axis_mac_tdata ),
.tvalid (mac_tx_axis_mac_tvalid ),
.tlast (mac_tx_axis_mac_tlast ),
.tready (mac_tx_axis_mac_tready )
);
//end
//endgenerate
axi4_st_mux u_pat_mux
(
//Globle Signals
.mux_select (pat_mux_select ),//0:udp pat; 1:mac pat;
//Mux In 0 Interface
.tdata0 (udp_tx_axis_mac_tdata ),
.tvalid0 (udp_tx_axis_mac_tvalid ),
.tlast0 (udp_tx_axis_mac_tlast ),
.tuser0 (1'b0 ),
.tready0 (udp_tx_axis_mac_tready ),
//Mux In 1 Interface
.tdata1 (mac_tx_axis_mac_tdata ),
.tvalid1 (mac_tx_axis_mac_tvalid ),
.tlast1 (mac_tx_axis_mac_tlast ),
.tuser1 (1'b0 ),
.tready1 (mac_tx_axis_mac_tready ),
//Mux Out Interface
.tdata (pat_tx_axis_mac_tdata ),
.tvalid (pat_tx_axis_mac_tvalid ),
.tlast (pat_tx_axis_mac_tlast ),
.tuser (pat_tx_axis_mac_tuser ),
.tready (pat_tx_axis_mac_tready )
);
/*----------------------- The Tx AXI4 St Mux Module -----------------------*/
axi4_st_mux u_tx_axi4st_mux
(
//Globle Signals
.mux_select (axi4_st_mux_select ),//0:pat; 1:rx2tx loopback;
//Mux In 0 Interface
.tdata0 (pat_tx_axis_mac_tdata ),
.tvalid0 (pat_tx_axis_mac_tvalid ),
.tlast0 (pat_tx_axis_mac_tlast ),
.tuser0 (pat_tx_axis_mac_tuser ),
.tready0 (pat_tx_axis_mac_tready ),
//Mux In 1 Interface
.tdata1 (loop_tx_axis_mac_tdata ),
.tvalid1 (loop_tx_axis_mac_tvalid ),
.tlast1 (loop_tx_axis_mac_tlast ),
.tuser1 (loop_tx_axis_mac_tuser ),
.tready1 (loop_tx_axis_mac_tready ),
//Mux Out Interface
.tdata (tx_axis_mac_tdata ),
.tvalid (tx_axis_mac_tvalid ),
.tlast (tx_axis_mac_tlast ),
.tuser (tx_axis_mac_tuser ),
.tready (tx_axis_mac_tready )
);
/*----------------------- The Tri-mode Ethernet MAC core -----------------------*/
gTSE u_tsemac
(
//Globle Signals
.mac_reset (mac_reset ),
.proto_reset (proto_reset ),
.tx_mac_aclk (clk_125m ),
.rx_mac_aclk ( ),
.eth_speed ( ),
//Receive AXI4-Stream Interface
.rx_axis_clk (rx_axis_clk ),
.rx_axis_mac_tdata (rx_axis_mac_tdata ),
.rx_axis_mac_tvalid (rx_axis_mac_tvalid ),
.rx_axis_mac_tlast (rx_axis_mac_tlast ),
.rx_axis_mac_tstrb (),
.rx_axis_mac_tuser (rx_axis_mac_tuser ),
.rx_axis_mac_tready (rx_axis_mac_tready ),
//Transmit AXI4-Stream Interface
.tx_axis_clk (tx_axis_clk ),
.tx_axis_mac_tdata (tx_axis_mac_tdata ),
.tx_axis_mac_tvalid (tx_axis_mac_tvalid ),
.tx_axis_mac_tlast (tx_axis_mac_tlast ),
.tx_axis_mac_tstrb (1'b1 ),
.tx_axis_mac_tuser (tx_axis_mac_tuser ),
.tx_axis_mac_tready (tx_axis_mac_tready ),
//--RGMII Interface
.rgmii_txd_HI (rgmii_txd_HI ),
.rgmii_txd_LO (rgmii_txd_LO ),
.rgmii_tx_ctl_HI (rgmii_tx_ctl_HI ),
.rgmii_tx_ctl_LO (rgmii_tx_ctl_LO ),
.rgmii_txc_HI (rgmii_txc_HI ),
.rgmii_txc_LO (rgmii_txc_LO ),
.rgmii_rxd_HI (rgmii_rxd_HI ),
.rgmii_rxd_LO (rgmii_rxd_LO ),
.rgmii_rx_ctl_HI (rgmii_rx_ctl_HI ),
.rgmii_rx_ctl_LO (rgmii_rx_ctl_LO ),
.rgmii_rxc (rgmii_rxc ),
//AXI4-Lite Interface
.s_axi_aclk (clk_50m ),
.s_axi_awaddr (axi_awaddr ),
.s_axi_awvalid (axi_awvalid ),
.s_axi_awready (axi_awready ),
.s_axi_wdata (axi_wdata ),
.s_axi_wvalid (axi_wvalid ),
.s_axi_wready (axi_wready ),
.s_axi_bresp (axi_bresp ),
.s_axi_bvalid (axi_bvalid ),
.s_axi_bready (axi_bready ),
.s_axi_araddr (axi_araddr ),
.s_axi_arvalid (axi_arvalid ),
.s_axi_arready (axi_arready ),
.s_axi_rresp (axi_rresp ),
.s_axi_rdata (axi_rdata ),
.s_axi_rvalid (axi_rvalid ),
.s_axi_rready (axi_rready ),
//MDIO Interface
.Mdo (phy_mdo ),
.MdoEn (phy_mdo_en ),
.Mdi (phy_mdi ),
.Mdc (phy_mdc )
);
/*----------------------- User Interface Loopback Module ----------------------------*/
mac_rx2tx u_mac_rx2tx
(
//Globle Signals
//
//Receive AXI4-Stream Interface
.rx_axis_clk (rx_axis_clk ),
.rx_axis_rstn (mac_rstn ),
.rx_axis_mac_tdata (rx_axis_mac_tdata ),
.rx_axis_mac_tvalid (rx_axis_mac_tvalid ),
.rx_axis_mac_tlast (rx_axis_mac_tlast ),
.rx_axis_mac_tuser (rx_axis_mac_tuser ),
.rx_axis_mac_tready (rx_axis_mac_tready ),
//Transmit AXI4-Stream Interface
.tx_axis_clk (tx_axis_clk ),
.tx_axis_rstn (mac_rstn ),
.tx_axis_mac_tdata (loop_tx_axis_mac_tdata ),
.tx_axis_mac_tvalid (loop_tx_axis_mac_tvalid ),
.tx_axis_mac_tlast (loop_tx_axis_mac_tlast ),
.tx_axis_mac_tuser (loop_tx_axis_mac_tuser ),
.tx_axis_mac_tready (loop_tx_axis_mac_tready )
);
endmodule

497
fpga/ip/gTSE/Testbench/udp_pat_gen.v Normal file
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/////////////////////////////////////////////////////////////////////////////
// _____
// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
// / / \
// / / .. /
// / / .' /
// __/ /.' /
// __ \ /
// /_/ /\ \_____/ /
// ____/ \_______/
//
// *******************************
// Revisions:
// 1.0 Initial rev
//
// *******************************
`timescale 1 ns / 1 ns
module udp_pat_gen
(
//Globle Signals
input clk,
input rstn,
//Control Interface
input pat_gen_en,
input [15:0] pat_gen_num,//When value is 0, it's infinite mode
input [15:0] pat_gen_ipg,
//MAC Protocol Signals
input [47:0] dst_mac,
input [47:0] src_mac,
//IP Protocol Signals
input [31:0] src_ip,
input [31:0] dst_ip,
//UDP Protocol Signals
input [15:0] udp_dlen,
input [15:0] src_port,
input [15:0] dst_port,
//AXI4-Stream Interface
input rclk,
input rrstn,
input [7:0] rdata,
input rvalid,
input rlast,
output reg [7:0] tdata,
output reg tvalid,
output reg tlast,
input tready
);
// Parameter Define
localparam VER = 4'h4;//IPv4
localparam IHL = 4'h5;//Internet Header Length
localparam TOS = 8'h0;//Type Of Service
localparam FLG = 3'h0;//Flags
localparam TTL = 8'h40;//Time To Live
localparam PTC = 8'h11;//UDP Protocol
localparam IDLE = 3'h0;
localparam UDP_CHKSUM = 3'h1;
localparam IP_CHKSUM = 3'h2;
localparam PAT_IPG = 3'h3;
localparam PAT_GEN = 3'h4;
// Register Define
reg [2:0] cur_state;
reg [2:0] next_state;
reg pat_gen_en_dl1;
reg pat_gen_en_dl2;
reg [31:0] src_ip_r;
reg [31:0] dst_ip_r;
reg [15:0] src_port_r;
reg [15:0] dst_port_r;
reg pat_en;
reg infinite_en;
reg [15:0] num_cnt;
reg [15:0] udp_chksum_cnt;
reg [3:0] ip_chksum_cnt;
reg [15:0] ipg_cnt;
reg [15:0] pat_cnt;
reg [15:0] udp_len;
reg [15:0] udp_chksum_num;
reg [7:0] udp_data_h;
reg [7:0] udp_data_l;
reg [16:0] udp_chksum_r;
reg [15:0] udp_chksum;
reg [15:0] ip_len;
reg [15:0] ip_id;
reg [12:0] ip_ofs;
reg [16:0] ip_chksum_r;
reg [15:0] ip_chksum;
reg [15:0] pat_gen_num_r;
reg [15:0] pat_gen_ipg_r;
reg [47:0] dst_mac_r;
reg [47:0] src_mac_r;
reg [15:0] udp_dlen_r;
// Wire Define
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0) begin
pat_gen_num_r <= 16'h0;
pat_gen_ipg_r <= 16'h0;
dst_mac_r <= 48'h0;
src_mac_r <= 48'h0;
udp_dlen_r <= 16'h0;
end
else begin
pat_gen_num_r <= pat_gen_num;
pat_gen_ipg_r <= pat_gen_ipg;
dst_mac_r <= dst_mac;
src_mac_r <= src_mac;
udp_dlen_r <= udp_dlen;
end
end
/*----------------------- FSM Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
cur_state <= IDLE;
else
cur_state <= next_state;
end
always @(*)
begin
case(cur_state)
IDLE :
if(pat_en == 1'b1)
next_state = UDP_CHKSUM;
else
next_state = IDLE;
UDP_CHKSUM :
if(udp_chksum_cnt == udp_chksum_num)
next_state = IP_CHKSUM;
else
next_state = UDP_CHKSUM;
IP_CHKSUM :
if(ip_chksum_cnt == 4'd9)
next_state = PAT_GEN;
else
next_state = IP_CHKSUM;
PAT_IPG :
if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0)))
next_state = IDLE;
else if(ipg_cnt == pat_gen_ipg_r)
next_state = IP_CHKSUM;
else
next_state = PAT_IPG;
PAT_GEN :
if((tlast == 1'b1) && (tready == 1'b1))
next_state = PAT_IPG;
else
next_state = PAT_GEN;
default :
next_state = IDLE;
endcase
end
/*----------------------- Generator Control Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
begin
pat_gen_en_dl1 <= 1'h0;
pat_gen_en_dl2 <= 1'h0;
end
else
begin
pat_gen_en_dl1 <= pat_gen_en;
pat_gen_en_dl2 <= pat_gen_en_dl1;
end
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
begin
src_ip_r <= 32'h0;
dst_ip_r <= 32'h0;
src_port_r <= 16'h0;
dst_port_r <= 16'h0;
end
else
begin
src_ip_r <= src_ip;
dst_ip_r <= dst_ip;
src_port_r <= src_port;
dst_port_r <= dst_port;
end
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
pat_en <= 1'h0;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
pat_en <= 1'h1;
else if((cur_state == IDLE) && (pat_en == 1'b1))
pat_en <= 1'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
infinite_en <= 1'h0;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0))
infinite_en <= 1'h1;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
infinite_en <= 1'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
num_cnt <= 16'h0;
else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
num_cnt <= pat_gen_num_r;
else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0))
num_cnt <= num_cnt - 1'b1;
end
/*----------------------- UDP Protocol Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
udp_len <= 16'h0;
else
udp_len <= udp_dlen_r + 16'd8;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
udp_chksum_num <= 16'h0;
else if(udp_dlen_r[0] == 1'b1)
udp_chksum_num <= udp_dlen_r[15:1] + 16'd10;
else
udp_chksum_num <= udp_dlen_r[15:1] + 16'd9;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
begin
udp_data_h <= 8'h0;
udp_data_l <= 8'h0;
end
else if(cur_state == IDLE)
begin
udp_data_h <= 8'h0;
udp_data_l <= 8'h1;
end
else if((cur_state == UDP_CHKSUM) && (udp_chksum_cnt >= 16'h9))
begin
udp_data_h <= udp_data_h + 8'h2;
udp_data_l <= udp_data_l + 8'h2;
end
end
//udp checksum calculate
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
udp_chksum_r <= 17'h0;
else if(cur_state == IDLE)
udp_chksum_r <= 17'h0;
else if(cur_state == UDP_CHKSUM) begin
if (udp_chksum_cnt <= 16'd8) begin
case(udp_chksum_cnt[3:0])
4'd0 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[31:16] + udp_chksum_r[16];
4'd1 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[15:0] + udp_chksum_r[16];
4'd2 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[31:16] + udp_chksum_r[16];
4'd3 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[15:0] + udp_chksum_r[16];
4'd4 : udp_chksum_r <= udp_chksum_r[15:0] + 16'h11 + udp_chksum_r[16];
4'd5 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16];
4'd6 : udp_chksum_r <= udp_chksum_r[15:0] + src_port_r + udp_chksum_r[16];
4'd7 : udp_chksum_r <= udp_chksum_r[15:0] + dst_port_r + udp_chksum_r[16];
4'd8 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16];
default : udp_chksum_r <= 17'h0;
endcase
end
else begin
if(udp_chksum_cnt == udp_chksum_num)
udp_chksum_r <= udp_chksum_r[15:0] + udp_chksum_r[16];
else if((udp_chksum_cnt == udp_chksum_num-1) && (udp_dlen_r[0] == 1'b1))
udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,8'h0} + udp_chksum_r[16];
else
udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,udp_data_l} + udp_chksum_r[16];
end
end
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
udp_chksum <= 16'h0;
else
udp_chksum <= ~udp_chksum_r[15:0];
end
/*----------------------- IP Protocol Region ----------------------------*/
//IP Frame Total Length
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_len <= 16'h0;
else
ip_len <= udp_len + 16'd20;
end
//IP Frame Identification
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_id <= 16'h0;
else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1))
ip_id <= ip_id + 1'b1;
end
//IP Frame Fragment Offset
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_chksum <= 16'h0;
else
ip_chksum <= ~ip_chksum_r[15:0];
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_ofs <= 13'h0;
end
//ip checksum calculate
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_chksum_r <= 16'h0;
else if(cur_state == IDLE)
ip_chksum_r <= 16'h0;
else if(cur_state == IP_CHKSUM) begin
case(ip_chksum_cnt)
4'd0 : ip_chksum_r <= ip_chksum_r[15:0] + {VER,IHL,TOS} + ip_chksum_r[16];
4'd1 : ip_chksum_r <= ip_chksum_r[15:0] + ip_len + ip_chksum_r[16];
4'd2 : ip_chksum_r <= ip_chksum_r[15:0] + ip_id + ip_chksum_r[16];
4'd3 : ip_chksum_r <= ip_chksum_r[15:0] + {FLG,ip_ofs} + ip_chksum_r[16];
4'd4 : ip_chksum_r <= ip_chksum_r[15:0] + {TTL,PTC} + ip_chksum_r[16];
4'd5 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[31:16] + ip_chksum_r[16];
4'd6 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[15:0] + ip_chksum_r[16];
4'd7 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[31:16] + ip_chksum_r[16];
4'd8 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[15:0] + ip_chksum_r[16];
4'd9 : ip_chksum_r <= ip_chksum_r[15:0] + ip_chksum_r[16];
endcase
end
else if(cur_state == PAT_IPG)
ip_chksum_r <= 16'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_chksum <= 16'h0;
else
ip_chksum <= ~ip_chksum_r[15:0];
end
/*----------------------- Pattern Counter Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
udp_chksum_cnt <= 16'h0;
else if(cur_state == UDP_CHKSUM)
udp_chksum_cnt <= udp_chksum_cnt + 1'b1;
else
udp_chksum_cnt <= 16'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ip_chksum_cnt <= 4'h0;
else if(cur_state == IP_CHKSUM)
ip_chksum_cnt <= ip_chksum_cnt + 1'b1;
else
ip_chksum_cnt <= 4'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
ipg_cnt <= 16'h0;
else if(cur_state == PAT_IPG)
ipg_cnt <= ipg_cnt + 1'b1;
else
ipg_cnt <= 8'h0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
pat_cnt <= 16'h0;
else if(cur_state != PAT_GEN)
pat_cnt <= 16'h0;
else if(tready == 1'b1)
pat_cnt <= pat_cnt + 1'b1;
end
/*----------------------- Pattern Generator Region ----------------------------*/
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
tvalid <= 1'b0;
else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1))
tvalid <= 1'b1;
else if((tready == 1'b1) && (tlast == 1'b1))
tvalid <= 1'b0;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
tdata <= 8'h0;
else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd42))
case(pat_cnt[5:0])
6'd0 : tdata <= dst_mac_r[5*8 +: 8];
6'd1 : tdata <= dst_mac_r[4*8 +: 8];
6'd2 : tdata <= dst_mac_r[3*8 +: 8];
6'd3 : tdata <= dst_mac_r[2*8 +: 8];
6'd4 : tdata <= dst_mac_r[1*8 +: 8];
6'd5 : tdata <= dst_mac_r[0*8 +: 8];
6'd6 : tdata <= src_mac_r[5*8 +: 8];
6'd7 : tdata <= src_mac_r[4*8 +: 8];
6'd8 : tdata <= src_mac_r[3*8 +: 8];
6'd9 : tdata <= src_mac_r[2*8 +: 8];
6'd10 : tdata <= src_mac_r[1*8 +: 8];
6'd11 : tdata <= src_mac_r[0*8 +: 8];
6'd12 : tdata <= 8'h08;
6'd13 : tdata <= 8'h00;
6'd14 : tdata <= {VER,IHL};
6'd15 : tdata <= TOS;
6'd16 : tdata <= ip_len[15:8];
6'd17 : tdata <= ip_len[7:0];
6'd18 : tdata <= ip_id[15:8];
6'd19 : tdata <= ip_id[7:0];
6'd20 : tdata <= {FLG,ip_ofs[12:8]};
6'd21 : tdata <= ip_ofs[7:0];
6'd22 : tdata <= TTL;
6'd23 : tdata <= PTC;
6'd24 : tdata <= ip_chksum[15:8];
6'd25 : tdata <= ip_chksum[7:0];
6'd26 : tdata <= src_ip_r[3*8 +: 8];
6'd27 : tdata <= src_ip_r[2*8 +: 8];
6'd28 : tdata <= src_ip_r[1*8 +: 8];
6'd29 : tdata <= src_ip_r[0*8 +: 8];
6'd30 : tdata <= dst_ip_r[3*8 +: 8];
6'd31 : tdata <= dst_ip_r[2*8 +: 8];
6'd32 : tdata <= dst_ip_r[1*8 +: 8];
6'd33 : tdata <= dst_ip_r[0*8 +: 8];
6'd34 : tdata <= src_port_r[15:8];
6'd35 : tdata <= src_port_r[7:0];
6'd36 : tdata <= dst_port_r[15:8];
6'd37 : tdata <= dst_port_r[7:0];
6'd38 : tdata <= udp_len[15:8];
6'd39 : tdata <= udp_len[7:0];
6'd40 : tdata <= udp_chksum[15:8];
6'd41 : tdata <= udp_chksum[7:0];
6'd42 : tdata <= 8'h0;//UDP First Data
default : tdata <= tdata + 1'b1;
endcase
else if((cur_state == PAT_GEN) && (tready == 1'b1))
tdata <= tdata + 1'b1;
end
always @(posedge clk or negedge rstn)
begin
if(rstn == 1'b0)
tlast <= 1'b0;
else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == ip_len+16'd13))
tlast <= 1'b1;
else if(tready == 1'b1)
tlast <= 1'b0;
end
endmodule