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fpga/ip/gTSE/gTSE_tmpl.vhd
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fpga/ip/gTSE/gTSE_tmpl.vhd
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--------------------------------------------------------------------------------
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-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
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--
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-- This document contains proprietary information which is
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-- protected by copyright. All rights are reserved. This notice
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-- refers to original work by Efinix, Inc. which may be derivitive
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-- of other work distributed under license of the authors. In the
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-- case of derivative work, nothing in this notice overrides the
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-- original author's license agreement. Where applicable, the
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-- original license agreement is included in it's original
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-- unmodified form immediately below this header.
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--
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-- WARRANTY DISCLAIMER.
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-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
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-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
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-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
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-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
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-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
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-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
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--
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-- LIMITATION OF LIABILITY.
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-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
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-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
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-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
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-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
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-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
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-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
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-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
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-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
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-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
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-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
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-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
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-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
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-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
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-- APPLY TO LICENSEE.
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--
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--------------------------------------------------------------------------------
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------------- Begin Cut here for COMPONENT Declaration ------
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component gTSE is
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port (
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mac_reset : in std_logic;
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proto_reset : in std_logic;
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rx_mac_aclk : out std_logic;
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tx_mac_aclk : in std_logic;
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eth_speed : out std_logic_vector(2 downto 0);
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rx_axis_clk : in std_logic;
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rx_axis_mac_tuser : out std_logic;
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rx_axis_mac_tlast : out std_logic;
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rx_axis_mac_tvalid : out std_logic;
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rx_axis_mac_tready : in std_logic;
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tx_axis_clk : in std_logic;
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tx_axis_mac_tvalid : in std_logic;
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tx_axis_mac_tlast : in std_logic;
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tx_axis_mac_tuser : in std_logic;
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tx_axis_mac_tready : out std_logic;
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rgmii_txd_HI : out std_logic_vector(3 downto 0);
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rgmii_txd_LO : out std_logic_vector(3 downto 0);
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rgmii_tx_ctl_HI : out std_logic;
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rgmii_tx_ctl_LO : out std_logic;
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rgmii_txc_HI : out std_logic;
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rgmii_txc_LO : out std_logic;
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rgmii_rxd_HI : in std_logic_vector(3 downto 0);
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rgmii_rxd_LO : in std_logic_vector(3 downto 0);
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rgmii_rx_ctl_HI : in std_logic;
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rgmii_rx_ctl_LO : in std_logic;
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rgmii_rxc : in std_logic;
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s_axi_aclk : in std_logic;
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rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
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tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
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tx_axis_mac_tstrb : in std_logic_vector(0 to 0);
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rx_axis_mac_tstrb : out std_logic_vector(0 to 0);
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MdoEn : out std_logic;
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Mdo : out std_logic;
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Mdi : in std_logic;
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Mdc : out std_logic;
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s_axi_araddr : in std_logic_vector(9 downto 0);
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s_axi_arready : out std_logic;
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s_axi_arvalid : in std_logic;
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s_axi_awaddr : in std_logic_vector(9 downto 0);
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s_axi_awready : out std_logic;
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s_axi_awvalid : in std_logic;
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s_axi_bready : in std_logic;
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s_axi_bresp : out std_logic_vector(1 downto 0);
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s_axi_bvalid : out std_logic;
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s_axi_rdata : out std_logic_vector(31 downto 0);
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s_axi_rready : in std_logic;
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s_axi_rresp : out std_logic_vector(1 downto 0);
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s_axi_rvalid : out std_logic;
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s_axi_wdata : in std_logic_vector(31 downto 0);
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s_axi_wready : out std_logic;
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s_axi_wvalid : in std_logic
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);
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end component gTSE;
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---------------------- End COMPONENT Declaration ------------
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------------- Begin Cut here for INSTANTIATION Template -----
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u_gTSE : gTSE
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port map (
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mac_reset => mac_reset,
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proto_reset => proto_reset,
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rx_mac_aclk => rx_mac_aclk,
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tx_mac_aclk => tx_mac_aclk,
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eth_speed => eth_speed,
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rx_axis_clk => rx_axis_clk,
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rx_axis_mac_tuser => rx_axis_mac_tuser,
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rx_axis_mac_tlast => rx_axis_mac_tlast,
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rx_axis_mac_tvalid => rx_axis_mac_tvalid,
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rx_axis_mac_tready => rx_axis_mac_tready,
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tx_axis_clk => tx_axis_clk,
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tx_axis_mac_tvalid => tx_axis_mac_tvalid,
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tx_axis_mac_tlast => tx_axis_mac_tlast,
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tx_axis_mac_tuser => tx_axis_mac_tuser,
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tx_axis_mac_tready => tx_axis_mac_tready,
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rgmii_txd_HI => rgmii_txd_HI,
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rgmii_txd_LO => rgmii_txd_LO,
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rgmii_tx_ctl_HI => rgmii_tx_ctl_HI,
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rgmii_tx_ctl_LO => rgmii_tx_ctl_LO,
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rgmii_txc_HI => rgmii_txc_HI,
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rgmii_txc_LO => rgmii_txc_LO,
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rgmii_rxd_HI => rgmii_rxd_HI,
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rgmii_rxd_LO => rgmii_rxd_LO,
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rgmii_rx_ctl_HI => rgmii_rx_ctl_HI,
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rgmii_rx_ctl_LO => rgmii_rx_ctl_LO,
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rgmii_rxc => rgmii_rxc,
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s_axi_aclk => s_axi_aclk,
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rx_axis_mac_tdata => rx_axis_mac_tdata,
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tx_axis_mac_tdata => tx_axis_mac_tdata,
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tx_axis_mac_tstrb => tx_axis_mac_tstrb,
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rx_axis_mac_tstrb => rx_axis_mac_tstrb,
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MdoEn => MdoEn,
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Mdo => Mdo,
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Mdi => Mdi,
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Mdc => Mdc,
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s_axi_araddr => s_axi_araddr,
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s_axi_arready => s_axi_arready,
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s_axi_arvalid => s_axi_arvalid,
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s_axi_awaddr => s_axi_awaddr,
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s_axi_awready => s_axi_awready,
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s_axi_awvalid => s_axi_awvalid,
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s_axi_bready => s_axi_bready,
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s_axi_bresp => s_axi_bresp,
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s_axi_bvalid => s_axi_bvalid,
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s_axi_rdata => s_axi_rdata,
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s_axi_rready => s_axi_rready,
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s_axi_rresp => s_axi_rresp,
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s_axi_rvalid => s_axi_rvalid,
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s_axi_wdata => s_axi_wdata,
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s_axi_wready => s_axi_wready,
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s_axi_wvalid => s_axi_wvalid
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);
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------------------------ End INSTANTIATION Template ---------
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