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Byron Lathi
2026-04-14 21:34:37 -07:00
commit 50f8791588
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fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl.sv Normal file
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fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_define.svh Normal file
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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.272
// IP Version: 8.1
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam SYNC_CLK = 0;
localparam SYNC_STAGE = 2;
localparam DATA_WIDTH = 16;
localparam MODE = "FWFT";
localparam OUTPUT_REG = 0;
localparam PROG_FULL_ASSERT = 128;
localparam PROGRAMMABLE_FULL = "NONE";
localparam PROG_FULL_NEGATE = 128;
localparam PROGRAMMABLE_EMPTY = "NONE";
localparam PROG_EMPTY_ASSERT = 2;
localparam PROG_EMPTY_NEGATE = 3;
localparam OPTIONAL_FLAGS = 0;
localparam PIPELINE_REG = 1;
localparam DEPTH = 512;
localparam FAMILY = "TITANIUM";
localparam ASYM_WIDTH_RATIO = 4;
localparam BYPASS_RESET_SYNC = 0;
localparam ENDIANESS = 0;
localparam RAM_STYLE = "block_ram";
localparam OVERFLOW_PROTECT = 0;
localparam UNDERFLOW_PROTECT = 0;

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fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv Normal file
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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.272
// IP Version: 8.1
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
gTSE_core_fifo_ctrl u_gTSE_core_fifo_ctrl
(
.full_o ( full_o ),
.empty_o ( empty_o ),
.wr_clk_i ( wr_clk_i ),
.rd_clk_i ( rd_clk_i ),
.wr_en_i ( wr_en_i ),
.rd_en_i ( rd_en_i ),
.wdata ( wdata ),
.rst_busy ( rst_busy ),
.rdata ( rdata ),
.a_rst_i ( a_rst_i ),
.wr_datacount_o ( wr_datacount_o ),
.rd_datacount_o ( rd_datacount_o )
);

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fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd Normal file
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--------------------------------------------------------------------------------
-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
component gTSE_core_fifo_ctrl is
port (
full_o : out std_logic;
empty_o : out std_logic;
wr_clk_i : in std_logic;
rd_clk_i : in std_logic;
wr_en_i : in std_logic;
rd_en_i : in std_logic;
wdata : in std_logic_vector(15 downto 0);
rst_busy : out std_logic;
rdata : out std_logic_vector(15 downto 0);
a_rst_i : in std_logic;
wr_datacount_o : out std_logic_vector(9 downto 0);
rd_datacount_o : out std_logic_vector(9 downto 0)
);
end component gTSE_core_fifo_ctrl;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_gTSE_core_fifo_ctrl : gTSE_core_fifo_ctrl
port map (
full_o => full_o,
empty_o => empty_o,
wr_clk_i => wr_clk_i,
rd_clk_i => rd_clk_i,
wr_en_i => wr_en_i,
rd_en_i => rd_en_i,
wdata => wdata,
rst_busy => rst_busy,
rdata => rdata,
a_rst_i => a_rst_i,
wr_datacount_o => wr_datacount_o,
rd_datacount_o => rd_datacount_o
);
------------------------ End INSTANTIATION Template ---------

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fpga/ip/gTSE_core_fifo_ctrl/settings.json Normal file
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{
"args": [
"-o",
"gTSE_core_fifo_ctrl",
"--base_path",
"/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "memory",
"name": "efx_fifo_top",
"version": "8.1"
}
],
"conf": {
"SYNC_CLK": "0",
"SYNC_STAGE": "2",
"DEPTH_2": "9",
"DATA_WIDTH": "16",
"MODE": "\"FWFT\"",
"OUTPUT_REG": "0",
"PROG_FULL_ASSERT": "128",
"PROGRAMMABLE_FULL": "\"NONE\"",
"PFN_INTERNAL": "127",
"PEA_INTERNAL": "2",
"PEN_INTERNAL": "3",
"PROGRAMMABLE_EMPTY": "\"NONE\"",
"OPTIONAL_FLAGS": "0",
"PIPELINE_REG": "1",
"ASYM_WIDTH_RATIO": "4",
"BYPASS_RESET_SYNC": "0",
"ENDIANESS": "0",
"RAM_STYLE": "\"block_ram\"",
"OVERFLOW_PROTECT": "0",
"UNDERFLOW_PROTECT": "0"
},
"output": {
"external_source_source": [
"gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl.sv",
"gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_define.svh",
"gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv",
"gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd"
],
"external_example_example": [
"gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo.peri.xml",
"gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo.xml",
"gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo_top.v",
"gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo_T20.sdc",
"gTSE_core_fifo_ctrl/T20F256_devkit/efx_symmetric_width_fifo_top.sv",
"gTSE_core_fifo_ctrl/T20F256_devkit/gTSE_core_fifo_ctrl.sv",
"gTSE_core_fifo_ctrl/T20F256_devkit/gTSE_core_fifo_ctrl_define.svh"
],
"external_example_2": [
"gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo.peri.xml",
"gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo.xml",
"gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo_top.v",
"gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo_Ti60.sdc",
"gTSE_core_fifo_ctrl/Ti60F225_devkit/efx_symmetric_width_fifo_top.sv",
"gTSE_core_fifo_ctrl/Ti60F225_devkit/gTSE_core_fifo_ctrl.sv",
"gTSE_core_fifo_ctrl/Ti60F225_devkit/gTSE_core_fifo_ctrl_define.svh"
],
"external_testbench_testbench": [
"gTSE_core_fifo_ctrl/Testbench/fifo_tb.sv",
"gTSE_core_fifo_ctrl/Testbench/xrun.sh",
"gTSE_core_fifo_ctrl/Testbench/msim.sh",
"gTSE_core_fifo_ctrl/Testbench/flist",
"gTSE_core_fifo_ctrl/Testbench/modelsim.do",
"gTSE_core_fifo_ctrl/Testbench/gTSE_core_fifo_ctrl.sv",
"gTSE_core_fifo_ctrl/Testbench/gTSE_core_fifo_ctrl_define.svh"
]
},
"ooc_synthesis": {},
"sw_version": "2025.2.272",
"generated_date": "2025-10-16T09:35:38.547531+00:00"
}