initial commit

sim/sources.list

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+verilator.vlt
+verilog6502_wrapper_tb.sv
+
+../src/regs/verilog6502_io_regs_pkg.sv
+../src/regs/verilog6502_io_regs.sv
+
+../src/verilog6502_addr_decoder.sv
+../src/verilog6502_internal_memory.sv
+../src/verilog6502_apb_adapter.sv
+../src/verilog6502_wrapper.sv
+
+
+../sub/verilog-6502/ALU.v
+../sub/verilog-6502/cpu_65c02.v
+
+../sub/taxi/src/apb/rtl/taxi_apb_if.sv
+../sub/taxi/src/axi/rtl/taxi_axi_if.sv
+../sub/taxi/src/axi/rtl/taxi_axi_ram_if_rd.sv
+../sub/taxi/src/axi/rtl/taxi_axi_ram_if_wr.sv
+../sub/taxi/src/axi/rtl/taxi_axi_ram_if_rdwr.sv
+../sub/taxi/src/apb/rtl/taxi_apb_interconnect.sv
+../sub/taxi/src/apb/rtl/taxi_apb_tie.sv
+../sub/taxi/src/prim/rtl/taxi_arbiter.sv
+../sub/taxi/src/prim/rtl/taxi_penc.sv

sim/verilator.vlt

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+`verilator_config
+
+lint_off -file "**/ALU.v"
+lint_off -file "**/cpu_65c02.v"
+lint_off -rule MULTIDRIVEN -file "**/verilog6502_io_regs.sv"
+lint_off -rule UNOPTFLAT
+lint_off -rule TIMESCALEMOD

sim/verilog6502_wrapper.yaml

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+tests:
+  - name: "verilog6502_wrapper"
+    toplevel: "verilog6502_wrapper_tb"
+    modules:
+      - "verilog6502_wrapper_test"
+    sources: "sources.list"
+    waves: True
+    defines:
+      SIM: "hi"

sim/verilog6502_wrapper_tb.sv

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+module verilog6502_wrapper_tb();
+
+`define SIM
+
+taxi_apb_if s_apb();
+taxi_axi_if m_axi();
+taxi_axi_if s_axi();
+
+logic clk;
+logic rst;
+
+logic o_irq_ext;
+logic i_irq_ext;
+
+
+verilog6502_wrapper u_dut(
+    .clk(clk),
+    .rst(rst),
+    .s_apb(s_apb),
+    .m_axi_rd(m_axi),
+    .m_axi_wr(m_axi),
+    .s_axi_rd(s_axi),
+    .s_axi_wr(s_axi),
+    .o_irq_ext(o_irq_ext),
+    .i_irq_ext(i_irq_ext)
+);
+
+endmodule

sim/verilog6502_wrapper_test.py

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+import cocotb
+from cocotb.handle import Immediate
+
+from cocotb.clock import Clock
+from cocotb.triggers import Timer, RisingEdge
+
+from cocotbext.axi.apb import ApbMaster, ApbBus
+from cocotbext.axi import AxiMaster, AxiBus
+
+
+
+CLK_PERIOD = 5
+
+
+@cocotb.test
+async def test_sanity(dut):
+    print("Hello world")
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+
+    s_apb = ApbMaster(ApbBus.from_prefix(dut.s_apb, ""), dut.clk, dut.rst)
+
+    s_axi = AxiMaster(AxiBus.from_prefix(dut.s_axi, ""), dut.clk, dut.rst)
+
+
+    dut.rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.rst.value = 0
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+
+    await s_axi.write(0x0, [0x4c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00])
+    
+    cocotb.start_soon(s_axi.read(0x0, 8))
+
+    await Timer(10, "us")
+
+    await s_apb.write_dword(0x0, 0)
+
+    await Timer(10, "us")