initial commit

sim/verilog6502_wrapper_test.py

@@ -0,0 +1,40 @@
+import cocotb
+from cocotb.handle import Immediate
+
+from cocotb.clock import Clock
+from cocotb.triggers import Timer, RisingEdge
+
+from cocotbext.axi.apb import ApbMaster, ApbBus
+from cocotbext.axi import AxiMaster, AxiBus
+
+
+
+CLK_PERIOD = 5
+
+
+@cocotb.test
+async def test_sanity(dut):
+    print("Hello world")
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+
+    s_apb = ApbMaster(ApbBus.from_prefix(dut.s_apb, ""), dut.clk, dut.rst)
+
+    s_axi = AxiMaster(AxiBus.from_prefix(dut.s_axi, ""), dut.clk, dut.rst)
+
+
+    dut.rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.rst.value = 0
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+
+    await s_axi.write(0x0, [0x4c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00])
+    
+    cocotb.start_soon(s_axi.read(0x0, 8))
+
+    await Timer(10, "us")
+
+    await s_apb.write_dword(0x0, 0)
+
+    await Timer(10, "us")