Start over pretty much.
This commit is contained in:
Byron Lathi
1
hw/efinix_fpga/.lock
Normal file
1
hw/efinix_fpga/.lock
Normal file
@@ -0,0 +1 @@
|
||||
18538
|
||||
@@ -1,27 +0,0 @@
|
||||
module HexDriver (input [3:0] In0,
|
||||
output logic [6:0] Out0);
|
||||
|
||||
always_comb
|
||||
begin
|
||||
unique case (In0)
|
||||
4'b0000 : Out0 = 7'b1000000; // '0'
|
||||
4'b0001 : Out0 = 7'b1111001; // '1'
|
||||
4'b0010 : Out0 = 7'b0100100; // '2'
|
||||
4'b0011 : Out0 = 7'b0110000; // '3'
|
||||
4'b0100 : Out0 = 7'b0011001; // '4'
|
||||
4'b0101 : Out0 = 7'b0010010; // '5'
|
||||
4'b0110 : Out0 = 7'b0000010; // '6'
|
||||
4'b0111 : Out0 = 7'b1111000; // '7'
|
||||
4'b1000 : Out0 = 7'b0000000; // '8'
|
||||
4'b1001 : Out0 = 7'b0010000; // '9'
|
||||
4'b1010 : Out0 = 7'b0001000; // 'A'
|
||||
4'b1011 : Out0 = 7'b0000011; // 'b'
|
||||
4'b1100 : Out0 = 7'b1000110; // 'C'
|
||||
4'b1101 : Out0 = 7'b0100001; // 'd'
|
||||
4'b1110 : Out0 = 7'b0000110; // 'E'
|
||||
4'b1111 : Out0 = 7'b0001110; // 'F'
|
||||
default : Out0 = 7'bX;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,42 +0,0 @@
|
||||
module SevenSeg(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input rw,
|
||||
|
||||
input [7:0] data,
|
||||
input cs,
|
||||
input [1:0] addr,
|
||||
|
||||
output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5
|
||||
);
|
||||
|
||||
logic [7:0] _data [3:0];
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst)
|
||||
_data = '{default:'0};
|
||||
if (~rw & cs)
|
||||
_data[addr] <= data;
|
||||
end
|
||||
|
||||
|
||||
logic [3:0] hex_4[5:0];
|
||||
|
||||
assign {hex_4[5], hex_4[4]} = _data[2];
|
||||
assign {hex_4[3], hex_4[2]} = _data[1];
|
||||
assign {hex_4[1], hex_4[0]} = _data[0];
|
||||
|
||||
logic [6:0] _HEX0, _HEX1, _HEX2, _HEX3, _HEX4, _HEX5;
|
||||
|
||||
HexDriver hex_drivers[5:0] (hex_4, {_HEX5, _HEX4, _HEX3, _HEX2, _HEX1, _HEX0});
|
||||
|
||||
assign HEX0 = _HEX0 | {7{~_data[3][0]}};
|
||||
assign HEX1 = _HEX1 | {7{~_data[3][1]}};
|
||||
assign HEX2 = _HEX2 | {7{~_data[3][2]}};
|
||||
assign HEX3 = _HEX3 | {7{~_data[3][3]}};
|
||||
assign HEX4 = _HEX4 | {7{~_data[3][4]}};
|
||||
assign HEX5 = _HEX5 | {7{~_data[3][5]}};
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -1,24 +0,0 @@
|
||||
module addr_decode(
|
||||
input logic [23:0] addr,
|
||||
output logic sdram_cs,
|
||||
output logic rom_cs,
|
||||
output logic hex_cs,
|
||||
output logic uart_cs,
|
||||
output logic irq_cs,
|
||||
output logic board_io_cs,
|
||||
output logic mm_cs1,
|
||||
output logic mm_cs2,
|
||||
output logic sd_cs
|
||||
);
|
||||
|
||||
assign rom_cs = addr >= 24'h008000 && addr < 24'h010000;
|
||||
assign sdram_cs = addr < 24'h007fe0 || addr >= 24'h010000;
|
||||
assign mm_cs1 = addr >= 24'h007fe0 && addr < 24'h007ff0;
|
||||
assign hex_cs = addr >= 24'h007ff0 && addr < 24'h007ff4;
|
||||
assign uart_cs = addr >= 24'h007ff4 && addr < 24'h007ff6;
|
||||
assign board_io_cs = addr == 24'h007ff6;
|
||||
assign mm_cs2 = addr == 24'h007ff7;
|
||||
assign sd_cs = addr >= 24'h007ff8 && addr < 24'h007ffe;
|
||||
assign irq_cs = addr == 24'h007fff;
|
||||
|
||||
endmodule
|
||||
@@ -1,27 +0,0 @@
|
||||
module board_io(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input rw,
|
||||
|
||||
input [7:0] data_in,
|
||||
input cs,
|
||||
input [1:0] addr,
|
||||
|
||||
output logic [7:0] data_out,
|
||||
|
||||
output logic [7:0] led,
|
||||
input [7:0] sw
|
||||
);
|
||||
|
||||
assign data_out = sw;
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst)
|
||||
led = '0;
|
||||
if (~rw & cs)
|
||||
led <= data_in;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,106 +0,0 @@
|
||||
module crc7 #(parameter POLYNOMIAL = 8'h89)
|
||||
(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input load,
|
||||
input [39:0] data_in,
|
||||
|
||||
output logic [6:0] crc_out,
|
||||
output logic valid
|
||||
);
|
||||
|
||||
logic [46:0] data;
|
||||
logic [46:0] next_data;
|
||||
logic [46:0] polyshift;
|
||||
|
||||
typedef enum bit [1:0] {IDLE, WORKING, VALID} macro_t;
|
||||
struct packed {
|
||||
macro_t macro;
|
||||
logic [5:0] count;
|
||||
} state, next_state;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
polyshift <= {POLYNOMIAL, 39'b0}; //start all the way at the left
|
||||
data <= '0;
|
||||
state.macro <= IDLE;
|
||||
state.count <= '0;
|
||||
end else begin
|
||||
if (load) begin
|
||||
data <= {data_in, 7'b0};
|
||||
end else begin
|
||||
data <= next_data;
|
||||
end
|
||||
state <= next_state;
|
||||
|
||||
if (state.macro == WORKING) begin
|
||||
polyshift <= polyshift >> 1;
|
||||
end
|
||||
|
||||
if (state.macro == VALID) begin
|
||||
polyshift <= {POLYNOMIAL, 39'b0};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
next_state = state;
|
||||
|
||||
case (state.macro)
|
||||
IDLE: begin
|
||||
if (load) begin
|
||||
next_state.macro = WORKING;
|
||||
next_state.count = '0;
|
||||
end
|
||||
end
|
||||
|
||||
WORKING: begin
|
||||
if (state.count < 39) begin
|
||||
next_state.count = state.count + 6'b1;
|
||||
end else begin
|
||||
next_state.macro = VALID;
|
||||
next_state.count = '0;
|
||||
end
|
||||
end
|
||||
|
||||
VALID: begin // Same as IDLE, but IDLE is just for reset.
|
||||
if (load) begin
|
||||
next_state.macro = WORKING;
|
||||
next_state.count = '0;
|
||||
end
|
||||
end
|
||||
|
||||
default:;
|
||||
endcase
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
valid = 0;
|
||||
next_data = '0;
|
||||
crc_out = '0;
|
||||
|
||||
case (state.macro)
|
||||
IDLE: begin
|
||||
valid = 0;
|
||||
end
|
||||
|
||||
WORKING: begin
|
||||
if (data[6'd46 - state.count]) begin
|
||||
next_data = data ^ polyshift;
|
||||
end else begin
|
||||
next_data = data;
|
||||
end
|
||||
end
|
||||
|
||||
VALID: begin
|
||||
valid = ~load;
|
||||
next_data = data;
|
||||
crc_out = data[6:0];
|
||||
end
|
||||
|
||||
default:;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
297
hw/efinix_fpga/debug_profile.wizard.json
Normal file
297
hw/efinix_fpga/debug_profile.wizard.json
Normal file
@@ -0,0 +1,297 @@
|
||||
{
|
||||
"debug_cores": [
|
||||
{
|
||||
"name": "la0",
|
||||
"type": "la",
|
||||
"uuid": "d64eaf74d37c4eb79fa6271eeceeb4bc",
|
||||
"trigin_en": false,
|
||||
"trigout_en": false,
|
||||
"auto_inserted": true,
|
||||
"capture_control": false,
|
||||
"data_depth": 32,
|
||||
"input_pipeline": 1,
|
||||
"probes": [
|
||||
{
|
||||
"name": "cpu_resb",
|
||||
"width": 1,
|
||||
"probe_type": 1
|
||||
},
|
||||
{
|
||||
"name": "cpu_addr",
|
||||
"width": 16,
|
||||
"probe_type": 1
|
||||
},
|
||||
{
|
||||
"name": "button_reset",
|
||||
"width": 1,
|
||||
"probe_type": 1
|
||||
}
|
||||
]
|
||||
}
|
||||
],
|
||||
"connections": [
|
||||
{
|
||||
"command": "add_ports",
|
||||
"id": 1,
|
||||
"args": {
|
||||
"netlist": "super6502",
|
||||
"ports": [
|
||||
{
|
||||
"name": "jtag_inst1_CAPTURE",
|
||||
"dir": "in",
|
||||
"width": 1
|
||||
},
|
||||
{
|
||||
"name": "jtag_inst1_DRCK",
|
||||
"dir": "in",
|
||||
"width": 1
|
||||
},
|
||||
{
|
||||
"name": "jtag_inst1_RESET",
|
||||
"dir": "in",
|
||||
"width": 1
|
||||
},
|
||||
{
|
||||
"name": "jtag_inst1_RUNTEST",
|
||||
"dir": "in",
|
||||
"width": 1
|
||||
},
|
||||
{
|
||||
"name": "jtag_inst1_SEL",
|
||||
"dir": "in",
|
||||
"width": 1
|
||||
},
|
||||
{
|
||||
"name": "jtag_inst1_SHIFT",
|
||||
"dir": "in",
|
||||
"width": 1
|
||||
},
|
||||
{
|
||||
"name": "jtag_inst1_TCK",
|
||||
"dir": "in",
|
||||
"width": 1
|
||||
},
|
||||
{
|
||||
"name": "jtag_inst1_TDI",
|
||||
"dir": "in",
|
||||
"width": 1
|
||||
},
|
||||
{
|
||||
"name": "jtag_inst1_TMS",
|
||||
"dir": "in",
|
||||
"width": 1
|
||||
},
|
||||
{
|
||||
"name": "jtag_inst1_UPDATE",
|
||||
"dir": "in",
|
||||
"width": 1
|
||||
},
|
||||
{
|
||||
"name": "jtag_inst1_TDO",
|
||||
"dir": "out",
|
||||
"width": 1
|
||||
}
|
||||
]
|
||||
}
|
||||
},
|
||||
{
|
||||
"command": "instantiate",
|
||||
"netlist": "edb_top",
|
||||
"id": 2,
|
||||
"instance": "edb_top_inst"
|
||||
},
|
||||
{
|
||||
"command": "connect",
|
||||
"id": 3,
|
||||
"args": {
|
||||
"instance": "edb_top_inst",
|
||||
"ports": [
|
||||
{
|
||||
"name": "bscan_CAPTURE",
|
||||
"net": "jtag_inst1_CAPTURE"
|
||||
},
|
||||
{
|
||||
"name": "bscan_DRCK",
|
||||
"net": "jtag_inst1_DRCK"
|
||||
},
|
||||
{
|
||||
"name": "bscan_RESET",
|
||||
"net": "jtag_inst1_RESET"
|
||||
},
|
||||
{
|
||||
"name": "bscan_RUNTEST",
|
||||
"net": "jtag_inst1_RUNTEST"
|
||||
},
|
||||
{
|
||||
"name": "bscan_SEL",
|
||||
"net": "jtag_inst1_SEL"
|
||||
},
|
||||
{
|
||||
"name": "bscan_SHIFT",
|
||||
"net": "jtag_inst1_SHIFT"
|
||||
},
|
||||
{
|
||||
"name": "bscan_TCK",
|
||||
"net": "jtag_inst1_TCK"
|
||||
},
|
||||
{
|
||||
"name": "bscan_TDI",
|
||||
"net": "jtag_inst1_TDI"
|
||||
},
|
||||
{
|
||||
"name": "bscan_TMS",
|
||||
"net": "jtag_inst1_TMS"
|
||||
},
|
||||
{
|
||||
"name": "bscan_UPDATE",
|
||||
"net": "jtag_inst1_UPDATE"
|
||||
},
|
||||
{
|
||||
"name": "bscan_TDO",
|
||||
"net": "jtag_inst1_TDO"
|
||||
},
|
||||
{
|
||||
"name": "la0_clk",
|
||||
"net": "clk_2",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe0",
|
||||
"net": "cpu_resb",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[0]",
|
||||
"net": "cpu_addr[0]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[1]",
|
||||
"net": "cpu_addr[1]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[2]",
|
||||
"net": "cpu_addr[2]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[3]",
|
||||
"net": "cpu_addr[3]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[4]",
|
||||
"net": "cpu_addr[4]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[5]",
|
||||
"net": "cpu_addr[5]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[6]",
|
||||
"net": "cpu_addr[6]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[7]",
|
||||
"net": "cpu_addr[7]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[8]",
|
||||
"net": "cpu_addr[8]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[9]",
|
||||
"net": "cpu_addr[9]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[10]",
|
||||
"net": "cpu_addr[10]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[11]",
|
||||
"net": "cpu_addr[11]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[12]",
|
||||
"net": "cpu_addr[12]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[13]",
|
||||
"net": "cpu_addr[13]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[14]",
|
||||
"net": "cpu_addr[14]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe1[15]",
|
||||
"net": "cpu_addr[15]",
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "la0_probe2",
|
||||
"net": "button_reset",
|
||||
"path": []
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
],
|
||||
"vdbs": [
|
||||
{
|
||||
"file": "debug_top.post.vdb",
|
||||
"instance": "edb_top_inst"
|
||||
}
|
||||
],
|
||||
"session": {
|
||||
"wizard": {
|
||||
"data_depth": 32,
|
||||
"capture_control": false,
|
||||
"selected_nets": [
|
||||
{
|
||||
"name": "cpu_resb",
|
||||
"width": 1,
|
||||
"clk_domain": "clk_2",
|
||||
"selected_probe_type": "DATA AND TRIGGER",
|
||||
"child": [],
|
||||
"path": []
|
||||
},
|
||||
{
|
||||
"name": "cpu_addr",
|
||||
"width": 16,
|
||||
"clk_domain": "clk_2",
|
||||
"selected_probe_type": "DATA AND TRIGGER",
|
||||
"child": [],
|
||||
"path": [],
|
||||
"net_idx_left": 15,
|
||||
"net_idx_right": 0
|
||||
},
|
||||
{
|
||||
"name": "button_reset",
|
||||
"width": 1,
|
||||
"clk_domain": "clk_2",
|
||||
"selected_probe_type": "DATA AND TRIGGER",
|
||||
"child": [],
|
||||
"path": []
|
||||
}
|
||||
],
|
||||
"top_module": "super6502",
|
||||
"db_checksum": "ba5fce12098a2c03e7bae2e9a172d1842464edfca8e284870b3519e987537970",
|
||||
"src": "elaborate",
|
||||
"jtag_user": "USER1",
|
||||
"input_pipeline": 1
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,80 +0,0 @@
|
||||
// =============================================================================
|
||||
// Generated by efx_ipmgr
|
||||
// Version: 2021.2.323
|
||||
// IP Version: 1.5
|
||||
// =============================================================================
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
|
||||
//
|
||||
// This document contains proprietary information which is
|
||||
// protected by copyright. All rights are reserved. This notice
|
||||
// refers to original work by Efinix, Inc. which may be derivitive
|
||||
// of other work distributed under license of the authors. In the
|
||||
// case of derivative work, nothing in this notice overrides the
|
||||
// original author's license agreement. Where applicable, the
|
||||
// original license agreement is included in it's original
|
||||
// unmodified form immediately below this header.
|
||||
//
|
||||
// WARRANTY DISCLAIMER.
|
||||
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
|
||||
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
|
||||
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
|
||||
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
|
||||
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
|
||||
//
|
||||
// LIMITATION OF LIABILITY.
|
||||
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
|
||||
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
|
||||
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
|
||||
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
|
||||
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
|
||||
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
|
||||
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
|
||||
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
|
||||
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
|
||||
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
|
||||
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
|
||||
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
|
||||
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
|
||||
// APPLY TO LICENSEE.
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
localparam fSYS_MHz = 100;
|
||||
localparam fCK_MHz = 200;
|
||||
localparam tIORT_u = 2;
|
||||
localparam BL = 1;
|
||||
localparam DDIO_TYPE = "SOFT";
|
||||
localparam DQ_WIDTH = 8;
|
||||
localparam DQ_GROUP = 2;
|
||||
localparam BA_WIDTH = 2;
|
||||
localparam ROW_WIDTH = 13;
|
||||
localparam COL_WIDTH = 9;
|
||||
localparam tPWRUP = 200000;
|
||||
localparam tRAS = 44;
|
||||
localparam tRC = 66;
|
||||
localparam tRCD = 20;
|
||||
localparam tREF = 64000000;
|
||||
localparam tWR = 2;
|
||||
localparam tMRD = 2;
|
||||
localparam tRFC = 66;
|
||||
localparam tRAS_MAX = 120000;
|
||||
localparam DATA_RATE = 2;
|
||||
localparam AXI_ARADDR_WIDTH = 24;
|
||||
localparam SDRAM_MODE = "Native";
|
||||
localparam AXI_BUSER_WIDTH = 2;
|
||||
localparam AXI_BID_WIDTH = 4;
|
||||
localparam AXI_AWUSER_WIDTH = 2;
|
||||
localparam AXI_AWID_WIDTH = 4;
|
||||
localparam AXI_AWADDR_WIDTH = 24;
|
||||
localparam AXI_RDATA_WIDTH = 32;
|
||||
localparam AXI_WUSER_WIDTH = 2;
|
||||
localparam AXI_WDATA_WIDTH = 32;
|
||||
localparam AXI_RUSER_WIDTH = 3;
|
||||
localparam AXI_ARUSER_WIDTH = 3;
|
||||
localparam AXI_ARID_WIDTH = 4;
|
||||
localparam tRP = 20;
|
||||
localparam CL = 3;
|
||||
@@ -1,83 +0,0 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
|
||||
//
|
||||
// This document contains proprietary information which is
|
||||
// protected by copyright. All rights are reserved. This notice
|
||||
// refers to original work by Efinix, Inc. which may be derivitive
|
||||
// of other work distributed under license of the authors. In the
|
||||
// case of derivative work, nothing in this notice overrides the
|
||||
// original author's license agreement. Where applicable, the
|
||||
// original license agreement is included in it's original
|
||||
// unmodified form immediately below this header.
|
||||
//
|
||||
// WARRANTY DISCLAIMER.
|
||||
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
|
||||
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
|
||||
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
|
||||
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
|
||||
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
|
||||
//
|
||||
// LIMITATION OF LIABILITY.
|
||||
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
|
||||
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
|
||||
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
|
||||
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
|
||||
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
|
||||
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
|
||||
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
|
||||
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
|
||||
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
|
||||
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
|
||||
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
|
||||
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
|
||||
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
|
||||
// APPLY TO LICENSEE.
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
sdram u_sdram(
|
||||
.i_we ( i_we ),
|
||||
.i_sysclk ( i_sysclk ),
|
||||
.i_arst ( i_arst ),
|
||||
.i_sdrclk ( i_sdrclk ),
|
||||
.i_tACclk ( i_tACclk ),
|
||||
.i_pll_locked ( i_pll_locked ),
|
||||
.i_re ( i_re ),
|
||||
.i_last ( i_last ),
|
||||
.o_dbg_tRTW_done ( o_dbg_tRTW_done ),
|
||||
.o_dbg_ref_req ( o_dbg_ref_req ),
|
||||
.o_dbg_wr_ack ( o_dbg_wr_ack ),
|
||||
.o_dbg_rd_ack ( o_dbg_rd_ack ),
|
||||
.o_dbg_n_CS ( o_dbg_n_CS ),
|
||||
.o_dbg_n_RAS ( o_dbg_n_RAS ),
|
||||
.o_dbg_n_CAS ( o_dbg_n_CAS ),
|
||||
.o_dbg_n_WE ( o_dbg_n_WE ),
|
||||
.o_dbg_BA ( o_dbg_BA ),
|
||||
.o_dbg_ADDR ( o_dbg_ADDR ),
|
||||
.o_dbg_DATA_out ( o_dbg_DATA_out ),
|
||||
.o_dbg_DATA_in ( o_dbg_DATA_in ),
|
||||
.i_addr ( i_addr ),
|
||||
.i_din ( i_din ),
|
||||
.o_dout ( o_dout ),
|
||||
.o_sdr_state ( o_sdr_state ),
|
||||
.o_sdr_init_done ( o_sdr_init_done ),
|
||||
.o_wr_ack ( o_wr_ack ),
|
||||
.o_rd_ack ( o_rd_ack ),
|
||||
.o_ref_req ( o_ref_req ),
|
||||
.o_rd_valid ( o_rd_valid ),
|
||||
.o_sdr_CKE ( o_sdr_CKE ),
|
||||
.o_sdr_n_CS ( o_sdr_n_CS ),
|
||||
.o_sdr_n_RAS ( o_sdr_n_RAS ),
|
||||
.o_sdr_n_CAS ( o_sdr_n_CAS ),
|
||||
.o_sdr_n_WE ( o_sdr_n_WE ),
|
||||
.o_sdr_BA ( o_sdr_BA ),
|
||||
.o_sdr_ADDR ( o_sdr_ADDR ),
|
||||
.o_sdr_DATA ( o_sdr_DATA ),
|
||||
.o_sdr_DATA_oe ( o_sdr_DATA_oe ),
|
||||
.i_sdr_DATA ( i_sdr_DATA ),
|
||||
.o_sdr_DQM ( o_sdr_DQM ),
|
||||
.o_dbg_dly_cnt_b ( o_dbg_dly_cnt_b ),
|
||||
.o_dbg_tRCD_done ( o_dbg_tRCD_done )
|
||||
);
|
||||
@@ -1,132 +0,0 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.
|
||||
//
|
||||
// This document contains proprietary information which is
|
||||
// protected by copyright. All rights are reserved. This notice
|
||||
// refers to original work by Efinix, Inc. which may be derivitive
|
||||
// of other work distributed under license of the authors. In the
|
||||
// case of derivative work, nothing in this notice overrides the
|
||||
// original author's license agreement. Where applicable, the
|
||||
// original license agreement is included in it's original
|
||||
// unmodified form immediately below this header.
|
||||
//
|
||||
// WARRANTY DISCLAIMER.
|
||||
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
|
||||
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
|
||||
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
|
||||
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
|
||||
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
|
||||
//
|
||||
// LIMITATION OF LIABILITY.
|
||||
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
|
||||
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
|
||||
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
|
||||
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
|
||||
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
|
||||
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
|
||||
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
|
||||
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
|
||||
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
|
||||
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
|
||||
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
|
||||
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
|
||||
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
|
||||
// APPLY TO LICENSEE.
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
------------- Begin Cut here for COMPONENT Declaration ------
|
||||
COMPONENT sdram is
|
||||
PORT (
|
||||
i_we : in std_logic;
|
||||
i_sysclk : in std_logic;
|
||||
i_arst : in std_logic;
|
||||
i_sdrclk : in std_logic;
|
||||
i_tACclk : in std_logic;
|
||||
i_pll_locked : in std_logic;
|
||||
i_re : in std_logic;
|
||||
i_last : in std_logic;
|
||||
o_dbg_tRTW_done : out std_logic;
|
||||
o_dbg_ref_req : out std_logic;
|
||||
o_dbg_wr_ack : out std_logic;
|
||||
o_dbg_rd_ack : out std_logic;
|
||||
o_dbg_n_CS : out std_logic_vector(1 downto 0);
|
||||
o_dbg_n_RAS : out std_logic_vector(1 downto 0);
|
||||
o_dbg_n_CAS : out std_logic_vector(1 downto 0);
|
||||
o_dbg_n_WE : out std_logic_vector(1 downto 0);
|
||||
o_dbg_BA : out std_logic_vector(3 downto 0);
|
||||
o_dbg_ADDR : out std_logic_vector(25 downto 0);
|
||||
o_dbg_DATA_out : out std_logic_vector(31 downto 0);
|
||||
o_dbg_DATA_in : out std_logic_vector(31 downto 0);
|
||||
i_addr : in std_logic_vector(23 downto 0);
|
||||
i_din : in std_logic_vector(31 downto 0);
|
||||
o_dout : out std_logic_vector(31 downto 0);
|
||||
o_sdr_state : out std_logic_vector(3 downto 0);
|
||||
o_sdr_init_done : out std_logic;
|
||||
o_wr_ack : out std_logic;
|
||||
o_rd_ack : out std_logic;
|
||||
o_ref_req : out std_logic;
|
||||
o_rd_valid : out std_logic;
|
||||
o_sdr_CKE : out std_logic_vector(1 downto 0);
|
||||
o_sdr_n_CS : out std_logic_vector(1 downto 0);
|
||||
o_sdr_n_RAS : out std_logic_vector(1 downto 0);
|
||||
o_sdr_n_CAS : out std_logic_vector(1 downto 0);
|
||||
o_sdr_n_WE : out std_logic_vector(1 downto 0);
|
||||
o_sdr_BA : out std_logic_vector(3 downto 0);
|
||||
o_sdr_ADDR : out std_logic_vector(25 downto 0);
|
||||
o_sdr_DATA : out std_logic_vector(31 downto 0);
|
||||
o_sdr_DATA_oe : out std_logic_vector(31 downto 0);
|
||||
i_sdr_DATA : in std_logic_vector(31 downto 0);
|
||||
o_sdr_DQM : out std_logic_vector(3 downto 0);
|
||||
o_dbg_dly_cnt_b : out std_logic_vector(5 downto 0);
|
||||
o_dbg_tRCD_done : out std_logic);
|
||||
END COMPONENT;
|
||||
---------------------- End COMPONENT Declaration ------------
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template -----
|
||||
u_sdram : sdram
|
||||
PORT MAP (
|
||||
i_we => i_we,
|
||||
i_sysclk => i_sysclk,
|
||||
i_arst => i_arst,
|
||||
i_sdrclk => i_sdrclk,
|
||||
i_tACclk => i_tACclk,
|
||||
i_pll_locked => i_pll_locked,
|
||||
i_re => i_re,
|
||||
i_last => i_last,
|
||||
o_dbg_tRTW_done => o_dbg_tRTW_done,
|
||||
o_dbg_ref_req => o_dbg_ref_req,
|
||||
o_dbg_wr_ack => o_dbg_wr_ack,
|
||||
o_dbg_rd_ack => o_dbg_rd_ack,
|
||||
o_dbg_n_CS => o_dbg_n_CS,
|
||||
o_dbg_n_RAS => o_dbg_n_RAS,
|
||||
o_dbg_n_CAS => o_dbg_n_CAS,
|
||||
o_dbg_n_WE => o_dbg_n_WE,
|
||||
o_dbg_BA => o_dbg_BA,
|
||||
o_dbg_ADDR => o_dbg_ADDR,
|
||||
o_dbg_DATA_out => o_dbg_DATA_out,
|
||||
o_dbg_DATA_in => o_dbg_DATA_in,
|
||||
i_addr => i_addr,
|
||||
i_din => i_din,
|
||||
o_dout => o_dout,
|
||||
o_sdr_state => o_sdr_state,
|
||||
o_sdr_init_done => o_sdr_init_done,
|
||||
o_wr_ack => o_wr_ack,
|
||||
o_rd_ack => o_rd_ack,
|
||||
o_ref_req => o_ref_req,
|
||||
o_rd_valid => o_rd_valid,
|
||||
o_sdr_CKE => o_sdr_CKE,
|
||||
o_sdr_n_CS => o_sdr_n_CS,
|
||||
o_sdr_n_RAS => o_sdr_n_RAS,
|
||||
o_sdr_n_CAS => o_sdr_n_CAS,
|
||||
o_sdr_n_WE => o_sdr_n_WE,
|
||||
o_sdr_BA => o_sdr_BA,
|
||||
o_sdr_ADDR => o_sdr_ADDR,
|
||||
o_sdr_DATA => o_sdr_DATA,
|
||||
o_sdr_DATA_oe => o_sdr_DATA_oe,
|
||||
i_sdr_DATA => i_sdr_DATA,
|
||||
o_sdr_DQM => o_sdr_DQM,
|
||||
o_dbg_dly_cnt_b => o_dbg_dly_cnt_b,
|
||||
o_dbg_tRCD_done => o_dbg_tRCD_done);
|
||||
------------------------ End INSTANTIATION Template ---------
|
||||
@@ -1,44 +0,0 @@
|
||||
{
|
||||
"args": [
|
||||
"-o",
|
||||
"sdram",
|
||||
"--base_path",
|
||||
"/home/byron/Projects/super6502/hw/efinix_fpga/ip",
|
||||
"--vlnv",
|
||||
{
|
||||
"vendor": "efinixinc.com",
|
||||
"library": "memory_controller",
|
||||
"name": "efx_sdram_controller",
|
||||
"version": "1.5"
|
||||
}
|
||||
],
|
||||
"conf": {
|
||||
"fCK_MHz": "200",
|
||||
"tIORT_u": "2",
|
||||
"CL": "3",
|
||||
"DDIO_TYPE": "0",
|
||||
"DQ_GROUP": "2",
|
||||
"ROW_WIDTH": "13",
|
||||
"COL_WIDTH": "9",
|
||||
"tPWRUP": "200000",
|
||||
"tRAS": "44",
|
||||
"tRAS_MAX": "120000",
|
||||
"tRC": "66",
|
||||
"tRCD": "20",
|
||||
"tREF": "64000000",
|
||||
"tRFC ": "66",
|
||||
"tRP": "20",
|
||||
"SDRAM_MODE": "0",
|
||||
"DATA_RATE": "2"
|
||||
},
|
||||
"output": {
|
||||
"external_source": [
|
||||
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v",
|
||||
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram_define.vh",
|
||||
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram_tmpl.vhd",
|
||||
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram_tmpl.v"
|
||||
]
|
||||
},
|
||||
"sw_version": "2021.2.323",
|
||||
"generated_date": "2022-06-12T00:16:17.036312"
|
||||
}
|
||||
@@ -1,58 +0,0 @@
|
||||
/*
|
||||
* This is based off of the 74LS610, but is not identical.
|
||||
Some of the inputs are flipped so that they are all active high,
|
||||
and some outputs are reordered.
|
||||
Notably, when MM is low, MA is present on MO0-MO4, not 8 to 11.
|
||||
*/
|
||||
|
||||
module memory_mapper(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input rw,
|
||||
input cs,
|
||||
|
||||
input MM_cs,
|
||||
|
||||
input [3:0] RS,
|
||||
|
||||
input [3:0] MA,
|
||||
|
||||
input logic [11:0] data_in,
|
||||
output logic [11:0] data_out,
|
||||
|
||||
output logic [11:0] MO
|
||||
);
|
||||
|
||||
logic [11:0] RAM [16];
|
||||
|
||||
logic MM;
|
||||
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
MM <= '0;
|
||||
end else begin
|
||||
if (MM_cs & ~rw) begin // can't read MM but do you really need too?
|
||||
MM = |data_in;
|
||||
end
|
||||
|
||||
if (cs & ~rw) begin // write to registers
|
||||
RAM[RS] <= data_in;
|
||||
end else if (cs & rw) begin // read registers
|
||||
data_out <= RAM[RS];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always_comb begin
|
||||
if (MM) begin // normal mode
|
||||
MO = RAM[MA];
|
||||
end else begin // passthrough mode
|
||||
MO = {8'b0, MA};
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,159 +0,0 @@
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 09, 2022 21:36:12
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0010 VERI-ERROR] instantiating unknown module 'cpu_clk' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:92)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 09, 2022 21:36:40
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0010 VERI-ERROR] instantiating unknown module 'memory_mapper' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:118)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 09, 2022 21:42:28
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:85)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 12:05:39
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:85)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:19:40
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0010 VERI-ERROR] overwriting previous definition of module 'sdram' (VERI-1206) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:174)
|
||||
[EFX-0010 VERI-ERROR] module 'axi4_sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1006)
|
||||
[EFX-0010 VERI-ERROR] module 'dual_clock_fifo_wrapper_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1327)
|
||||
[EFX-0010 VERI-ERROR] module 'dual_clock_fifo_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1740)
|
||||
[EFX-0010 VERI-ERROR] module 'efx_sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:2308)
|
||||
[EFX-0010 VERI-ERROR] module 'sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:2585)
|
||||
[EFX-0010 VERI-ERROR] module 'sdram_fsm_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3419)
|
||||
[EFX-0010 VERI-ERROR] module 'sdram_io_block_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3784)
|
||||
[EFX-0010 VERI-ERROR] module 'sdram_simple_dual_port_ram_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3948)
|
||||
[EFX-0010 VERI-ERROR] module 'sync_ddio_group_in_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:4066)
|
||||
[EFX-0010 VERI-ERROR] module 'sync_ddio_group_out_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:4194)
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:20:04
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:20:55
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:21:29
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:85)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:21:33
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:85)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 13, 2022 19:05:46
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0010 VERI-ERROR] 'DQ_GROUP' is not a constant (VERI-1188) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
|
||||
[EFX-0010 VERI-ERROR] module 'sdram_adapter' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:68)
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 13, 2022 19:08:09
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0010 VERI-ERROR] 'DQ_GROUP' is not a constant (VERI-1188) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
|
||||
[EFX-0010 VERI-ERROR] module 'sdram_adapter' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:68)
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 13, 2022 19:08:21
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
@@ -1,397 +0,0 @@
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 09, 2022 21:36:12
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
|
||||
[EFX-0010 VERI-ERROR] instantiating unknown module 'cpu_clk' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:92)
|
||||
[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 09, 2022 21:36:40
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
|
||||
[EFX-0010 VERI-ERROR] instantiating unknown module 'memory_mapper' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:118)
|
||||
[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 09, 2022 21:42:28
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
|
||||
[EFX-0012 VERI-INFO] compiling module 'memory_mapper' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:8)
|
||||
[EFX-0012 VERI-INFO] extracting RAM for identifier 'RAM' (VERI-2571) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:27)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
|
||||
[EFX-0012 VERI-INFO] compiling module 'addr_decode' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv:1)
|
||||
[EFX-0012 VERI-INFO] compiling module 'sdram' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:1)
|
||||
[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:85)
|
||||
[EFX-0012 VERI-INFO] module 'sdram' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:1)
|
||||
[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 12:05:39
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
|
||||
[EFX-0012 VERI-INFO] compiling module 'memory_mapper' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:8)
|
||||
[EFX-0012 VERI-INFO] extracting RAM for identifier 'RAM' (VERI-2571) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:27)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
|
||||
[EFX-0012 VERI-INFO] compiling module 'addr_decode' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv:1)
|
||||
[EFX-0012 VERI-INFO] compiling module 'sdram' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:1)
|
||||
[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:85)
|
||||
[EFX-0012 VERI-INFO] module 'sdram' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:1)
|
||||
[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:19:40
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
[EFX-0010 VERI-ERROR] overwriting previous definition of module 'sdram' (VERI-1206) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:174)
|
||||
[EFX-0012 VERI-INFO] previous definition of design element 'sdram' is here (VERI-2142) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:87)
|
||||
[EFX-0010 VERI-ERROR] module 'axi4_sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1006)
|
||||
[EFX-0010 VERI-ERROR] module 'dual_clock_fifo_wrapper_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1327)
|
||||
[EFX-0010 VERI-ERROR] module 'dual_clock_fifo_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1740)
|
||||
[EFX-0010 VERI-ERROR] module 'efx_sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:2308)
|
||||
[EFX-0010 VERI-ERROR] module 'sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:2585)
|
||||
[EFX-0010 VERI-ERROR] module 'sdram_fsm_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3419)
|
||||
[EFX-0010 VERI-ERROR] module 'sdram_io_block_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3784)
|
||||
[EFX-0010 VERI-ERROR] module 'sdram_simple_dual_port_ram_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3948)
|
||||
[EFX-0010 VERI-ERROR] module 'sync_ddio_group_in_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:4066)
|
||||
[EFX-0010 VERI-ERROR] module 'sync_ddio_group_out_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:4194)
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:20:04
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0011 VERI-WARNING] port 'i_we' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
|
||||
[EFX-0011 VERI-WARNING] port 'o_dbg_tRTW_done' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:20:55
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
|
||||
[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
|
||||
[EFX-0011 VERI-WARNING] port 'i_we' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
|
||||
[EFX-0011 VERI-WARNING] port 'o_dbg_tRTW_done' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:21:29
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
|
||||
[EFX-0012 VERI-INFO] compiling module 'memory_mapper' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:8)
|
||||
[EFX-0012 VERI-INFO] extracting RAM for identifier 'RAM' (VERI-2571) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:27)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
|
||||
[EFX-0012 VERI-INFO] compiling module 'addr_decode' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv:1)
|
||||
[EFX-0012 VERI-INFO] compiling module 'sdram_adapter' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:85)
|
||||
[EFX-0012 VERI-INFO] module 'sdram_adapter' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:21:33
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
|
||||
[EFX-0012 VERI-INFO] compiling module 'memory_mapper' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:8)
|
||||
[EFX-0012 VERI-INFO] extracting RAM for identifier 'RAM' (VERI-2571) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:27)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
|
||||
[EFX-0012 VERI-INFO] compiling module 'addr_decode' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv:1)
|
||||
[EFX-0012 VERI-INFO] compiling module 'sdram_adapter' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:85)
|
||||
[EFX-0012 VERI-INFO] module 'sdram_adapter' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 13, 2022 19:05:46
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_areset', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:21)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sysclk', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:22)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_we_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:27)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_re_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:28)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_last_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:29)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_addr_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:30)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_din_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:31)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dout', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:32)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_state', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:33)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_init_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:34)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:35)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:36)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_valid', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:38)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_CKE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:40)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:41)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:42)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:43)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:44)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:45)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:46)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:47)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA_oe', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:48)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'DQ_GROUP', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'DQ_WIDTH', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DQM', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:50)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_dly_cnt_b', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:52)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRCD_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:53)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRTW_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:54)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ref_req', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:55)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:56)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:57)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:58)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:59)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:60)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:61)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:62)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:63)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_out', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:64)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_in', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:65)
|
||||
[EFX-0010 VERI-ERROR] 'DQ_GROUP' is not a constant (VERI-1188) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
|
||||
[EFX-0010 VERI-ERROR] module 'sdram_adapter' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:68)
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 13, 2022 19:08:09
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_areset', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:21)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sysclk', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:22)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_we_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:27)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_re_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:28)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_last_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:29)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_addr_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:30)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_din_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:31)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dout', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:32)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_state', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:33)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_init_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:34)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:35)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:36)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_valid', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:38)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_CKE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:40)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:41)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:42)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:43)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:44)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:45)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:46)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:47)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA_oe', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:48)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'DQ_GROUP', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'DQ_WIDTH', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DQM', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:50)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_dly_cnt_b', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:52)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRCD_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:53)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRTW_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:54)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ref_req', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:55)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:56)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:57)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:58)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:59)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:60)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:61)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:62)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:63)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_out', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:64)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_in', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:65)
|
||||
[EFX-0010 VERI-ERROR] 'DQ_GROUP' is not a constant (VERI-1188) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
|
||||
[EFX-0010 VERI-ERROR] module 'sdram_adapter' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:68)
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 13, 2022 19:08:21
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_areset', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:21)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sysclk', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:22)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_we_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:27)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_re_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:28)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_last_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:29)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_addr_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:30)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'r_din_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:31)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dout', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:32)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_state', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:33)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_init_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:34)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:35)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:36)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_valid', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:38)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_CKE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:40)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:41)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:42)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:43)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:44)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:45)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:46)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:47)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA_oe', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:48)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DQM', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:50)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_dly_cnt_b', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:52)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRCD_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:53)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRTW_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:54)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ref_req', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:55)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:56)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:57)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:58)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:59)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:60)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:61)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:62)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:63)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_out', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:64)
|
||||
[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_in', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:65)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
|
||||
[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
|
||||
[EFX-0011 VERI-WARNING] port 'i_sysclk' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
|
||||
[EFX-0011 VERI-WARNING] port 'o_pll_reset' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
@@ -1,113 +0,0 @@
|
||||
[EFX-0000 INFO] Efinix FPGA Synthesis.
|
||||
[EFX-0000 INFO] Version: 2021.2.323.4.6
|
||||
[EFX-0000 INFO] Compiled: May 12 2022.
|
||||
[EFX-0000 INFO]
|
||||
[EFX-0000 INFO] Copyright (C) 2013 - 2021 Efinix Inc. All rights reserved.
|
||||
|
||||
INFO: Read project database "/home/byron/Projects/super6502/hw/efinix_fpga/super6502.xml"
|
||||
INFO: ***** Beginning Analysis ... *****
|
||||
INFO: default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
|
||||
-- Analyzing Verilog file '/home/byron/Software/efinity/2021.2/sim_models/maplib/efinix_maplib.v' (VERI-1482)
|
||||
-- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv' (VERI-1482)
|
||||
-- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/crc7.sv' (VERI-1482)
|
||||
-- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv' (VERI-1482)
|
||||
-- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/uart.sv' (VERI-1482)
|
||||
-- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/HexDriver.sv' (VERI-1482)
|
||||
-- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv' (VERI-1482)
|
||||
-- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/board_io.sv' (VERI-1482)
|
||||
-- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/SevenSeg.sv' (VERI-1482)
|
||||
-- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/sd_controller.sv' (VERI-1482)
|
||||
-- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv' (VERI-1482)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(21): INFO: undeclared symbol 'w_areset', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(22): INFO: undeclared symbol 'w_sysclk', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(27): INFO: undeclared symbol 'r_we_1P', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(28): INFO: undeclared symbol 'r_re_1P', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(29): INFO: undeclared symbol 'r_last_1P', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(30): INFO: undeclared symbol 'r_addr_1P', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(31): INFO: undeclared symbol 'r_din_1P', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(32): INFO: undeclared symbol 'w_dout', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(33): INFO: undeclared symbol 'w_sdr_state', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(34): INFO: undeclared symbol 'w_sdr_init_done', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(35): INFO: undeclared symbol 'w_wr_ack', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(36): INFO: undeclared symbol 'w_rd_ack', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(38): INFO: undeclared symbol 'w_rd_valid', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(40): INFO: undeclared symbol 'w_sdr_CKE', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(41): INFO: undeclared symbol 'w_sdr_n_CS', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(42): INFO: undeclared symbol 'w_sdr_n_RAS', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(43): INFO: undeclared symbol 'w_sdr_n_CAS', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(44): INFO: undeclared symbol 'w_sdr_n_WE', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(45): INFO: undeclared symbol 'w_sdr_BA', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(46): INFO: undeclared symbol 'w_sdr_ADDR', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(47): INFO: undeclared symbol 'w_sdr_DATA', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(48): INFO: undeclared symbol 'w_sdr_DATA_oe', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(50): INFO: undeclared symbol 'w_sdr_DQM', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(52): INFO: undeclared symbol 'w_dbg_dly_cnt_b', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(53): INFO: undeclared symbol 'w_dbg_tRCD_done', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(54): INFO: undeclared symbol 'w_dbg_tRTW_done', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(55): INFO: undeclared symbol 'w_dbg_ref_req', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(56): INFO: undeclared symbol 'w_dbg_wr_ack', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(57): INFO: undeclared symbol 'w_dbg_rd_ack', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(58): INFO: undeclared symbol 'w_dbg_n_CS', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(59): INFO: undeclared symbol 'w_dbg_n_RAS', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(60): INFO: undeclared symbol 'w_dbg_n_CAS', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(61): INFO: undeclared symbol 'w_dbg_n_WE', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(62): INFO: undeclared symbol 'w_dbg_BA', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(63): INFO: undeclared symbol 'w_dbg_ADDR', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(64): INFO: undeclared symbol 'w_dbg_DATA_out', assumed default net type 'wire' (VERI-2561)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(65): INFO: undeclared symbol 'w_dbg_DATA_in', assumed default net type 'wire' (VERI-2561)
|
||||
-- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v' (VERI-1482)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(155): ERROR: cannot find port 'rst' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(156): ERROR: cannot find port 'clk_50' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(157): ERROR: cannot find port 'cpu_clk' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(158): ERROR: cannot find port 'addr' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(159): ERROR: cannot find port 'sdram_cs' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(160): ERROR: cannot find port 'rwb' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(161): ERROR: cannot find port 'data_in' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(162): ERROR: cannot find port 'data_out' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(165): ERROR: cannot find port 'DRAM_CLK' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(166): ERROR: cannot find port 'DRAM_ADDR' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(167): ERROR: cannot find port 'DRAM_BA' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(168): ERROR: cannot find port 'DRAM_CAS_N' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(169): ERROR: cannot find port 'DRAM_CKE' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(170): ERROR: cannot find port 'DRAM_CS_N' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(171): ERROR: cannot find port 'DRAM_DQ' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(172): ERROR: cannot find port 'DRAM_UDQM' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(173): ERROR: cannot find port 'DRAM_LDQM' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(174): ERROR: cannot find port 'DRAM_RAS_N' on this module (VERI-1010)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(175): ERROR: cannot find port 'DRAM_WE_N' on this module (VERI-1010)
|
||||
[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
|
||||
INFO: Analysis took 0.0226114 seconds.
|
||||
INFO: Analysis took 0.02 seconds (approximately) in total CPU time.
|
||||
INFO: Analysis virtual memory usage: begin = 186.592 MB, end = 187.592 MB, delta = 1 MB
|
||||
INFO: Analysis resident set memory usage: begin = 73.968 MB, end = 77.944 MB, delta = 3.976 MB
|
||||
INFO: Analysis peak resident set memory usage = 634.104 MB
|
||||
INFO: ***** Ending Analysis ... *****
|
||||
INFO: ***** Beginning Elaboration ... *****
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(176): WARNING: port 'i_sysclk' is not connected on this instance (VERI-2435)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(176): WARNING: port 'o_pll_reset' remains unconnected for this instance (VERI-1927)
|
||||
/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(204): WARNING: port 'addr' is not connected on this instance (VERI-2435)
|
||||
INFO: Elaboration took 0.00132981 seconds.
|
||||
INFO: Elaboration took 0 seconds (approximately) in total CPU time.
|
||||
INFO: Elaboration virtual memory usage: begin = 187.592 MB, end = 187.592 MB, delta = 0 MB
|
||||
INFO: Elaboration resident set memory usage: begin = 77.944 MB, end = 77.944 MB, delta = 0 MB
|
||||
INFO: Elaboration peak resident set memory usage = 634.104 MB
|
||||
INFO: ***** Ending Elaboration ... *****
|
||||
@@ -1,93 +0,0 @@
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 09, 2022 21:36:12
|
||||
///////////////////////////////////
|
||||
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 09, 2022 21:36:40
|
||||
///////////////////////////////////
|
||||
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 09, 2022 21:42:28
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 12:05:39
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:19:40
|
||||
///////////////////////////////////
|
||||
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:20:04
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0011 VERI-WARNING] port 'i_we' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
|
||||
[EFX-0011 VERI-WARNING] port 'o_dbg_tRTW_done' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:20:55
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0011 VERI-WARNING] port 'i_we' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
|
||||
[EFX-0011 VERI-WARNING] port 'o_dbg_tRTW_done' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:21:29
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 11, 2022 19:21:33
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
|
||||
[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 13, 2022 19:05:46
|
||||
///////////////////////////////////
|
||||
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 13, 2022 19:08:09
|
||||
///////////////////////////////////
|
||||
|
||||
|
||||
///////////////////////////////////
|
||||
// Efinity Synthesis Started
|
||||
// Jun 13, 2022 19:08:21
|
||||
///////////////////////////////////
|
||||
|
||||
[EFX-0011 VERI-WARNING] port 'i_sysclk' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
|
||||
[EFX-0011 VERI-WARNING] port 'o_pll_reset' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
|
||||
[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
|
||||
@@ -1,235 +0,0 @@
|
||||
module sd_controller(
|
||||
input clk,
|
||||
input sd_clk,
|
||||
input rst,
|
||||
|
||||
input [2:0] addr,
|
||||
input [7:0] data,
|
||||
input cs,
|
||||
input rw,
|
||||
|
||||
input i_sd_cmd,
|
||||
output logic o_sd_cmd,
|
||||
|
||||
input i_sd_data,
|
||||
output logic o_sd_data,
|
||||
|
||||
output logic [7:0] data_out
|
||||
);
|
||||
|
||||
logic [31:0] arg;
|
||||
logic [5:0] cmd;
|
||||
|
||||
logic [47:0] rxcmd_buf;
|
||||
logic [31:0] rx_val;
|
||||
|
||||
logic [7:0] rxdata_buf [512];
|
||||
logic [8:0] data_count;
|
||||
|
||||
logic [15:0] data_crc;
|
||||
|
||||
|
||||
assign rx_val = rxcmd_buf[39:8];
|
||||
|
||||
always_comb begin
|
||||
data_out = 'x;
|
||||
|
||||
if (addr < 4'h4) begin
|
||||
data_out = rx_val[8 * addr +: 8];
|
||||
end else if (addr == 4'h4) begin
|
||||
data_out = {data_flag, read_flag};
|
||||
end else if (addr == 4'h5) begin
|
||||
data_out = rxdata_buf[data_count];
|
||||
end
|
||||
end
|
||||
|
||||
logic read_flag, next_read_flag;
|
||||
logic data_flag, next_data_flag;
|
||||
|
||||
typedef enum bit [2:0] {IDLE, LOAD, CRC, TXCMD, RXCMD, TXDATA, RXDATA, RXDCRC} macro_t;
|
||||
struct packed {
|
||||
macro_t macro;
|
||||
logic [8:0] count;
|
||||
logic [2:0] d_bit_count;
|
||||
} state, next_state;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
state.macro <= IDLE;
|
||||
state.count <= '0;
|
||||
state.d_bit_count <= '1;
|
||||
read_flag <= '0;
|
||||
data_flag <= '0;
|
||||
data_count <= '0;
|
||||
end else begin
|
||||
if (state.macro == TXCMD || state.macro == CRC) begin
|
||||
if (sd_clk) begin
|
||||
state <= next_state;
|
||||
end
|
||||
end else if (state.macro == RXCMD || state.macro == RXDATA || state.macro == RXDCRC) begin
|
||||
if (~sd_clk) begin
|
||||
state <= next_state;
|
||||
end
|
||||
end else begin
|
||||
state <= next_state;
|
||||
end
|
||||
end
|
||||
|
||||
if (sd_clk) begin
|
||||
read_flag <= next_read_flag;
|
||||
data_flag <= next_data_flag;
|
||||
end
|
||||
|
||||
if (cs & ~rw) begin
|
||||
if (addr < 4'h4) begin
|
||||
arg[8 * addr +: 8] <= data;
|
||||
end else if (addr == 4'h4) begin
|
||||
cmd <= data[6:0];
|
||||
end
|
||||
end
|
||||
|
||||
if (cs & addr == 4'h5 && sd_clk) begin
|
||||
data_count <= data_count + 8'b1;
|
||||
end
|
||||
|
||||
if (state.macro == RXCMD) begin
|
||||
rxcmd_buf[6'd46-state.count] <= i_sd_cmd; //we probabily missed bit 47
|
||||
end
|
||||
|
||||
if (state.macro == RXDATA && ~sd_clk) begin
|
||||
rxdata_buf[state.count][state.d_bit_count] <= i_sd_data;
|
||||
end
|
||||
|
||||
if (state.macro == RXDCRC && ~sd_clk) begin
|
||||
data_crc[4'd15-state.count] <= i_sd_data;
|
||||
data_count <= '0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
logic [6:0] crc;
|
||||
logic load_crc;
|
||||
logic crc_valid;
|
||||
logic [39:0] _packet;
|
||||
assign _packet = {1'b0, 1'b1, cmd, arg};
|
||||
logic [47:0] packet_crc;
|
||||
assign packet_crc = {_packet, crc, 1'b1};
|
||||
|
||||
crc7 u_crc7(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.load(load_crc),
|
||||
.data_in(_packet),
|
||||
.crc_out(crc),
|
||||
.valid(crc_valid)
|
||||
);
|
||||
|
||||
always_comb begin
|
||||
next_state = state;
|
||||
next_read_flag = read_flag;
|
||||
next_data_flag = data_flag;
|
||||
|
||||
case (state.macro)
|
||||
IDLE: begin
|
||||
if (~i_sd_cmd) begin // receive data if sd pulls cmd low
|
||||
next_state.macro = RXCMD;
|
||||
end
|
||||
|
||||
if (~i_sd_data) begin
|
||||
next_state.d_bit_count = '1;
|
||||
next_state.macro = RXDATA;
|
||||
end
|
||||
|
||||
if (addr == 4'h4 & cs & ~rw) begin // transmit if cpu writes to cmd
|
||||
next_state.macro = LOAD;
|
||||
end
|
||||
|
||||
if (addr == 4'h4 & cs & rw) begin
|
||||
next_read_flag = '0;
|
||||
end
|
||||
|
||||
if (addr == 4'h5 & cs) begin
|
||||
next_data_flag = '0;
|
||||
end
|
||||
end
|
||||
|
||||
LOAD: begin
|
||||
next_state.macro = CRC;
|
||||
end
|
||||
|
||||
CRC: begin
|
||||
next_state.macro = TXCMD;
|
||||
end
|
||||
|
||||
TXCMD: begin
|
||||
if (state.count < 47) begin
|
||||
next_state.count = state.count + 6'b1;
|
||||
end else begin
|
||||
next_state.macro = IDLE;
|
||||
next_state.count = '0;
|
||||
end
|
||||
end
|
||||
|
||||
RXCMD: begin
|
||||
if (state.count < 47) begin
|
||||
next_state.count = state.count + 6'b1;
|
||||
end else begin
|
||||
next_read_flag = '1;
|
||||
next_state.macro = IDLE;
|
||||
next_state.count = '0;
|
||||
end
|
||||
end
|
||||
|
||||
RXDATA: begin
|
||||
if (state.count < 511 || (state.count == 511 && state.d_bit_count > 0)) begin
|
||||
if (state.d_bit_count == 8'h0) begin
|
||||
next_state.count = state.count + 9'b1;
|
||||
end
|
||||
next_state.d_bit_count = state.d_bit_count - 3'h1;
|
||||
end else begin
|
||||
next_data_flag = '1;
|
||||
next_state.macro = RXDCRC;
|
||||
next_state.count = '0;
|
||||
end
|
||||
end
|
||||
|
||||
RXDCRC: begin
|
||||
if (state.count < 16) begin
|
||||
next_state.count = state.count + 9'b1;
|
||||
end else begin
|
||||
next_state.macro = IDLE;
|
||||
next_state.count = '0;
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
next_state.macro = IDLE;
|
||||
next_state.count = '0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
o_sd_cmd = '1; //default to 1
|
||||
o_sd_data = '1;
|
||||
|
||||
load_crc = '0;
|
||||
|
||||
case (state.macro)
|
||||
IDLE:;
|
||||
|
||||
CRC: begin
|
||||
load_crc = '1;
|
||||
end
|
||||
|
||||
TXCMD: begin
|
||||
o_sd_cmd = packet_crc[6'd47 - state.count];
|
||||
end
|
||||
|
||||
RXCMD:;
|
||||
|
||||
default:;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,68 +0,0 @@
|
||||
module sdram_adapter(
|
||||
input i_sysclk,
|
||||
input i_sdrclk,
|
||||
input i_tACclk,
|
||||
input i_pll_locked,
|
||||
output o_pll_reset,
|
||||
output o_sdr_CKE,
|
||||
output o_sdr_n_CS,
|
||||
output o_sdr_n_WE,
|
||||
output o_sdr_n_RAS,
|
||||
output o_sdr_n_CAS,
|
||||
output [1:0]o_sdr_BA,
|
||||
output [12:0]o_sdr_ADDR,
|
||||
input [15:0]i_sdr_DATA,
|
||||
output [15:0]o_sdr_DATA,
|
||||
output [15:0]o_sdr_DATA_oe,
|
||||
output [1:0]o_sdr_DQM
|
||||
);
|
||||
|
||||
sdram u_sdram (
|
||||
.i_arst (w_areset),
|
||||
.i_sysclk (w_sysclk),
|
||||
.i_sdrclk (i_sdrclk),
|
||||
.i_tACclk (i_tACclk),
|
||||
.i_pll_locked (1'b1),
|
||||
|
||||
.i_we (r_we_1P),
|
||||
.i_re (r_re_1P),
|
||||
.i_last (r_last_1P),
|
||||
.i_addr (r_addr_1P),
|
||||
.i_din (r_din_1P),
|
||||
.o_dout (w_dout),
|
||||
.o_sdr_state (w_sdr_state),
|
||||
.o_sdr_init_done (w_sdr_init_done),
|
||||
.o_wr_ack (w_wr_ack),
|
||||
.o_rd_ack (w_rd_ack),
|
||||
.o_ref_req (),
|
||||
.o_rd_valid (w_rd_valid),
|
||||
|
||||
.o_sdr_CKE (w_sdr_CKE),
|
||||
.o_sdr_n_CS (w_sdr_n_CS),
|
||||
.o_sdr_n_RAS (w_sdr_n_RAS),
|
||||
.o_sdr_n_CAS (w_sdr_n_CAS),
|
||||
.o_sdr_n_WE (w_sdr_n_WE),
|
||||
.o_sdr_BA (w_sdr_BA),
|
||||
.o_sdr_ADDR (w_sdr_ADDR),
|
||||
.o_sdr_DATA (w_sdr_DATA),
|
||||
.o_sdr_DATA_oe (w_sdr_DATA_oe),
|
||||
.i_sdr_DATA ({{16{1'b0}}, i_sdr_DATA}),
|
||||
.o_sdr_DQM (w_sdr_DQM),
|
||||
|
||||
.o_dbg_dly_cnt_b (w_dbg_dly_cnt_b),
|
||||
.o_dbg_tRCD_done (w_dbg_tRCD_done),
|
||||
.o_dbg_tRTW_done (w_dbg_tRTW_done),
|
||||
.o_dbg_ref_req (w_dbg_ref_req),
|
||||
.o_dbg_wr_ack (w_dbg_wr_ack),
|
||||
.o_dbg_rd_ack (w_dbg_rd_ack),
|
||||
.o_dbg_n_CS (w_dbg_n_CS),
|
||||
.o_dbg_n_RAS (w_dbg_n_RAS),
|
||||
.o_dbg_n_CAS (w_dbg_n_CAS),
|
||||
.o_dbg_n_WE (w_dbg_n_WE),
|
||||
.o_dbg_BA (w_dbg_BA),
|
||||
.o_dbg_ADDR (w_dbg_ADDR),
|
||||
.o_dbg_DATA_out (w_dbg_DATA_out),
|
||||
.o_dbg_DATA_in (w_dbg_DATA_in)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -1,275 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2021.2.323.4.6" db_version="20212999" last_change_date="Sat Jun 11 18:46:25 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
|
||||
<efxpt:device_info>
|
||||
<efxpt:iobank_info>
|
||||
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="1B_1C" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="1D_1E" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="3A_3B_3C" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="3D_3E" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="4A" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="4B" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="BR" iostd="1.2 V"/>
|
||||
<efxpt:iobank name="TL" iostd="1.2 V"/>
|
||||
<efxpt:iobank name="TR" iostd="1.2 V"/>
|
||||
</efxpt:iobank_info>
|
||||
<efxpt:ctrl_info>
|
||||
<efxpt:ctrl name="cfg" ctrl_def="CONFIG_CTRL0" clock_name="" is_clk_invert="false" cbsel_bus_name="cfg_CBSEL" config_ctrl_name="cfg_CONFIG" ena_capture_name="cfg_ENA" error_status_name="cfg_ERROR" um_signal_status_name="cfg_USR_STATUS" is_remote_update_enable="false" is_user_mode_enable="false"/>
|
||||
</efxpt:ctrl_info>
|
||||
</efxpt:device_info>
|
||||
<efxpt:gpio_info device_def="T20F256">
|
||||
<efxpt:gpio name="i_BRPLL_clkin" gpio_def="GPIOR_157" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_BRPLL_clkin" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="i_sw2" gpio_def="GPIOL_02" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sw2" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="i_sw3" gpio_def="GPIOL_04" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sw3" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[0]" gpio_def="GPIOR_92" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[0]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[0]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[10]" gpio_def="GPIOR_116" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[10]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[10]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[10]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[11]" gpio_def="GPIOR_108" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[11]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[11]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[11]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[12]" gpio_def="GPIOR_112" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[12]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[12]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[12]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[13]" gpio_def="GPIOR_106" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[13]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[13]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[13]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[14]" gpio_def="GPIOR_98" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[14]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[14]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[14]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[15]" gpio_def="GPIOR_94" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[15]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[15]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[15]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[1]" gpio_def="GPIOR_90" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[1]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[1]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[2]" gpio_def="GPIOR_97" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[2]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[2]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[2]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[3]" gpio_def="GPIOR_95" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[3]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[3]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[3]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[4]" gpio_def="GPIOR_93" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[4]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[4]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[4]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[5]" gpio_def="GPIOR_83" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[5]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[5]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[5]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[6]" gpio_def="GPIOR_84" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[6]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[6]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[6]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[7]" gpio_def="GPIOR_82" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[7]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[7]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[7]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[8]" gpio_def="GPIOR_136" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[8]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[8]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[8]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[9]" gpio_def="GPIOR_119" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[9]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[9]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[9]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[0]" gpio_def="GPIOL_11" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[0]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[10]" gpio_def="GPIOL_16" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[10]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[11]" gpio_def="GPIOL_37" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[11]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[12]" gpio_def="GPIOL_18" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[12]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[13]" gpio_def="GPIOL_36" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[13]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[14]" gpio_def="GPIOL_19" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[14]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[15]" gpio_def="GPIOL_35" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[15]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[1]" gpio_def="GPIOL_43" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[1]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[2]" gpio_def="GPIOL_12" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[2]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[3]" gpio_def="GPIOL_42" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[3]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[4]" gpio_def="GPIOL_13" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[4]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[5]" gpio_def="GPIOL_41" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[5]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[6]" gpio_def="GPIOL_14" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[6]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[7]" gpio_def="GPIOL_40" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[7]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[8]" gpio_def="GPIOL_15" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[8]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg[9]" gpio_def="GPIOL_39" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_dbg[9]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg_sdr_CK" gpio_def="GPIOR_76" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_dbg_sdr_CKn" gpio_def="GPIOR_78" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="i_sdrclk" is_clock_inverted="true" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_led[0]" gpio_def="GPIOR_104" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_led[0]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_led[1]" gpio_def="GPIOR_105" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_led[1]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_led[2]" gpio_def="GPIOR_117" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_led[2]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_led[3]" gpio_def="GPIOR_118" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_led[3]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_led[4]" gpio_def="GPIOR_153" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_led[4]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_led[5]" gpio_def="GPIOR_154" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_led[5]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_led[6]" gpio_def="GPIOR_155" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_led[6]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_led[7]" gpio_def="GPIOR_156" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_led[7]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[0]" gpio_def="GPIOR_85" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[10]" gpio_def="GPIOR_89" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[10]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[11]" gpio_def="GPIOR_143" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[11]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[12]" gpio_def="GPIOR_144" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[12]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[1]" gpio_def="GPIOR_87" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[2]" gpio_def="GPIOR_86" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[2]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[3]" gpio_def="GPIOR_88" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[3]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[4]" gpio_def="GPIOR_133" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[4]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[5]" gpio_def="GPIOR_135" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[5]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[6]" gpio_def="GPIOR_131" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[6]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[7]" gpio_def="GPIOR_148" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[7]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[8]" gpio_def="GPIOR_138" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[8]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[9]" gpio_def="GPIOR_147" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[9]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_BA[0]" gpio_def="GPIOR_102" mode="output" bus_name="o_sdr_BA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_BA[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_BA[1]" gpio_def="GPIOR_99" mode="output" bus_name="o_sdr_BA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_BA[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_CK" gpio_def="GPIOR_146" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="i_sdrclk" is_clock_inverted="true" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_CKE" gpio_def="GPIOR_145" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_CKE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_DQM[0]" gpio_def="GPIOR_80" mode="output" bus_name="o_sdr_DQM" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_DQM[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_DQM[1]" gpio_def="GPIOR_132" mode="output" bus_name="o_sdr_DQM" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_DQM[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_n_CAS" gpio_def="GPIOR_139" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_n_CAS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="2"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_n_CS" gpio_def="GPIOR_103" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_n_CS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_n_RAS" gpio_def="GPIOR_91" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_n_RAS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_n_WE" gpio_def="GPIOR_141" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_n_WE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:global_unused_config state="input with weak pullup"/>
|
||||
<efxpt:bus name="io_sdr_DATA" mode="inout" msb="15" lsb="0"/>
|
||||
<efxpt:bus name="o_dbg" mode="output" msb="15" lsb="0"/>
|
||||
<efxpt:bus name="o_led" mode="output" msb="7" lsb="0"/>
|
||||
<efxpt:bus name="o_sdr_ADDR" mode="output" msb="12" lsb="0"/>
|
||||
<efxpt:bus name="o_sdr_BA" mode="output" msb="1" lsb="0"/>
|
||||
<efxpt:bus name="o_sdr_DQM" mode="output" msb="1" lsb="0"/>
|
||||
</efxpt:gpio_info>
|
||||
<efxpt:pll_info>
|
||||
<efxpt:pll name="pll_inst1" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.00" multiplier="8" pre_divider="4" post_divider="2" reset_name="o_pll_reset" locked_name="i_pll_locked" is_ipfrz="false" is_bypass_lock="true">
|
||||
<efxpt:output_clock name="i_sdrclk" number="0" out_divider="2" adv_out_phase_shift="0"/>
|
||||
<efxpt:output_clock name="i_tACclk" number="1" out_divider="2" adv_out_phase_shift="0"/>
|
||||
<efxpt:output_clock name="i_sysclk" number="2" out_divider="4" adv_out_phase_shift="0"/>
|
||||
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="2" clksel_name="" feedback_clock_name="i_sysclk" feedback_mode="core"/>
|
||||
</efxpt:pll>
|
||||
</efxpt:pll_info>
|
||||
<efxpt:lvds_info/>
|
||||
<efxpt:jtag_info/>
|
||||
</efxpt:design_db>
|
||||
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2021.2.323.4.6" db_version="20212999" last_change_date="Sat Jun 11 19:20:20 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
|
||||
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2021.2.323.4.6" db_version="20212999" last_change_date="Tue Nov 1 18:31:26 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
|
||||
<efxpt:device_info>
|
||||
<efxpt:iobank_info>
|
||||
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
@@ -18,177 +18,130 @@
|
||||
</efxpt:ctrl_info>
|
||||
</efxpt:device_info>
|
||||
<efxpt:gpio_info device_def="T20F256">
|
||||
<efxpt:gpio name="gpio_inst41" gpio_def="" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="gpio_inst41" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:gpio name="button_reset" gpio_def="GPIOL_02" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="button_reset" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="i_BRPLL_clkin" gpio_def="GPIOR_157" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_BRPLL_clkin" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:gpio name="cpu_addr[0]" gpio_def="GPIOL_65" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[0]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[0]" gpio_def="GPIOR_92" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[0]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[0]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[10]" gpio_def="GPIOL_46" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[10]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[10]" gpio_def="GPIOR_116" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[10]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[10]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[10]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[11]" gpio_def="GPIOL_44" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[11]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[11]" gpio_def="GPIOR_108" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[11]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[11]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[11]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[12]" gpio_def="GPIOL_45" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[12]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[12]" gpio_def="GPIOR_112" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[12]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[12]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[12]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[13]" gpio_def="GPIOL_47" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[13]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[13]" gpio_def="GPIOR_106" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[13]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[13]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[13]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[14]" gpio_def="GPIOL_49" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[14]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[14]" gpio_def="GPIOR_98" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[14]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[14]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[14]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[15]" gpio_def="GPIOL_51" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[15]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[15]" gpio_def="GPIOR_94" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[15]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[15]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[15]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[1]" gpio_def="GPIOL_63" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[1]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[1]" gpio_def="GPIOR_90" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[1]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[1]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[2]" gpio_def="GPIOL_62" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[2]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[2]" gpio_def="GPIOR_97" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[2]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[2]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[2]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[3]" gpio_def="GPIOL_60" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[3]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[3]" gpio_def="GPIOR_95" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[3]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[3]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[3]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[4]" gpio_def="GPIOL_58" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[4]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[4]" gpio_def="GPIOR_93" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[4]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[4]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[4]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[5]" gpio_def="GPIOL_56" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[5]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[5]" gpio_def="GPIOR_83" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[5]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[5]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[5]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[6]" gpio_def="GPIOL_54" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[6]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[6]" gpio_def="GPIOR_84" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[6]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[6]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[6]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[7]" gpio_def="GPIOL_52" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[7]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[7]" gpio_def="GPIOR_82" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[7]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[7]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[7]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[8]" gpio_def="GPIOL_50" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[8]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[8]" gpio_def="GPIOR_136" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[8]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[8]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[8]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_addr[9]" gpio_def="GPIOL_48" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_addr[9]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="io_sdr_DATA[9]" gpio_def="GPIOR_119" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="i_sdr_DATA[9]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="o_sdr_DATA[9]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="o_sdr_DATA_oe[9]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
|
||||
<efxpt:gpio name="cpu_clk" gpio_def="GPIOL_71" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="clk_2" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[0]" gpio_def="GPIOR_85" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_data[0]" gpio_def="GPIOL_68" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="cpu_data_in[0]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="cpu_data_out[0]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="cpu_data_oe[0]" is_register="false" clock_name="" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[10]" gpio_def="GPIOR_89" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[10]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_data[1]" gpio_def="GPIOL_66" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="cpu_data_in[1]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="cpu_data_out[1]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="cpu_data_oe[1]" is_register="false" clock_name="" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[11]" gpio_def="GPIOR_143" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[11]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_data[2]" gpio_def="GPIOL_64" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="cpu_data_in[2]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="cpu_data_out[2]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="cpu_data_oe[2]" is_register="false" clock_name="" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[12]" gpio_def="GPIOR_144" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[12]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_data[3]" gpio_def="GPIOL_61" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="cpu_data_in[3]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="cpu_data_out[3]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="cpu_data_oe[3]" is_register="false" clock_name="" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[1]" gpio_def="GPIOR_87" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_data[4]" gpio_def="GPIOL_59" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="cpu_data_in[4]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="cpu_data_out[4]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="cpu_data_oe[4]" is_register="false" clock_name="" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[2]" gpio_def="GPIOR_86" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[2]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_data[5]" gpio_def="GPIOL_57" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="cpu_data_in[5]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="cpu_data_out[5]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="cpu_data_oe[5]" is_register="false" clock_name="" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[3]" gpio_def="GPIOR_88" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[3]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_data[6]" gpio_def="GPIOL_55" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="cpu_data_in[6]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="cpu_data_out[6]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="cpu_data_oe[6]" is_register="false" clock_name="" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[4]" gpio_def="GPIOR_133" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[4]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_data[7]" gpio_def="GPIOL_53" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="cpu_data_in[7]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
<efxpt:output_config name="cpu_data_out[7]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:output_enable_config name="cpu_data_oe[7]" is_register="false" clock_name="" is_clock_inverted="false"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[5]" gpio_def="GPIOR_135" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[5]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_irqb" gpio_def="GPIOL_72" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_irqb" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[6]" gpio_def="GPIOR_131" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[6]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_nmib" gpio_def="GPIOL_69" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_nmib" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[7]" gpio_def="GPIOR_148" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[7]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_rdy" gpio_def="GPIOL_74" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_rdy" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[8]" gpio_def="GPIOR_138" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[8]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_resb" gpio_def="GPIOL_73" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="cpu_resb" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_ADDR[9]" gpio_def="GPIOR_147" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_ADDR[9]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_rwb" gpio_def="GPIOL_70" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="cpu_rwb" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_BA[0]" gpio_def="GPIOR_102" mode="output" bus_name="o_sdr_BA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_BA[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="cpu_sync" gpio_def="GPIOL_67" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="cpu_sync" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_BA[1]" gpio_def="GPIOR_99" mode="output" bus_name="o_sdr_BA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_BA[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_CK" gpio_def="GPIOR_146" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="i_sdrclk" is_clock_inverted="true" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_CKE" gpio_def="GPIOR_145" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_CKE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_DQM[0]" gpio_def="GPIOR_80" mode="output" bus_name="o_sdr_DQM" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_DQM[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_DQM[1]" gpio_def="GPIOR_132" mode="output" bus_name="o_sdr_DQM" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_DQM[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_n_CAS" gpio_def="GPIOR_139" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_n_CAS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="2"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_n_CS" gpio_def="GPIOR_103" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_n_CS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_n_RAS" gpio_def="GPIOR_91" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_n_RAS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:gpio name="o_sdr_n_WE" gpio_def="GPIOR_141" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:output_config name="o_sdr_n_WE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
|
||||
<efxpt:gpio name="pll_in" gpio_def="GPIOR_157" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
|
||||
<efxpt:input_config name="pll_in" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
|
||||
</efxpt:gpio>
|
||||
<efxpt:global_unused_config state="input with weak pullup"/>
|
||||
<efxpt:bus name="io_sdr_DATA" mode="inout" msb="15" lsb="0"/>
|
||||
<efxpt:bus name="o_sdr_ADDR" mode="output" msb="12" lsb="0"/>
|
||||
<efxpt:bus name="o_sdr_BA" mode="output" msb="1" lsb="0"/>
|
||||
<efxpt:bus name="o_sdr_DQM" mode="output" msb="1" lsb="0"/>
|
||||
<efxpt:bus name="cpu_data" mode="inout" msb="7" lsb="0"/>
|
||||
<efxpt:bus name="cpu_addr" mode="output" msb="15" lsb="0"/>
|
||||
</efxpt:gpio_info>
|
||||
<efxpt:pll_info>
|
||||
<efxpt:pll name="sdram_pll" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.00" multiplier="2" pre_divider="1" post_divider="8" reset_name="o_pll_reset" locked_name="i_pll_locked" is_ipfrz="false" is_bypass_lock="true">
|
||||
<efxpt:output_clock name="i_sdrclk" number="0" out_divider="1" adv_out_phase_shift="0"/>
|
||||
<efxpt:output_clock name="i_tACclk" number="1" out_divider="1" adv_out_phase_shift="0"/>
|
||||
<efxpt:output_clock name="i_sysclk" number="2" out_divider="2" adv_out_phase_shift="0"/>
|
||||
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="i_sysclk" feedback_mode="core"/>
|
||||
</efxpt:pll>
|
||||
<efxpt:pll name="cpu_clk_pll" pll_def="PLL_TL0" ref_clock_name="i_BRPLL_clkin" ref_clock_freq="100.00" multiplier="32" pre_divider="2" post_divider="8" reset_name="" locked_name="" is_ipfrz="false" is_bypass_lock="true">
|
||||
<efxpt:output_clock name="cpu_clk_pll_CLKOUT0" number="0" out_divider="25" adv_out_phase_shift="0"/>
|
||||
<efxpt:adv_prop ref_clock_mode="core" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
|
||||
<efxpt:pll name="pll_cpu_clk" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.00" multiplier="16" pre_divider="1" post_divider="8" reset_name="pll_cpu_reset" locked_name="pll_cpu_locked" is_ipfrz="false" is_bypass_lock="true">
|
||||
<efxpt:output_clock name="clk_50" number="0" out_divider="2" adv_out_phase_shift="0"/>
|
||||
<efxpt:output_clock name="clk_2" number="1" out_divider="50" adv_out_phase_shift="0"/>
|
||||
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
|
||||
</efxpt:pll>
|
||||
</efxpt:pll_info>
|
||||
<efxpt:lvds_info/>
|
||||
|
||||
114
hw/efinix_fpga/super6502.pt.sdc
Normal file
114
hw/efinix_fpga/super6502.pt.sdc
Normal file
@@ -0,0 +1,114 @@
|
||||
|
||||
# Efinity Interface Designer SDC
|
||||
# Version: 2021.2.323.4.6
|
||||
# Date: 2022-11-01 18:17
|
||||
|
||||
# Copyright (C) 2017 - 2021 Efinix Inc. All rights reserved.
|
||||
|
||||
# Device: T20F256
|
||||
# Project: super6502
|
||||
# Timing Model: C4 (final)
|
||||
|
||||
# PLL Constraints
|
||||
#################
|
||||
create_clock -period 20.00 clk_50
|
||||
create_clock -period 500.00 clk_2
|
||||
|
||||
# GPIO Constraints
|
||||
####################
|
||||
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {button_reset}]
|
||||
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {button_reset}]
|
||||
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_sync}]
|
||||
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_sync}]
|
||||
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {pll_in}]
|
||||
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {pll_in}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[0]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[0]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[1]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[1]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[2]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[2]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[3]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[3]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[4]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[4]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[5]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[5]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[6]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[6]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[7]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[7]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[8]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[8]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[9]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[9]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[10]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[10]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[11]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[11]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[12]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[12]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[13]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[13]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[14]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[14]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[15]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[15]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_irqb}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_irqb}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_nmib}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_nmib}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_rdy}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_rdy}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_resb}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_resb}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_rwb}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_rwb}]
|
||||
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[0]}]
|
||||
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[0]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[0]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[0]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[0]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[0]}]
|
||||
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[1]}]
|
||||
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[1]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[1]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[1]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[1]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[1]}]
|
||||
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[2]}]
|
||||
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[2]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[2]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[2]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[2]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[2]}]
|
||||
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[3]}]
|
||||
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[3]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[3]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[3]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[3]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[3]}]
|
||||
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[4]}]
|
||||
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[4]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[4]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[4]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[4]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[4]}]
|
||||
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[5]}]
|
||||
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[5]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[5]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[5]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[5]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[5]}]
|
||||
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[6]}]
|
||||
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[6]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[6]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[6]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[6]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[6]}]
|
||||
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[7]}]
|
||||
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[7]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[7]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[7]}]
|
||||
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[7]}]
|
||||
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[7]}]
|
||||
@@ -1,256 +1,39 @@
|
||||
module super6502
|
||||
(
|
||||
input [7:0] cpu_data_in,
|
||||
input cpu_sync,
|
||||
input pll_in,
|
||||
input button_reset,
|
||||
input pll_cpu_locked,
|
||||
input clk_50,
|
||||
input clk_2,
|
||||
output logic [15:0] cpu_addr,
|
||||
output logic [7:0] cpu_data_out,
|
||||
output logic [7:0] cpu_data_oe,
|
||||
output logic cpu_irqb,
|
||||
output logic cpu_nmib,
|
||||
output logic cpu_rdy,
|
||||
output logic cpu_resb,
|
||||
output logic cpu_rwb,
|
||||
output logic pll_cpu_reset
|
||||
);
|
||||
|
||||
module super6502(
|
||||
input clk_50,
|
||||
input pll_inst1_CLKOUT0,
|
||||
input logic rst_n,
|
||||
input logic button_1,
|
||||
|
||||
input logic [15:0] cpu_addr,
|
||||
inout logic [7:0] cpu_data,
|
||||
|
||||
input logic cpu_vpb,
|
||||
input logic cpu_mlb,
|
||||
input logic cpu_rwb,
|
||||
input logic cpu_sync,
|
||||
|
||||
output logic cpu_led,
|
||||
output logic cpu_resb,
|
||||
output logic cpu_rdy,
|
||||
output logic cpu_sob,
|
||||
output logic cpu_irqb,
|
||||
output logic cpu_phi2,
|
||||
output logic cpu_be,
|
||||
output logic cpu_nmib,
|
||||
|
||||
output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
|
||||
|
||||
input logic UART_RXD,
|
||||
output logic UART_TXD,
|
||||
|
||||
input [7:0] SW,
|
||||
output logic [7:0] LED,
|
||||
|
||||
inout logic [15: 2] ARDUINO_IO,
|
||||
|
||||
///////// SDRAM /////////
|
||||
output DRAM_CLK,
|
||||
output DRAM_CKE,
|
||||
output [12: 0] DRAM_ADDR,
|
||||
output [ 1: 0] DRAM_BA,
|
||||
inout [15: 0] DRAM_DQ,
|
||||
output DRAM_LDQM,
|
||||
output DRAM_UDQM,
|
||||
output DRAM_CS_N,
|
||||
output DRAM_WE_N,
|
||||
output DRAM_CAS_N,
|
||||
output DRAM_RAS_N
|
||||
);
|
||||
|
||||
logic rst;
|
||||
assign rst = ~rst_n;
|
||||
|
||||
logic clk;
|
||||
|
||||
logic [7:0] cpu_data_in;
|
||||
assign cpu_data_in = cpu_data;
|
||||
|
||||
logic [7:0] cpu_data_out;
|
||||
assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
|
||||
|
||||
logic o_sd_cmd, i_sd_cmd;
|
||||
logic o_sd_data, i_sd_data;
|
||||
|
||||
assign ARDUINO_IO[11] = o_sd_cmd ? 1'bz : 1'b0;
|
||||
assign ARDUINO_IO[12] = o_sd_data ? 1'bz : 1'b0;
|
||||
assign ARDUINO_IO[13] = cpu_phi2;
|
||||
assign ARDUINO_IO[6] = 1'b1;
|
||||
|
||||
assign i_sd_cmd = ARDUINO_IO[11];
|
||||
assign i_sd_data = ARDUINO_IO[12];
|
||||
|
||||
logic [7:0] rom_data_out;
|
||||
logic [7:0] sdram_data_out;
|
||||
logic [7:0] uart_data_out;
|
||||
logic [7:0] irq_data_out;
|
||||
logic [7:0] board_io_data_out;
|
||||
logic [7:0] mm_data_out;
|
||||
logic [7:0] sd_data_out;
|
||||
|
||||
logic sdram_cs;
|
||||
logic rom_cs;
|
||||
logic hex_cs;
|
||||
logic uart_cs;
|
||||
logic irq_cs;
|
||||
logic board_io_cs;
|
||||
logic mm_cs1;
|
||||
logic mm_cs2;
|
||||
logic sd_cs;
|
||||
|
||||
assign clk = pll_inst1_CLKOUT0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
cpu_phi2 <= ~cpu_phi2;
|
||||
end
|
||||
assign pll_cpu_reset = '1;
|
||||
|
||||
assign cpu_data_oe = '0;
|
||||
assign cpu_rdy = '1;
|
||||
assign cpu_sob = '0;
|
||||
assign cpu_resb = rst_n;
|
||||
assign cpu_be = '1;
|
||||
assign cpu_irqb = '1;
|
||||
assign cpu_nmib = '1;
|
||||
assign cpu_irqb = irq_data_out == 0;
|
||||
|
||||
logic [11:0] mm_MO;
|
||||
|
||||
logic [23:0] mm_addr;
|
||||
assign mm_addr = {mm_MO, cpu_addr[11:0]};
|
||||
|
||||
memory_mapper memory_mapper(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.rw(cpu_rwb),
|
||||
.cs(mm_cs1),
|
||||
.MM_cs(mm_cs2),
|
||||
.RS(cpu_addr[3:0]),
|
||||
.MA(cpu_addr[15:12]),
|
||||
.data_in(cpu_data_in),
|
||||
.data_out(mm_data_out),
|
||||
.MO(mm_MO)
|
||||
);
|
||||
|
||||
addr_decode decode(
|
||||
.addr(mm_addr),
|
||||
.sdram_cs(sdram_cs),
|
||||
.rom_cs(rom_cs),
|
||||
.hex_cs(hex_cs),
|
||||
.uart_cs(uart_cs),
|
||||
.irq_cs(irq_cs),
|
||||
.board_io_cs(board_io_cs),
|
||||
.mm_cs1(mm_cs1),
|
||||
.mm_cs2(mm_cs2),
|
||||
.sd_cs(sd_cs)
|
||||
);
|
||||
|
||||
|
||||
always_comb begin
|
||||
if (sdram_cs)
|
||||
cpu_data_out = sdram_data_out;
|
||||
else if (rom_cs)
|
||||
cpu_data_out = rom_data_out;
|
||||
else if (uart_cs)
|
||||
cpu_data_out = uart_data_out;
|
||||
else if (irq_cs)
|
||||
cpu_data_out = irq_data_out;
|
||||
else if (board_io_cs)
|
||||
cpu_data_out = board_io_data_out;
|
||||
else if (mm_cs1)
|
||||
cpu_data_out = mm_data_out;
|
||||
else if (sd_cs)
|
||||
cpu_data_out = sd_data_out;
|
||||
else
|
||||
cpu_data_out = 'x;
|
||||
end
|
||||
|
||||
|
||||
sdram_adapter u_sdram_adapter(
|
||||
.rst(rst),
|
||||
.clk_50(clk_50),
|
||||
.cpu_clk(cpu_phi2),
|
||||
.addr(mm_addr),
|
||||
.sdram_cs(sdram_cs),
|
||||
.rwb(cpu_rwb),
|
||||
.data_in(cpu_data_in),
|
||||
.data_out(sdram_data_out),
|
||||
|
||||
//SDRAM
|
||||
.DRAM_CLK(DRAM_CLK), //clk_sdram.clk
|
||||
.DRAM_ADDR(DRAM_ADDR), //sdram_wire.addr
|
||||
.DRAM_BA(DRAM_BA), //.ba
|
||||
.DRAM_CAS_N(DRAM_CAS_N), //.cas_n
|
||||
.DRAM_CKE(DRAM_CKE), //.cke
|
||||
.DRAM_CS_N(DRAM_CS_N), //.cs_n
|
||||
.DRAM_DQ(DRAM_DQ), //.dq
|
||||
.DRAM_UDQM(DRAM_UDQM), //.dqm
|
||||
.DRAM_LDQM(DRAM_LDQM),
|
||||
.DRAM_RAS_N(DRAM_RAS_N), //.ras_n
|
||||
.DRAM_WE_N(DRAM_WE_N) //.we_n
|
||||
);
|
||||
|
||||
|
||||
rom boot_rom(
|
||||
.address(cpu_addr[14:0]),
|
||||
.clock(clk),
|
||||
.q(rom_data_out)
|
||||
);
|
||||
|
||||
SevenSeg segs(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.rw(cpu_rwb),
|
||||
.data(cpu_data_in),
|
||||
.cs(hex_cs),
|
||||
.addr(cpu_addr[1:0]),
|
||||
.HEX0(HEX0), .HEX1(HEX1), .HEX2(HEX2), .HEX3(HEX3), .HEX4(HEX4), .HEX5(HEX5)
|
||||
);
|
||||
|
||||
board_io board_io(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.rw(cpu_rwb),
|
||||
.data_in(cpu_data_in),
|
||||
.data_out(board_io_data_out),
|
||||
.cs(board_io_cs),
|
||||
.led(LED),
|
||||
.sw(SW)
|
||||
);
|
||||
|
||||
logic uart_irq;
|
||||
|
||||
uart uart(
|
||||
.clk_50(clk_50),
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.rw(cpu_rwb),
|
||||
.data_in(cpu_data_in),
|
||||
.cs(uart_cs),
|
||||
.addr(cpu_addr[1:0]),
|
||||
.RXD(UART_RXD),
|
||||
.TXD(UART_TXD),
|
||||
.irq(uart_irq),
|
||||
.data_out(uart_data_out)
|
||||
);
|
||||
|
||||
sd_controller sd_controller(
|
||||
.clk(clk),
|
||||
.sd_clk(cpu_phi2),
|
||||
.rst(rst),
|
||||
.addr(cpu_addr[2:0]),
|
||||
.data(cpu_data_in),
|
||||
.cs(sd_cs),
|
||||
.rw(cpu_rwb),
|
||||
|
||||
.i_sd_cmd(i_sd_cmd),
|
||||
.o_sd_cmd(o_sd_cmd),
|
||||
|
||||
.i_sd_data(i_sd_data),
|
||||
.o_sd_data(o_sd_data),
|
||||
|
||||
.data_out(sd_data_out)
|
||||
);
|
||||
|
||||
always_ff @(posedge clk_50) begin
|
||||
if (rst)
|
||||
irq_data_out <= '0;
|
||||
else if (irq_cs && ~cpu_rwb)
|
||||
irq_data_out <= irq_data_out & cpu_data_in;
|
||||
|
||||
always @(posedge clk_2) begin
|
||||
if (button_reset == '0) begin
|
||||
cpu_resb <= '0;
|
||||
end
|
||||
else begin
|
||||
if (~button_1)
|
||||
irq_data_out[0] <= '1;
|
||||
if (uart_irq)
|
||||
irq_data_out[1] <= '1;
|
||||
if (cpu_resb == '0) begin
|
||||
cpu_resb <= '1;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -1,35 +1,22 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<efx:project name="super6502" description="" last_change_date="Wed August 17 2022 12:17:48" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2021.2.323.4.6" last_run_state="fail" last_run_tool="efx_map" last_run_flow="syn" config_result_in_sync="true" design_ood="" place_ood="" route_ood="" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
|
||||
<efx:project name="super6502" description="" last_change_date="Tue November 1 2022 18:28:14" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2021.2.323.4.6" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
|
||||
<efx:device_info>
|
||||
<efx:family name="Trion"/>
|
||||
<efx:device name="T20F256"/>
|
||||
<efx:timing_model name="C3"/>
|
||||
<efx:timing_model name="C4"/>
|
||||
</efx:device_info>
|
||||
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
|
||||
<efx:top_module name="super6502"/>
|
||||
<efx:top_module name=""/>
|
||||
<efx:design_file name="super6502.sv" version="default" library="default"/>
|
||||
<efx:design_file name="crc7.sv" version="default" library="default"/>
|
||||
<efx:design_file name="memory_mapper.sv" version="default" library="default"/>
|
||||
<efx:design_file name="uart.sv" version="default" library="default"/>
|
||||
<efx:design_file name="HexDriver.sv" version="default" library="default"/>
|
||||
<efx:design_file name="addr_decode.sv" version="default" library="default"/>
|
||||
<efx:design_file name="board_io.sv" version="default" library="default"/>
|
||||
<efx:design_file name="SevenSeg.sv" version="default" library="default"/>
|
||||
<efx:design_file name="sd_controller.sv" version="default" library="default"/>
|
||||
<efx:design_file name="sdram_adapter.sv" version="default" library="default"/>
|
||||
<efx:top_vhdl_arch name=""/>
|
||||
</efx:design_info>
|
||||
<efx:constraint_info>
|
||||
<efx:sdc_file name=""/>
|
||||
<efx:sdc_file name="super6502.pt.sdc"/>
|
||||
<efx:inter_file name=""/>
|
||||
</efx:constraint_info>
|
||||
<efx:sim_info/>
|
||||
<efx:misc_info/>
|
||||
<efx:ip_info>
|
||||
<efx:ip instance_name="sdram" path="ip/sdram/settings.json">
|
||||
<efx:ip_src_file name="sdram.v"/>
|
||||
</efx:ip>
|
||||
</efx:ip_info>
|
||||
<efx:ip_info/>
|
||||
<efx:synthesis tool_name="efx_map">
|
||||
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
|
||||
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
|
||||
@@ -47,7 +34,6 @@
|
||||
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
|
||||
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
|
||||
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
|
||||
<efx:param name="include" value="ip/sdram" value_type="e_string"/>
|
||||
</efx:synthesis>
|
||||
<efx:place_and_route tool_name="efx_pnr">
|
||||
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
|
||||
@@ -77,7 +63,7 @@
|
||||
</efx:bitstream_generation>
|
||||
<efx:debugger>
|
||||
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
|
||||
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
|
||||
<efx:param name="profile" value="NONE" value_type="e_string"/>
|
||||
<efx:param name="auto_instantiation" value="on" value_type="e_bool"/>
|
||||
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
|
||||
</efx:debugger>
|
||||
</efx:project>
|
||||
|
||||
@@ -1,228 +0,0 @@
|
||||
module uart(
|
||||
input clk_50,
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input cs,
|
||||
input rw,
|
||||
input [7:0] data_in,
|
||||
input [1:0] addr,
|
||||
|
||||
input RXD,
|
||||
|
||||
output logic TXD,
|
||||
|
||||
output logic irq,
|
||||
output logic [7:0] data_out
|
||||
);
|
||||
|
||||
//Handle reading and writing registers
|
||||
|
||||
logic [7:0] tx_buf;
|
||||
logic [7:0] rx_buf;
|
||||
logic [7:0] status;
|
||||
|
||||
logic tx_flag;
|
||||
logic rx_flag;
|
||||
|
||||
logic tx_flag_set;
|
||||
logic tx_flag_clear;
|
||||
logic rx_flag_set;
|
||||
logic rx_flag_clear;
|
||||
|
||||
assign status[0] = tx_flag | tx_flag_clear;
|
||||
assign status[1] = rx_flag | rx_flag_set;
|
||||
|
||||
assign irq = status[1];
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
tx_flag_set <= '0;
|
||||
rx_flag_clear <= '0;
|
||||
tx_buf <= '0;
|
||||
status[7:2] <= '0;
|
||||
end
|
||||
|
||||
if (cs) begin
|
||||
if (~rw) begin
|
||||
if (addr == 0)
|
||||
tx_buf <= data_in;
|
||||
end else begin
|
||||
if (addr == 0)
|
||||
data_out <= rx_buf;
|
||||
if (addr == 1)
|
||||
data_out <= status;
|
||||
end
|
||||
end
|
||||
|
||||
if (~rw & cs && addr == 0)
|
||||
tx_flag_set <= '1;
|
||||
else
|
||||
tx_flag_set <= '0;
|
||||
|
||||
if (rw & cs && addr == 0)
|
||||
rx_flag_clear <= '1;
|
||||
else
|
||||
rx_flag_clear <= '0;
|
||||
end
|
||||
|
||||
// tx state controller
|
||||
typedef enum bit [2:0] {START, DATA, PARITY, STOP, IDLE} macro_t;
|
||||
struct packed {
|
||||
macro_t macro;
|
||||
logic [3:0] count;
|
||||
} tx_state, tx_next_state, rx_state, rx_next_state;
|
||||
localparam logic [3:0] maxcount = 4'h7;
|
||||
|
||||
// baud rate: 9600
|
||||
localparam baud = 9600;
|
||||
localparam count = (50000000/baud)-1;
|
||||
logic [14:0] tx_clkdiv;
|
||||
|
||||
always_ff @(posedge clk_50) begin
|
||||
if (rst) begin
|
||||
tx_clkdiv <= 0;
|
||||
tx_state.macro <= IDLE;
|
||||
tx_state.count <= 3'b0;
|
||||
tx_flag <= '0;
|
||||
end else begin
|
||||
if (tx_flag_set)
|
||||
tx_flag <= '1;
|
||||
else if (tx_flag_clear)
|
||||
tx_flag <= '0;
|
||||
|
||||
if (tx_clkdiv == count) begin
|
||||
tx_clkdiv <= 0;
|
||||
tx_state <= tx_next_state;
|
||||
end else begin
|
||||
tx_clkdiv <= tx_clkdiv + 15'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
tx_next_state = tx_state;
|
||||
|
||||
unique case (tx_state.macro)
|
||||
START: begin
|
||||
tx_next_state.macro = DATA;
|
||||
tx_next_state.count = 3'b0;
|
||||
end
|
||||
DATA: begin
|
||||
if (tx_state.count == maxcount) begin
|
||||
tx_next_state.macro = STOP; // or PARITY
|
||||
tx_next_state.count = 3'b0;
|
||||
end else begin
|
||||
tx_next_state.count = tx_state.count + 3'b1;
|
||||
tx_next_state.macro = DATA;
|
||||
end
|
||||
end
|
||||
PARITY: begin
|
||||
end
|
||||
STOP: begin
|
||||
tx_next_state.macro = IDLE;
|
||||
tx_next_state.count = '0;
|
||||
end
|
||||
IDLE: begin
|
||||
if (tx_flag)
|
||||
tx_next_state.macro = START;
|
||||
else
|
||||
tx_next_state.macro = IDLE;
|
||||
end
|
||||
|
||||
default:;
|
||||
endcase
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
TXD = '1;
|
||||
tx_flag_clear = '0;
|
||||
|
||||
unique case (tx_state.macro)
|
||||
START: begin
|
||||
TXD = '0;
|
||||
end
|
||||
DATA: begin
|
||||
TXD = tx_buf[tx_state.count];
|
||||
end
|
||||
PARITY: begin
|
||||
|
||||
end
|
||||
STOP: begin
|
||||
tx_flag_clear = '1;
|
||||
TXD = '1;
|
||||
end
|
||||
IDLE: begin
|
||||
TXD = '1;
|
||||
end
|
||||
|
||||
default:;
|
||||
endcase
|
||||
end
|
||||
|
||||
//basically in idle state we need to sample RXD very fast,
|
||||
//then as soon as we detect that RXD is low, we start clkdiv
|
||||
//going and then go into the start state.
|
||||
|
||||
logic [14:0] rx_clkdiv;
|
||||
|
||||
always_ff @(posedge clk_50) begin
|
||||
if (rst) begin
|
||||
rx_buf <= '0;
|
||||
rx_clkdiv <= 0;
|
||||
rx_state.macro <= IDLE;
|
||||
rx_state.count <= 3'b0;
|
||||
end else begin
|
||||
if (rx_flag_set)
|
||||
rx_flag <= '1;
|
||||
else if (rx_flag_clear)
|
||||
rx_flag <= '0;
|
||||
|
||||
if (rx_state.macro == IDLE) begin // Sample constantly in idle state
|
||||
rx_state <= rx_next_state;
|
||||
rx_clkdiv <= count/15'h2; // offset rx clock by 1/2 phase
|
||||
end else begin
|
||||
if (rx_clkdiv == count) begin // other states are as usual
|
||||
rx_clkdiv <= 0;
|
||||
rx_state <= rx_next_state;
|
||||
if (rx_state.macro == DATA)
|
||||
rx_buf[rx_state.count] = RXD;
|
||||
end else begin
|
||||
rx_clkdiv <= rx_clkdiv + 15'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
rx_next_state = rx_state;
|
||||
rx_flag_set = '0;
|
||||
|
||||
unique case (rx_state.macro)
|
||||
IDLE: begin
|
||||
if (~RXD)
|
||||
rx_next_state.macro = START;
|
||||
end
|
||||
START: begin
|
||||
rx_next_state.macro = DATA;
|
||||
rx_next_state.count = 3'b0;
|
||||
end
|
||||
DATA: begin
|
||||
if (rx_state.count == maxcount) begin
|
||||
rx_next_state.macro = STOP;
|
||||
rx_next_state.count = 3'b0;
|
||||
end else begin
|
||||
rx_next_state.count = rx_state.count + 3'b1;
|
||||
rx_next_state.macro = DATA;
|
||||
end
|
||||
end
|
||||
PARITY: begin
|
||||
end
|
||||
STOP: begin
|
||||
rx_flag_set = '1;
|
||||
rx_next_state.macro = IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,31 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2021.2.323.4.6" db_version="20212999" last_change_date="Thu Jun 9 21:34:24 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
|
||||
<efxpt:device_info>
|
||||
<efxpt:iobank_info>
|
||||
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="1B_1C" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="1D_1E" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="3A_3B_3C" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="3D_3E" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="4A" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="4B" iostd="3.3 V LVTTL / LVCMOS"/>
|
||||
<efxpt:iobank name="BR" iostd="1.2 V"/>
|
||||
<efxpt:iobank name="TL" iostd="1.2 V"/>
|
||||
<efxpt:iobank name="TR" iostd="1.2 V"/>
|
||||
</efxpt:iobank_info>
|
||||
<efxpt:ctrl_info>
|
||||
<efxpt:ctrl name="cfg" ctrl_def="CONFIG_CTRL0" clock_name="" is_clk_invert="false" cbsel_bus_name="cfg_CBSEL" config_ctrl_name="cfg_CONFIG" ena_capture_name="cfg_ENA" error_status_name="cfg_ERROR" um_signal_status_name="cfg_USR_STATUS" is_remote_update_enable="false" is_user_mode_enable="false"/>
|
||||
</efxpt:ctrl_info>
|
||||
</efxpt:device_info>
|
||||
<efxpt:gpio_info device_def="T20F256">
|
||||
<efxpt:global_unused_config state="input with weak pullup"/>
|
||||
</efxpt:gpio_info>
|
||||
<efxpt:pll_info>
|
||||
<efxpt:pll name="pll_inst1" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.00" multiplier="32" pre_divider="1" post_divider="8" reset_name="" locked_name="" is_ipfrz="false" is_bypass_lock="true">
|
||||
<efxpt:output_clock name="pll_inst1_CLKOUT0" number="0" out_divider="200" adv_out_phase_shift="0"/>
|
||||
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
|
||||
</efxpt:pll>
|
||||
</efxpt:pll_info>
|
||||
<efxpt:lvds_info/>
|
||||
<efxpt:jtag_info/>
|
||||
</efxpt:design_db>
|
||||
@@ -1,3 +0,0 @@
|
||||
{
|
||||
"migration_launch_pt": "normal"
|
||||
}
|
||||
@@ -1 +0,0 @@
|
||||
"/home/byron/Software/efinity/2021.2/bin/efx_map" --project "super6502" --root "super6502" --write-efx-verilog "/home/byron/Projects/super6502/hw/efinix_fpga/outflow/super6502.map.v" --write-premap-module "/home/byron/Projects/super6502/hw/efinix_fpga/outflow/super6502.elab.vdb" --binary-db "/home/byron/Projects/super6502/hw/efinix_fpga/super6502.vdb" --device "T20F256" --family "Trion" --mode "speed" --max_ram "-1" --max_mult "-1" --infer-clk-enable "3" --infer-sync-set-reset "1" --fanout-limit "0" --bram_output_regs_packing "1" --retiming "1" --seq_opt "1" --blast_const_operand_adders "1" --operator-sharing "0" --optimize-adder-tree "0" --mult_input_regs_packing "1" --mult_output_regs_packing "1" --veri_option "verilog_mode=sv_09,vhdl_mode=vhdl_2008" --work-dir "/home/byron/Projects/super6502/hw/efinix_fpga/work_syn" --output-dir "/home/byron/Projects/super6502/hw/efinix_fpga/outflow" --project-xml "/home/byron/Projects/super6502/hw/efinix_fpga/super6502.xml" --I "/home/byron/Projects/super6502/hw/efinix_fpga" --I "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram"
|
||||
Reference in New Issue
Block a user