Byron Lathi
|
532364b8d2
|
remove sd from regular sim
Figure out how to do this later
|
2023-10-06 22:08:40 -07:00 |
|
Byron Lathi
|
fe72a4e9ea
|
Remove dependency on file, since its created anyway
|
2023-10-06 13:21:54 -07:00 |
|
Byron Lathi
|
d27e442d5e
|
Use REPO_TOP in script, call script from makefile
|
2023-10-06 13:18:36 -07:00 |
|
Byron Lathi
|
a5ff9fb5da
|
Update verilog sd
|
2023-10-06 12:46:29 -07:00 |
|
Byron Lathi
|
a3e0ab0e1e
|
Use 8 bit memory !! Will eat all your RAM!
Figure out a better way to load memories that doesn't immediately oom
you.
|
2023-10-06 07:28:34 -07:00 |
|
Byron Lathi
|
2b98ad1522
|
Increase sim time to get into sd block reads
|
2023-10-04 22:50:55 -07:00 |
|
Byron Lathi
|
e6e3044f25
|
update sd emulator
|
2023-10-04 20:27:25 -07:00 |
|
Byron Lathi
|
6a684f62f8
|
Remove another wait, update sd emulator
|
2023-10-04 20:24:56 -07:00 |
|
Byron Lathi
|
019b9c8120
|
Update sd, remove wait state
|
2023-10-04 19:11:45 -07:00 |
|
Byron Lathi
|
c1f7b33dda
|
Update sd card emu
|
2023-10-03 23:08:56 -07:00 |
|
Byron Lathi
|
3a211faed7
|
Don't have sd wait in simulation
need to figure out how to set that RTL_SIM flag only when we are
compiling code for the sim
also bro the sim is like 8000x slower than irl.
|
2023-09-30 17:40:01 -07:00 |
|
Byron Lathi
|
cc32430f2a
|
Refactor makefile, update verilog-sd-emulator
|
2023-09-29 23:48:28 -07:00 |
|
Byron Lathi
|
913351efd4
|
Add sd emulator as submodule
|
2023-09-28 23:09:47 -07:00 |
|
Byron Lathi
|
62967aa88d
|
Resolve "Add build check to CI"
|
2023-09-29 05:14:52 +00:00 |
|
Byron Lathi
|
4d0abbb508
|
Add sim uart
|
2023-09-27 22:15:27 -07:00 |
|
Byron Lathi
|
9e19a1eb72
|
Disable sdr debug, initialize uart status
|
2023-09-27 21:14:09 -07:00 |
|
Byron Lathi
|
ec4c3bab86
|
Update verilog-6502 bslathi19/verilog-6502@aaf4c084ef
|
2023-09-26 23:15:22 -07:00 |
|
Byron Lathi
|
915188e8f1
|
New test program that causes the error
|
2023-09-26 18:23:01 -07:00 |
|
Byron Lathi
|
c2dd5d616b
|
Gate rdy behind sdram_cs #28
|
2023-09-25 23:45:23 -07:00 |
|
Byron Lathi
|
4ee21f23b6
|
Up the sim time
|
2023-09-25 19:13:06 -07:00 |
|
Byron Lathi
|
95e05292cc
|
Fix clocks, define RTL_SIM
|
2023-09-24 23:58:32 -07:00 |
|
Byron Lathi
|
be68b4c9f9
|
Change sdrclk and sysclk to have aligned rising edges
|
2023-09-24 14:53:38 -07:00 |
|
Byron Lathi
|
3fcfa4d3ac
|
Add REPO_TOP env var
|
2023-09-24 10:35:17 -07:00 |
|
Byron Lathi
|
9bd031e35e
|
Add support for test programs
|
2023-09-24 10:29:32 -07:00 |
|
Byron Lathi
|
13ea5ca71b
|
Add memory
|
2023-09-24 10:06:23 -07:00 |
|
Byron Lathi
|
d3aa195adf
|
Add updated sim cpu with fix
|
2023-09-23 10:49:44 -07:00 |
|
Byron Lathi
|
00173f4e89
|
Add submodule back
|
2023-09-23 09:59:39 -07:00 |
|
Byron Lathi
|
77dd4f1002
|
remove sim submodule
|
2023-09-23 09:59:09 -07:00 |
|
Byron Lathi
|
bc0ab7eb54
|
Fix infinite loop
|
2023-09-22 19:46:25 -07:00 |
|
Byron Lathi
|
5e03795c09
|
Get something simulated
Infinite loop being caused somewhere
|
2023-09-21 23:22:17 -07:00 |
|
Byron Lathi
|
1f503b2d80
|
update sim environment
|
2023-09-21 20:35:52 -07:00 |
|
Byron Lathi
|
e50203dd3e
|
Add generic SDR
|
2023-09-21 19:23:31 -07:00 |
|
Byron Lathi
|
d37e32ec64
|
Add sim cpu
|
2023-09-18 23:27:54 -07:00 |
|
Byron Lathi
|
5ca5fca29b
|
Get SD card working in SPI
|
2023-07-23 14:55:14 -07:00 |
|
Byron Lathi
|
6a1a76db35
|
Implement basic SPI controller
|
2023-07-21 23:01:37 -07:00 |
|
Byron Lathi
|
85f12c75f1
|
Start spi controller and tb
|
2023-07-21 22:10:39 -07:00 |
|
Byron Lathi
|
9a2f0a4bb4
|
Create interrupt controller
|
2023-01-03 14:50:45 -05:00 |
|
Byron Lathi
|
34afd3875c
|
Add timer and testbench
|
2022-12-29 11:14:32 -05:00 |
|