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bslathi19
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super6502
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e50203dd3ede3ad47e9f24c5923328ae0ec103c6
super6502
/
hw
/
efinix_fpga
/
simulation
History
Byron Lathi
e50203dd3e
Add generic SDR
2023-09-21 19:23:31 -07:00
..
verilog-6502
@
a5f605d00d
Add sim cpu
2023-09-18 23:27:54 -07:00
generic_sdr.v
Add generic SDR
2023-09-21 19:23:31 -07:00
interrupt_controller_tb.sv
Create interrupt controller
2023-01-03 14:50:45 -05:00
Makefile
Implement basic SPI controller
2023-07-21 23:01:37 -07:00
sim_top.sv
Add sim cpu
2023-09-18 23:27:54 -07:00
spi_controller_tb.sv
Get SD card working in SPI
2023-07-23 14:55:14 -07:00
super6502_sdram_controller_define.vh
Add generic SDR
2023-09-21 19:23:31 -07:00
timer_tb.sv
Add timer and testbench
2022-12-29 11:14:32 -05:00