Alex Forencich
|
84fb93b5c3
|
example: Add signal sync timing constraints to example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 16:04:32 -08:00 |
|
Alex Forencich
|
7047cb5c4f
|
eth: Tie off transceiver control signals during simulation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-24 16:28:59 -08:00 |
|
Alex Forencich
|
27033384d9
|
example: Update GPIO constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-23 16:24:15 -08:00 |
|
Alex Forencich
|
75a746333e
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 23:36:13 -08:00 |
|
Alex Forencich
|
db8b1fc27e
|
example/VCU108: Add 25G MACs on QSFP28 port on VCU108
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 22:33:54 -08:00 |
|
Alex Forencich
|
a56a33abc9
|
examples: Add notes on required licenses
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-19 12:02:07 -08:00 |
|
Alex Forencich
|
8241f33d47
|
example/VCU108: Example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-18 18:13:10 -08:00 |
|
Alex Forencich
|
c7b79f9afb
|
example/VCU108: Add example design for VCU108
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-18 15:14:36 -08:00 |
|