bslathi19
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  • Joined on 2025-11-07
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bslathi19 pushed to taxi_apb at bslathi19/PeakRDL-BusDecoder 2026-02-03 22:01:47 -08:00
3f39cac8f4 Gate assertions behind "PEAKRDL_ASSERTIONS define"
fbe0f1898b Add taxi apb interface
36ec8b9715 update lock
244bd8d773 revamp docs
bad845d15e Fix/better spec enforcing (#41)
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bslathi19 created branch master in bslathi19/creditcardle 2026-01-24 21:56:51 -08:00
bslathi19 pushed to master at bslathi19/creditcardle 2026-01-24 21:56:51 -08:00
bffc50aef0 Proof of concept
bslathi19 created repository bslathi19/creditcardle 2026-01-24 21:56:38 -08:00
bslathi19 pushed to master at bslathi19/crypto 2026-01-18 21:59:04 -08:00
9b40c88673 Whatever I was working on
bslathi19 pushed to master at bslathi19/crypto 2026-01-18 20:41:48 -08:00
d5035c6c81 Add poly1305 stage
2102cb41f4 Fix bug where top 2 bits were getting lost in the modulo
d6a062baa0 Make modular mult work
ad257f4220 Add mult, but it doesn't quite work
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bslathi19 pushed to master at bslathi19/wireguard_fpga 2026-01-18 01:32:48 -08:00
a76a054387 Add upstream ip check
098ba2e2cd Add skeletons
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bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-01-18 01:30:36 -08:00
62da198a76 dma: Remove extraneous comma
bslathi19 pushed to master at bslathi19/wireguard_fpga 2026-01-17 23:20:00 -08:00
3d64d3d0ba Add top docs
bslathi19 pushed to master at bslathi19/wireguard_fpga 2026-01-17 22:45:57 -08:00
b40f8b02e4 add submodules
bslathi19 created repository bslathi19/wireguard_fpga 2026-01-17 22:39:04 -08:00
bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-01-17 19:33:56 -08:00
8328f50673 lss: Add I2C slave APB master module and testbench
9e8925de39 lss: Tie off unused interface signals
9e336fbdd5 Update readme
bedd85d7f6 Update readme
be40d3ac2d eth: Update example design readme
Compare 53 commits »
bslathi19 commented on issue bslathi19/alibaba_pcie#4 2025-11-23 23:15:22 -08:00
FPGA error when trying to send the ethernet packet

Somehow after sending the read DMA, everything comes back as all 1s. What happens there?

bslathi19 opened issue bslathi19/alibaba_pcie#4 2025-11-23 23:14:52 -08:00
FPGA error when trying to send the ethernet packet
bslathi19 pushed to master at bslathi19/alibaba_pcie 2025-11-23 23:12:20 -08:00
5e3be70f43 Add more register printout
bslathi19 pushed to master at bslathi19/alibaba_pcie 2025-11-23 23:06:24 -08:00
f4aa00ffa0 Fix register printout
bslathi19 pushed to master at bslathi19/alibaba_pcie 2025-11-23 22:59:01 -08:00
187f551b2b Update test code
bslathi19 pushed to master at bslathi19/alibaba_pcie 2025-11-23 22:58:40 -08:00
fab665b765 Update test code
bslathi19 pushed to master at bslathi19/alibaba_pcie 2025-11-23 22:03:04 -08:00
3419fd6a61 Update regs
bslathi19 pushed to master at bslathi19/PeakRDL-python-regmap 2025-11-23 19:44:06 -08:00