bslathi19
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  • Joined on 2025-11-07
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bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-24 20:30:51 -07:00
cdbb6a9720 Get it to ACTUALLY compile :)
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-24 20:09:19 -07:00
6c6c3d295b Add design doc
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-24 20:06:24 -07:00
a21cc4241a Get it to compile at least
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-24 17:13:38 -07:00
151643b2ad Get it working more
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-24 15:54:04 -07:00
61ee654b18 Get it roughly working
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-22 23:54:50 -07:00
aa8c4a64df First shot at happy path
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-22 22:28:17 -07:00
df25550c8a Add cache arrays and test
3ea31e40aa Last commit before I nuke it
8fd83c2563 Get it to kinda work
Compare 3 commits »
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-16 16:55:41 -07:00
62a3408eb7 Add some stuff related to cache
bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-05-12 18:41:00 -07:00
3951a565b5 Update readme
39a53f0dd7 cndm: Update designs
09c583c7be cndm_proto: Update designs
3541463c91 eth: Update example designs
0745952e14 eth: Fix testbench
Compare 57 commits »
bslathi19 commented on issue bslathi19/verilog6502#3 2026-05-09 17:18:25 -07:00
embedded vs application processor

Actually lets just make the L1 direct mapped. Thats the easiest way to ensure that the cpu can run fast enough, even if there is some thrashing.

bslathi19 commented on issue bslathi19/verilog6502#3 2026-05-09 16:50:48 -07:00
embedded vs application processor

It is very important that the lowest level cache have 0 cycle latency (aka 1 cycle access). the 6502 relies on memory accessing being extremely fast because of its lack of registers.

For cache…

bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-09 16:04:11 -07:00
042d7724ff Move everything around
bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-09 16:00:41 -07:00
9e174a4f02 Move everything around
bslathi19 commented on issue bslathi19/verilog6502#3 2026-05-09 15:55:14 -07:00
embedded vs application processor

We need to create a simple MMU which has cache settings for each page. Page 0 contains zero page, so should probably always be cached. However this has considerations for later if we do multitaskin…

bslathi19 pushed to blathi/soc_core at bslathi19/verilog6502 2026-05-09 15:44:41 -07:00
bslathi19 created branch blathi/soc_core in bslathi19/verilog6502 2026-05-09 15:44:40 -07:00
bslathi19 opened issue bslathi19/verilog6502#3 2026-05-09 15:43:22 -07:00
embedded vs application processor
bslathi19 closed issue bslathi19/verilog6502#1 2026-05-09 15:34:23 -07:00
32 Bit address support
bslathi19 deleted branch 32bit from bslathi19/verilog6502 2026-05-09 15:34:03 -07:00
bslathi19 merged pull request bslathi19/verilog6502#2 2026-05-09 15:34:02 -07:00
32bit