bslathi19

bslathi19 pushed to master at bslathi19/fpga6502

2026-04-18 19:20:00 -07:00

470bbc39ec Grand refactor

bslathi19 pushed to master at bslathi19/fpga6502

2026-04-18 18:55:45 -07:00

ef6b5f0669 Factor out verilog6502 into its own submodule

bslathi19 pushed to master at bslathi19/verilog6502

2026-04-18 18:55:12 -07:00

06f933fa56 Factor out verilog-6502 submodule

bslathi19 created branch master in bslathi19/verilog6502

2026-04-18 18:50:48 -07:00

bslathi19 pushed to master at bslathi19/verilog6502

2026-04-18 18:50:48 -07:00

db61ca2d74 Create project

bslathi19 created repository bslathi19/verilog6502

2026-04-18 18:50:40 -07:00

bslathi19 pushed to master at bslathi19/fpga6502

2026-04-18 18:40:35 -07:00

048af1c341 Add external memory

bslathi19 created branch master in bslathi19/fpga6502

2026-04-18 16:19:47 -07:00

bslathi19 pushed to master at bslathi19/fpga6502

2026-04-18 16:19:47 -07:00

756b96d9e2 Kinda working

50f8791588 initial commit

bslathi19 created repository bslathi19/fpga6502

2026-04-18 16:19:26 -07:00

bslathi19 pushed to master at third-party/verilog-6502

2026-04-18 16:02:50 -07:00

8f19e45b40 Add WAI instruction

bslathi19 created branch master in third-party/verilog-6502

2026-04-18 16:02:23 -07:00

bslathi19 pushed to master at third-party/verilog-6502

2026-04-18 16:02:23 -07:00

ef2cc5ab45 Merge pull request #1 from willisblackburn/master

6b47307d48 Applied fix to DIHOLD logic that was already applied to original cpu.v core

a5f605d00d 65C02: fix a bug with TSB/TRB when RDY used

4f141c7a13 Merge remote-tracking branch 'upstream/master'

fec47c5427 Fix synthesis warnings, add SYNC output

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bslathi19 created repository third-party/verilog-6502

2026-04-18 16:01:46 -07:00

bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-04-07 20:48:44 -07:00

1fe508a6bf Update readme

2ae6e22c2c cndm: Add support for Napatech NT200A01/NT200A02

cf9c5d5ff3 eth: Fix NT200A01/NT200A02 XDC

fb9757106d cndm: Clean up multiple quad handling

bbe4353c3a eth: Fix Alveo example design UART handling

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bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-04-05 20:08:44 -07:00

32ed8d68a3 Update readme

5a066e87b8 cndm: Initial commit of DPDK PMD

ae69d16b93 cndm: Fix some allocation failure handling paths

924f41c0ff cndm: Fix bug in datapath manager state progression

5b14329483 axi: Clean up user signal width handling in AXI RAM IF modules

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bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-03-10 19:13:07 -07:00

962950a1e3 cndm: Use event queues in driver

d7eb1b21a2 cndm: Use event queues in driver model

c7279a1ea2 cndm: Add support for event queues

ed61857bc3 cndm: Move interrupt handling out of CQ

2ea3c204de cndm: Rework queue notification mechanism to eliminate ream race

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bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-03-09 02:33:06 -07:00

50ba1d4c89 cndm: Make IRQ assignments configurable, add IRQ rate limiter

8773672f26 cndm: Board-level parameter cleanup

9af793edc6 cndm: Parameter cleanup

2bb2710bbd pcie: Add IRQ rate limit module and testbench

86b9947794 stats: Clean up array init

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bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-03-06 16:33:06 -08:00

ce8da1bc59 cndm: Fully share SQ/RQ HW resources

d0c9ae0637 cndm: Avoid using parameters from interfaces defined in the same module

a46b012c91 cndm: Widen internal datapath to prevent CDC-related bottlenecks

595d744aa4 cndm: Add qtype field to queue state to enable sharing

8263ebab24 cndm: Move SQ/RQ state into distributed RAM

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bslathi19 synced commits to master at bslathi19/taxi from mirror 2026-03-04 15:33:07 -08:00

f8f73ea570 cndm: Reorganize driver

9f56b9febd cndm: Reorganize driver model

6bf7240686 cndm: Rework desc/cpl mux/demux logic, add support for CQNs, implement queue allocation

8494e734a8 axis: Add TID_ROUTE parameter to taxi_axis_demux to faciliate routing replies by TID

4d8f0cfece cndm: Move control registers out of port module

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